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[176.171.212.97]) by smtp.gmail.com with ESMTPSA id w10-20020adfec4a000000b0032d2f09d991sm1461745wrn.33.2023.10.20.04.11.56 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 20 Oct 2023 04:11:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1697800318; x=1698405118; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=dKz6RVZSJf4qXCa2lKtHPOtLSVsJlJBrb9RFA879h2M=; b=sgHS3uTrI754IYwy/y5qPdrWANY+c52p+vbifdoOLzu23WyoRgkSER/xKTGcz6ySw1 qGJzjIzBEy6/EQWSwsscaXeo7Ggp9eKCs3IP8Yl6uzuKgsVskR4BtqVuMrtOEotjx5E4 W+zU7NveojfVGT46YcUQBiqGDkuCDUOQxZmXT9zJFTMrRNYomROwheFPVIfOhQunkm0N rHGOC9Vkh+GgbTSOL7SHl3dEHeKUs1SYgKcHsz1SGmirvFBAE34osQ/DAfn3T9ZDbXyo hzDvO8s1YEeYgk+GNIDu0GA0racPKFCupp4JD+JQwosIvlaHZMZ4snPOv5HXetTQ+74J zImg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697800318; x=1698405118; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=dKz6RVZSJf4qXCa2lKtHPOtLSVsJlJBrb9RFA879h2M=; b=EfFXQEtXlYlcOkuiuIYk5u9kgmdfjkvM8l/mPxkugc4+WbEDbLlLrjRqy3PZzaqcJN TRMQFts9HGXaO0PgJom4GavKxrFq1GbiFnBoHfmw/oUt+SJ/vbz8pvg2oJjmH+fABqYs E0wwWSc8ZwrYE0fOurSqemZvhgzNIuzNxC97j5FrR+WuAxDmLgjoF0P+tU9BcVTFRHZA vAtn12QJ3IbovjXU1Br8CIQXyrqmJ9endJL1x2vpvAxgg2uiB/h6IxFF2uo3lKDsNDE0 vcDZH65p0Hw5wbXVbmjL2HBlQpkbJ3dmoABe/dVyzEt5NpF9OpmHV8wJXVvKtd4ts/n9 ZKYQ== X-Gm-Message-State: AOJu0YyZ7VHrr8dTMkRX/tyvh4q+nLS1vbH2SndzjuSkr3nVDfCj+4nv 1WDhMQd7ADfPUTJfmRJFWes8PlS01dJO1mLq1hU= X-Google-Smtp-Source: AGHT+IHNLM9MIE9dmLCIwoICNvPyf4JrGzR6QfbWSDiHVe8pEbEX4mxFs0iqqH1vAgczLrKpCDoNwg== X-Received: by 2002:ac2:5233:0:b0:506:899d:1994 with SMTP id i19-20020ac25233000000b00506899d1994mr977816lfl.52.1697800317978; Fri, 20 Oct 2023 04:11:57 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Cameron Esfahani , Zhao Liu , Roman Bolshakov , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 3/3] target/i386/hvf: Rename 'X86CPU *x86_cpu' variable as 'cpu' Date: Fri, 20 Oct 2023 13:11:36 +0200 Message-ID: <20231020111136.44401-4-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231020111136.44401-1-philmd@linaro.org> References: <20231020111136.44401-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::133; envelope-from=philmd@linaro.org; helo=mail-lf1-x133.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697800347176100008 Follow the naming used by other files in target/i386/. No functional changes. Suggested-by: Zhao Liu Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Zhao Liu --- target/i386/hvf/x86_emu.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/target/i386/hvf/x86_emu.c b/target/i386/hvf/x86_emu.c index 5b82e84778..3a3f0a50d0 100644 --- a/target/i386/hvf/x86_emu.c +++ b/target/i386/hvf/x86_emu.c @@ -665,7 +665,7 @@ static void exec_lods(CPUX86State *env, struct x86_deco= de *decode) =20 void simulate_rdmsr(CPUX86State *env) { - X86CPU *x86_cpu =3D env_archcpu(env); + X86CPU *cpu =3D env_archcpu(env); CPUState *cs =3D env_cpu(env); uint32_t msr =3D ECX(env); uint64_t val =3D 0; @@ -675,10 +675,10 @@ void simulate_rdmsr(CPUX86State *env) val =3D rdtscp() + rvmcs(cs->accel->fd, VMCS_TSC_OFFSET); break; case MSR_IA32_APICBASE: - val =3D cpu_get_apic_base(x86_cpu->apic_state); + val =3D cpu_get_apic_base(cpu->apic_state); break; case MSR_IA32_UCODE_REV: - val =3D x86_cpu->ucode_rev; + val =3D cpu->ucode_rev; break; case MSR_EFER: val =3D rvmcs(cs->accel->fd, VMCS_GUEST_IA32_EFER); @@ -766,7 +766,7 @@ static void exec_rdmsr(CPUX86State *env, struct x86_dec= ode *decode) =20 void simulate_wrmsr(CPUX86State *env) { - X86CPU *x86_cpu =3D env_archcpu(env); + X86CPU *cpu =3D env_archcpu(env); CPUState *cs =3D env_cpu(env); uint32_t msr =3D ECX(env); uint64_t data =3D ((uint64_t)EDX(env) << 32) | EAX(env); @@ -775,7 +775,7 @@ void simulate_wrmsr(CPUX86State *env) case MSR_IA32_TSC: break; case MSR_IA32_APICBASE: - cpu_set_apic_base(x86_cpu->apic_state, data); + cpu_set_apic_base(cpu->apic_state, data); break; case MSR_FSBASE: wvmcs(cs->accel->fd, VMCS_GUEST_FS_BASE, data); @@ -1419,8 +1419,8 @@ static void init_cmd_handler() =20 void load_regs(CPUState *cs) { - X86CPU *x86_cpu =3D X86_CPU(cs); - CPUX86State *env =3D &x86_cpu->env; + X86CPU *cpu =3D X86_CPU(cs); + CPUX86State *env =3D &cpu->env; =20 int i =3D 0; RRX(env, R_EAX) =3D rreg(cs->accel->fd, HV_X86_RAX); @@ -1442,8 +1442,8 @@ void load_regs(CPUState *cs) =20 void store_regs(CPUState *cs) { - X86CPU *x86_cpu =3D X86_CPU(cs); - CPUX86State *env =3D &x86_cpu->env; + X86CPU *cpu =3D X86_CPU(cs); + CPUX86State *env =3D &cpu->env; =20 int i =3D 0; wreg(cs->accel->fd, HV_X86_RAX, RAX(env)); --=20 2.41.0