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No functional changes. Suggested-by: Zhao Liu Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Zhao Liu --- target/i386/hvf/x86_emu.c | 92 +++++++++++++++++++-------------------- 1 file changed, 46 insertions(+), 46 deletions(-) diff --git a/target/i386/hvf/x86_emu.c b/target/i386/hvf/x86_emu.c index cd7ef30126..5b82e84778 100644 --- a/target/i386/hvf/x86_emu.c +++ b/target/i386/hvf/x86_emu.c @@ -45,7 +45,7 @@ #include "vmcs.h" #include "vmx.h" =20 -void hvf_handle_io(CPUState *cpu, uint16_t port, void *data, +void hvf_handle_io(CPUState *cs, uint16_t port, void *data, int direction, int size, uint32_t count); =20 #define EXEC_2OP_FLAGS_CMD(env, decode, cmd, FLAGS_FUNC, save_res) \ @@ -666,13 +666,13 @@ static void exec_lods(CPUX86State *env, struct x86_de= code *decode) void simulate_rdmsr(CPUX86State *env) { X86CPU *x86_cpu =3D env_archcpu(env); - CPUState *cpu =3D env_cpu(env); + CPUState *cs =3D env_cpu(env); uint32_t msr =3D ECX(env); uint64_t val =3D 0; =20 switch (msr) { case MSR_IA32_TSC: - val =3D rdtscp() + rvmcs(cpu->accel->fd, VMCS_TSC_OFFSET); + val =3D rdtscp() + rvmcs(cs->accel->fd, VMCS_TSC_OFFSET); break; case MSR_IA32_APICBASE: val =3D cpu_get_apic_base(x86_cpu->apic_state); @@ -681,16 +681,16 @@ void simulate_rdmsr(CPUX86State *env) val =3D x86_cpu->ucode_rev; break; case MSR_EFER: - val =3D rvmcs(cpu->accel->fd, VMCS_GUEST_IA32_EFER); + val =3D rvmcs(cs->accel->fd, VMCS_GUEST_IA32_EFER); break; case MSR_FSBASE: - val =3D rvmcs(cpu->accel->fd, VMCS_GUEST_FS_BASE); + val =3D rvmcs(cs->accel->fd, VMCS_GUEST_FS_BASE); break; case MSR_GSBASE: - val =3D rvmcs(cpu->accel->fd, VMCS_GUEST_GS_BASE); + val =3D rvmcs(cs->accel->fd, VMCS_GUEST_GS_BASE); break; case MSR_KERNELGSBASE: - val =3D rvmcs(cpu->accel->fd, VMCS_HOST_FS_BASE); + val =3D rvmcs(cs->accel->fd, VMCS_HOST_FS_BASE); break; case MSR_STAR: abort(); @@ -745,8 +745,8 @@ void simulate_rdmsr(CPUX86State *env) val =3D env->mtrr_deftype; break; case MSR_CORE_THREAD_COUNT: - val =3D cpu->nr_threads * cpu->nr_cores; /* thread count, bits 15= ..0 */ - val |=3D ((uint32_t)cpu->nr_cores << 16); /* core count, bits 31..= 16 */ + val =3D cs->nr_threads * cs->nr_cores; /* thread count, bits 15..= 0 */ + val |=3D ((uint32_t)cs->nr_cores << 16); /* core count, bits 31..1= 6 */ break; default: /* fprintf(stderr, "%s: unknown msr 0x%x\n", __func__, msr); */ @@ -767,7 +767,7 @@ static void exec_rdmsr(CPUX86State *env, struct x86_dec= ode *decode) void simulate_wrmsr(CPUX86State *env) { X86CPU *x86_cpu =3D env_archcpu(env); - CPUState *cpu =3D env_cpu(env); + CPUState *cs =3D env_cpu(env); uint32_t msr =3D ECX(env); uint64_t data =3D ((uint64_t)EDX(env) << 32) | EAX(env); =20 @@ -778,13 +778,13 @@ void simulate_wrmsr(CPUX86State *env) cpu_set_apic_base(x86_cpu->apic_state, data); break; case MSR_FSBASE: - wvmcs(cpu->accel->fd, VMCS_GUEST_FS_BASE, data); + wvmcs(cs->accel->fd, VMCS_GUEST_FS_BASE, data); break; case MSR_GSBASE: - wvmcs(cpu->accel->fd, VMCS_GUEST_GS_BASE, data); + wvmcs(cs->accel->fd, VMCS_GUEST_GS_BASE, data); break; case MSR_KERNELGSBASE: - wvmcs(cpu->accel->fd, VMCS_HOST_FS_BASE, data); + wvmcs(cs->accel->fd, VMCS_HOST_FS_BASE, data); break; case MSR_STAR: abort(); @@ -796,10 +796,10 @@ void simulate_wrmsr(CPUX86State *env) abort(); break; case MSR_EFER: - /*printf("new efer %llx\n", EFER(cpu));*/ - wvmcs(cpu->accel->fd, VMCS_GUEST_IA32_EFER, data); + /*printf("new efer %llx\n", EFER(cs));*/ + wvmcs(cs->accel->fd, VMCS_GUEST_IA32_EFER, data); if (data & MSR_EFER_NXE) { - hv_vcpu_invalidate_tlb(cpu->accel->fd); + hv_vcpu_invalidate_tlb(cs->accel->fd); } break; case MSR_MTRRphysBase(0): @@ -848,9 +848,9 @@ void simulate_wrmsr(CPUX86State *env) =20 /* Related to support known hypervisor interface */ /* if (g_hypervisor_iface) - g_hypervisor_iface->wrmsr_handler(cpu, msr, data); + g_hypervisor_iface->wrmsr_handler(cs, msr, data); =20 - printf("write msr %llx\n", RCX(cpu));*/ + printf("write msr %llx\n", RCX(cs));*/ } =20 static void exec_wrmsr(CPUX86State *env, struct x86_decode *decode) @@ -1417,56 +1417,56 @@ static void init_cmd_handler() } } =20 -void load_regs(CPUState *cpu) +void load_regs(CPUState *cs) { - X86CPU *x86_cpu =3D X86_CPU(cpu); + X86CPU *x86_cpu =3D X86_CPU(cs); CPUX86State *env =3D &x86_cpu->env; =20 int i =3D 0; - RRX(env, R_EAX) =3D rreg(cpu->accel->fd, HV_X86_RAX); - RRX(env, R_EBX) =3D rreg(cpu->accel->fd, HV_X86_RBX); - RRX(env, R_ECX) =3D rreg(cpu->accel->fd, HV_X86_RCX); - RRX(env, R_EDX) =3D rreg(cpu->accel->fd, HV_X86_RDX); - RRX(env, R_ESI) =3D rreg(cpu->accel->fd, HV_X86_RSI); - RRX(env, R_EDI) =3D rreg(cpu->accel->fd, HV_X86_RDI); - RRX(env, R_ESP) =3D rreg(cpu->accel->fd, HV_X86_RSP); - RRX(env, R_EBP) =3D rreg(cpu->accel->fd, HV_X86_RBP); + RRX(env, R_EAX) =3D rreg(cs->accel->fd, HV_X86_RAX); + RRX(env, R_EBX) =3D rreg(cs->accel->fd, HV_X86_RBX); + RRX(env, R_ECX) =3D rreg(cs->accel->fd, HV_X86_RCX); + RRX(env, R_EDX) =3D rreg(cs->accel->fd, HV_X86_RDX); + RRX(env, R_ESI) =3D rreg(cs->accel->fd, HV_X86_RSI); + RRX(env, R_EDI) =3D rreg(cs->accel->fd, HV_X86_RDI); + RRX(env, R_ESP) =3D rreg(cs->accel->fd, HV_X86_RSP); + RRX(env, R_EBP) =3D rreg(cs->accel->fd, HV_X86_RBP); for (i =3D 8; i < 16; i++) { - RRX(env, i) =3D rreg(cpu->accel->fd, HV_X86_RAX + i); + RRX(env, i) =3D rreg(cs->accel->fd, HV_X86_RAX + i); } =20 - env->eflags =3D rreg(cpu->accel->fd, HV_X86_RFLAGS); + env->eflags =3D rreg(cs->accel->fd, HV_X86_RFLAGS); rflags_to_lflags(env); - env->eip =3D rreg(cpu->accel->fd, HV_X86_RIP); + env->eip =3D rreg(cs->accel->fd, HV_X86_RIP); } =20 -void store_regs(CPUState *cpu) +void store_regs(CPUState *cs) { - X86CPU *x86_cpu =3D X86_CPU(cpu); + X86CPU *x86_cpu =3D X86_CPU(cs); CPUX86State *env =3D &x86_cpu->env; =20 int i =3D 0; - wreg(cpu->accel->fd, HV_X86_RAX, RAX(env)); - wreg(cpu->accel->fd, HV_X86_RBX, RBX(env)); - wreg(cpu->accel->fd, HV_X86_RCX, RCX(env)); - wreg(cpu->accel->fd, HV_X86_RDX, RDX(env)); - wreg(cpu->accel->fd, HV_X86_RSI, RSI(env)); - wreg(cpu->accel->fd, HV_X86_RDI, RDI(env)); - wreg(cpu->accel->fd, HV_X86_RBP, RBP(env)); - wreg(cpu->accel->fd, HV_X86_RSP, RSP(env)); + wreg(cs->accel->fd, HV_X86_RAX, RAX(env)); + wreg(cs->accel->fd, HV_X86_RBX, RBX(env)); + wreg(cs->accel->fd, HV_X86_RCX, RCX(env)); + wreg(cs->accel->fd, HV_X86_RDX, RDX(env)); + wreg(cs->accel->fd, HV_X86_RSI, RSI(env)); + wreg(cs->accel->fd, HV_X86_RDI, RDI(env)); + wreg(cs->accel->fd, HV_X86_RBP, RBP(env)); + wreg(cs->accel->fd, HV_X86_RSP, RSP(env)); for (i =3D 8; i < 16; i++) { - wreg(cpu->accel->fd, HV_X86_RAX + i, RRX(env, i)); + wreg(cs->accel->fd, HV_X86_RAX + i, RRX(env, i)); } =20 lflags_to_rflags(env); - wreg(cpu->accel->fd, HV_X86_RFLAGS, env->eflags); - macvm_set_rip(cpu, env->eip); + wreg(cs->accel->fd, HV_X86_RFLAGS, env->eflags); + macvm_set_rip(cs, env->eip); } =20 bool exec_instruction(CPUX86State *env, struct x86_decode *ins) { - /*if (hvf_vcpu_id(cpu)) - printf("%d, %llx: exec_instruction %s\n", hvf_vcpu_id(cpu), env->eip, + /*if (hvf_vcpu_id(cs)) + printf("%d, %llx: exec_instruction %s\n", hvf_vcpu_id(cs), env->eip, decode_cmd_to_string(ins->cmd));*/ =20 if (!_cmd_handler[ins->cmd].handler) { --=20 2.41.0