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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id d28-20020adf9b9c000000b0031f3ad17b2csm4512690wrc.52.2023.10.19.06.35.44 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Oct 2023 06:35:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1697722545; x=1698327345; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=GZd0Sp79j4a2EdYyRqKY/xWbpD0HX364iiDAlt9cITU=; b=Bth19nMlJEViACDzYZqsKdzzxGm0j7mNJgvVr44laVjHuY2UcJL1CSTd8K0XAj4w7Q DYg0Bl9xTSMwavuwxigcEsG/GpLfYZzVaKYwEdAIUqccjuZ3NYApxgNmVKbgFfIzWLIA 8paNxwwA2wEIPCkmI07MOhkgBK2y/mH4qDug8fImJ8wgaMWx64cYCjWYxVQSfV3TAvVh dLtcYRZ8hDuFVxl7JhUHKLWNS+7wJiEoiZOlDR4hgjg5Ay+r9UubE6jAnp3ea9c46D3T V0Pqs0oMfm7uvmknitro+avWCA5IyuekFdQ0FUVbTNFwp2EPYSfEhQdwh6KIDIUp9CBD HPuA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697722545; x=1698327345; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=GZd0Sp79j4a2EdYyRqKY/xWbpD0HX364iiDAlt9cITU=; b=YboDUQSr6YoHnt55T4Tlxm9JFGvJqaVoCaDRas0k3PKPMD3B+DbqU/GawGcxZEcV7R nT5owsPC9y30j4o3BqWCQ6W/irJ971hkiLOiTpAstUt1xuQRor93dqt47/JT7Vn2FPEh ygxFDV0YF3y0GTulwUrn8q/GKoAc1ccqDz4plmFWbkbB6ZPaCMNPzPnNn9inlRA8Nj8z WN59kYeE74irNvyEJIOFvI7XBeak1oK0obutLAL7OvY+o/Fnf/PpVO22j7VapKEFRLRb m/CzXXAGo2tn5xGhac5yxpEhtKL9HuBsytzCY5fFei2Z8CSQmK4P0Qpd3g4jvKT8AP2f cNtQ== X-Gm-Message-State: AOJu0Yz7DoAPAUZy40wsTGigdiMFRosYkRp7trCcM15+qbp6142xJiu9 OdZUqHAcTyQ7r9yXImylnOYEhfQ44MDP52LIRs0= X-Google-Smtp-Source: AGHT+IGzAjyYcxNLqnXq6wNSsD2eLT68h6jQI4IVJ+mclNfVNXnS1IrmiKblk3lQAs6MzacWiGlO5w== X-Received: by 2002:a05:6000:71e:b0:32d:9701:90e5 with SMTP id bs30-20020a056000071e00b0032d970190e5mr1666075wrb.34.1697722545311; Thu, 19 Oct 2023 06:35:45 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 14/24] arm/kvm: convert to kvm_get_one_reg Date: Thu, 19 Oct 2023 14:35:27 +0100 Message-Id: <20231019133537.2114929-15-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231019133537.2114929-1-peter.maydell@linaro.org> References: <20231019133537.2114929-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697722638207100001 From: Cornelia Huck We can neaten the code by switching the callers that work on a CPUstate to the kvm_get_one_reg function. Reviewed-by: Gavin Shan Signed-off-by: Cornelia Huck Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20231010142453.224369-3-cohuck@redhat.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/kvm.c | 15 +++--------- target/arm/kvm64.c | 57 ++++++++++++---------------------------------- 2 files changed, 18 insertions(+), 54 deletions(-) diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 1a8084c4601..7903e2ddde1 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -553,24 +553,19 @@ bool write_kvmstate_to_list(ARMCPU *cpu) bool ok =3D true; =20 for (i =3D 0; i < cpu->cpreg_array_len; i++) { - struct kvm_one_reg r; uint64_t regidx =3D cpu->cpreg_indexes[i]; uint32_t v32; int ret; =20 - r.id =3D regidx; - switch (regidx & KVM_REG_SIZE_MASK) { case KVM_REG_SIZE_U32: - r.addr =3D (uintptr_t)&v32; - ret =3D kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r); + ret =3D kvm_get_one_reg(cs, regidx, &v32); if (!ret) { cpu->cpreg_values[i] =3D v32; } break; case KVM_REG_SIZE_U64: - r.addr =3D (uintptr_t)(cpu->cpreg_values + i); - ret =3D kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r); + ret =3D kvm_get_one_reg(cs, regidx, cpu->cpreg_values + i); break; default: g_assert_not_reached(); @@ -706,17 +701,13 @@ int kvm_arm_sync_mpstate_to_qemu(ARMCPU *cpu) void kvm_arm_get_virtual_time(CPUState *cs) { ARMCPU *cpu =3D ARM_CPU(cs); - struct kvm_one_reg reg =3D { - .id =3D KVM_REG_ARM_TIMER_CNT, - .addr =3D (uintptr_t)&cpu->kvm_vtime, - }; int ret; =20 if (cpu->kvm_vtime_dirty) { return; } =20 - ret =3D kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); + ret =3D kvm_get_one_reg(cs, KVM_REG_ARM_TIMER_CNT, &cpu->kvm_vtime); if (ret) { error_report("Failed to get KVM_REG_ARM_TIMER_CNT"); abort(); diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index 047b269a791..558c0b88dd6 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -909,14 +909,11 @@ int kvm_arch_put_registers(CPUState *cs, int level) static int kvm_arch_get_fpsimd(CPUState *cs) { CPUARMState *env =3D &ARM_CPU(cs)->env; - struct kvm_one_reg reg; int i, ret; =20 for (i =3D 0; i < 32; i++) { uint64_t *q =3D aa64_vfp_qreg(env, i); - reg.id =3D AARCH64_SIMD_CORE_REG(fp_regs.vregs[i]); - reg.addr =3D (uintptr_t)q; - ret =3D kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); + ret =3D kvm_get_one_reg(cs, AARCH64_SIMD_CORE_REG(fp_regs.vregs[i]= ), q); if (ret) { return ret; } else { @@ -940,15 +937,12 @@ static int kvm_arch_get_sve(CPUState *cs) { ARMCPU *cpu =3D ARM_CPU(cs); CPUARMState *env =3D &cpu->env; - struct kvm_one_reg reg; uint64_t *r; int n, ret; =20 for (n =3D 0; n < KVM_ARM64_SVE_NUM_ZREGS; ++n) { r =3D &env->vfp.zregs[n].d[0]; - reg.addr =3D (uintptr_t)r; - reg.id =3D KVM_REG_ARM64_SVE_ZREG(n, 0); - ret =3D kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); + ret =3D kvm_get_one_reg(cs, KVM_REG_ARM64_SVE_ZREG(n, 0), r); if (ret) { return ret; } @@ -957,9 +951,7 @@ static int kvm_arch_get_sve(CPUState *cs) =20 for (n =3D 0; n < KVM_ARM64_SVE_NUM_PREGS; ++n) { r =3D &env->vfp.pregs[n].p[0]; - reg.addr =3D (uintptr_t)r; - reg.id =3D KVM_REG_ARM64_SVE_PREG(n, 0); - ret =3D kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); + ret =3D kvm_get_one_reg(cs, KVM_REG_ARM64_SVE_PREG(n, 0), r); if (ret) { return ret; } @@ -967,9 +959,7 @@ static int kvm_arch_get_sve(CPUState *cs) } =20 r =3D &env->vfp.pregs[FFR_PRED_NUM].p[0]; - reg.addr =3D (uintptr_t)r; - reg.id =3D KVM_REG_ARM64_SVE_FFR(0); - ret =3D kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); + ret =3D kvm_get_one_reg(cs, KVM_REG_ARM64_SVE_FFR(0), r); if (ret) { return ret; } @@ -980,7 +970,6 @@ static int kvm_arch_get_sve(CPUState *cs) =20 int kvm_arch_get_registers(CPUState *cs) { - struct kvm_one_reg reg; uint64_t val; unsigned int el; uint32_t fpr; @@ -990,31 +979,24 @@ int kvm_arch_get_registers(CPUState *cs) CPUARMState *env =3D &cpu->env; =20 for (i =3D 0; i < 31; i++) { - reg.id =3D AARCH64_CORE_REG(regs.regs[i]); - reg.addr =3D (uintptr_t) &env->xregs[i]; - ret =3D kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); + ret =3D kvm_get_one_reg(cs, AARCH64_CORE_REG(regs.regs[i]), + &env->xregs[i]); if (ret) { return ret; } } =20 - reg.id =3D AARCH64_CORE_REG(regs.sp); - reg.addr =3D (uintptr_t) &env->sp_el[0]; - ret =3D kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); + ret =3D kvm_get_one_reg(cs, AARCH64_CORE_REG(regs.sp), &env->sp_el[0]); if (ret) { return ret; } =20 - reg.id =3D AARCH64_CORE_REG(sp_el1); - reg.addr =3D (uintptr_t) &env->sp_el[1]; - ret =3D kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); + ret =3D kvm_get_one_reg(cs, AARCH64_CORE_REG(sp_el1), &env->sp_el[1]); if (ret) { return ret; } =20 - reg.id =3D AARCH64_CORE_REG(regs.pstate); - reg.addr =3D (uintptr_t) &val; - ret =3D kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); + ret =3D kvm_get_one_reg(cs, AARCH64_CORE_REG(regs.pstate), &val); if (ret) { return ret; } @@ -1031,9 +1013,7 @@ int kvm_arch_get_registers(CPUState *cs) */ aarch64_restore_sp(env, 1); =20 - reg.id =3D AARCH64_CORE_REG(regs.pc); - reg.addr =3D (uintptr_t) &env->pc; - ret =3D kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); + ret =3D kvm_get_one_reg(cs, AARCH64_CORE_REG(regs.pc), &env->pc); if (ret) { return ret; } @@ -1047,9 +1027,7 @@ int kvm_arch_get_registers(CPUState *cs) aarch64_sync_64_to_32(env); } =20 - reg.id =3D AARCH64_CORE_REG(elr_el1); - reg.addr =3D (uintptr_t) &env->elr_el[1]; - ret =3D kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); + ret =3D kvm_get_one_reg(cs, AARCH64_CORE_REG(elr_el1), &env->elr_el[1]= ); if (ret) { return ret; } @@ -1059,9 +1037,8 @@ int kvm_arch_get_registers(CPUState *cs) * KVM SPSRs 0-4 map to QEMU banks 1-5 */ for (i =3D 0; i < KVM_NR_SPSR; i++) { - reg.id =3D AARCH64_CORE_REG(spsr[i]); - reg.addr =3D (uintptr_t) &env->banked_spsr[i + 1]; - ret =3D kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); + ret =3D kvm_get_one_reg(cs, AARCH64_CORE_REG(spsr[i]), + &env->banked_spsr[i + 1]); if (ret) { return ret; } @@ -1082,17 +1059,13 @@ int kvm_arch_get_registers(CPUState *cs) return ret; } =20 - reg.addr =3D (uintptr_t)(&fpr); - reg.id =3D AARCH64_SIMD_CTRL_REG(fp_regs.fpsr); - ret =3D kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); + ret =3D kvm_get_one_reg(cs, AARCH64_SIMD_CTRL_REG(fp_regs.fpsr), &fpr); if (ret) { return ret; } vfp_set_fpsr(env, fpr); =20 - reg.addr =3D (uintptr_t)(&fpr); - reg.id =3D AARCH64_SIMD_CTRL_REG(fp_regs.fpcr); - ret =3D kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); + ret =3D kvm_get_one_reg(cs, AARCH64_SIMD_CTRL_REG(fp_regs.fpcr), &fpr); if (ret) { return ret; } --=20 2.34.1