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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id d28-20020adf9b9c000000b0031f3ad17b2csm4512690wrc.52.2023.10.19.06.35.44 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Oct 2023 06:35:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1697722545; x=1698327345; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=JjwEGCnWRdnzpw2/wu0zwaRKL9Af9lEaMljStQ4GHxU=; b=VOPlsts7P4ZfLZrqHVMz9DC0Y6duX7ZdW7BxaYO/13p+fBOVPvgj7BBO+ksl5JCIOI giOB9n2UhLfKbTSSqdI3npD+vfmrA/plX2eX9zkRbOHlP44yytaRihZBZZJGQctpRUfa D7nf2DJEDgIhimjgSeSi+fdryD3g/qwYuqv+joIgcMQxDWjyvephsNMIbqjFFF8+sxmJ CapHIi+An0R9P6yqxsKmy/hpfgD6/A07nZNXsnAyppjLBotG8PdQksms+EFbSuO2i6MW cbeD7WnSAPuMp8+0pCTg268PThLjkcRHp91UIDYG0U0d+/0fsiALELMtxcmBFWttegQ0 jM4g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697722545; x=1698327345; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=JjwEGCnWRdnzpw2/wu0zwaRKL9Af9lEaMljStQ4GHxU=; b=nb/HOm/ApyRFlWsGj/0YT4FOrbafMRnoGD1cedsBiBPesa5V9cjGy7lTWXbBdPmDKc ni4OOh56/81yBNM3H9oXICeszMHqmh3HfwemxeBpaLdHWNbxlt7FrN/4Gype4BgHGF1W IC/u2+2wdZxuT27hBATZokUf1W/pH5+xnGqX8ZNoLHEwVhph57HkNhsHly0Do8zPWXCI AQCj8Pro7v+b8SJQwZ5lvG+aK7pI0Cl66/ux9uokNG5hg1gAi0QohrkdGyT6m/gg9/4B b/Wxa3FsrotSeV1nVhE24IIw7idGFyNKHT4OEorLmGVvi2KIMSSpU5ZE24jDN6tJGiBT NExQ== X-Gm-Message-State: AOJu0YysC/KjunzH/ddCKJid2wRVMHRCQgCQw/AEurjO47x8a71h5Ecg j8d6KeBXCS+jk8Fe5YGQxcO2lt4VrKhViDtKUV0= X-Google-Smtp-Source: AGHT+IHIAYG/DuLyzL5PjpHPxO0ANVzt3BvpWR8rrEheFnfszxJpGWRzBuJjYAMLTbxtFc10PSHjZw== X-Received: by 2002:a5d:4fcc:0:b0:32d:ad8b:2a04 with SMTP id h12-20020a5d4fcc000000b0032dad8b2a04mr1498546wrw.14.1697722544848; Thu, 19 Oct 2023 06:35:44 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 13/24] arm/kvm: convert to kvm_set_one_reg Date: Thu, 19 Oct 2023 14:35:26 +0100 Message-Id: <20231019133537.2114929-14-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231019133537.2114929-1-peter.maydell@linaro.org> References: <20231019133537.2114929-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697722841028100025 From: Cornelia Huck We can neaten the code by switching to the kvm_set_one_reg function. Reviewed-by: Gavin Shan Signed-off-by: Cornelia Huck Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20231010142453.224369-2-cohuck@redhat.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/kvm.c | 13 +++------ target/arm/kvm64.c | 66 +++++++++++++--------------------------------- 2 files changed, 21 insertions(+), 58 deletions(-) diff --git a/target/arm/kvm.c b/target/arm/kvm.c index b66b936a958..1a8084c4601 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -589,7 +589,6 @@ bool write_list_to_kvmstate(ARMCPU *cpu, int level) bool ok =3D true; =20 for (i =3D 0; i < cpu->cpreg_array_len; i++) { - struct kvm_one_reg r; uint64_t regidx =3D cpu->cpreg_indexes[i]; uint32_t v32; int ret; @@ -598,19 +597,17 @@ bool write_list_to_kvmstate(ARMCPU *cpu, int level) continue; } =20 - r.id =3D regidx; switch (regidx & KVM_REG_SIZE_MASK) { case KVM_REG_SIZE_U32: v32 =3D cpu->cpreg_values[i]; - r.addr =3D (uintptr_t)&v32; + ret =3D kvm_set_one_reg(cs, regidx, &v32); break; case KVM_REG_SIZE_U64: - r.addr =3D (uintptr_t)(cpu->cpreg_values + i); + ret =3D kvm_set_one_reg(cs, regidx, cpu->cpreg_values + i); break; default: g_assert_not_reached(); } - ret =3D kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &r); if (ret) { /* We might fail for "unknown register" and also for * "you tried to set a register which is constant with @@ -731,17 +728,13 @@ void kvm_arm_get_virtual_time(CPUState *cs) void kvm_arm_put_virtual_time(CPUState *cs) { ARMCPU *cpu =3D ARM_CPU(cs); - struct kvm_one_reg reg =3D { - .id =3D KVM_REG_ARM_TIMER_CNT, - .addr =3D (uintptr_t)&cpu->kvm_vtime, - }; int ret; =20 if (!cpu->kvm_vtime_dirty) { return; } =20 - ret =3D kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); + ret =3D kvm_set_one_reg(cs, KVM_REG_ARM_TIMER_CNT, &cpu->kvm_vtime); if (ret) { error_report("Failed to set KVM_REG_ARM_TIMER_CNT"); abort(); diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index 5e95c496bb9..047b269a791 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -540,14 +540,10 @@ static int kvm_arm_sve_set_vls(CPUState *cs) { ARMCPU *cpu =3D ARM_CPU(cs); uint64_t vls[KVM_ARM64_SVE_VLS_WORDS] =3D { cpu->sve_vq.map }; - struct kvm_one_reg reg =3D { - .id =3D KVM_REG_ARM64_SVE_VLS, - .addr =3D (uint64_t)&vls[0], - }; =20 assert(cpu->sve_max_vq <=3D KVM_ARM64_SVE_VQ_MAX); =20 - return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); + return kvm_set_one_reg(cs, KVM_REG_ARM64_SVE_VLS, &vls[0]); } =20 #define ARM_CPU_ID_MPIDR 3, 0, 0, 0, 5 @@ -726,19 +722,17 @@ static void kvm_inject_arm_sea(CPUState *c) static int kvm_arch_put_fpsimd(CPUState *cs) { CPUARMState *env =3D &ARM_CPU(cs)->env; - struct kvm_one_reg reg; int i, ret; =20 for (i =3D 0; i < 32; i++) { uint64_t *q =3D aa64_vfp_qreg(env, i); #if HOST_BIG_ENDIAN uint64_t fp_val[2] =3D { q[1], q[0] }; - reg.addr =3D (uintptr_t)fp_val; + ret =3D kvm_set_one_reg(cs, AARCH64_SIMD_CORE_REG(fp_regs.vregs[i]= ), + fp_val); #else - reg.addr =3D (uintptr_t)q; + ret =3D kvm_set_one_reg(cs, AARCH64_SIMD_CORE_REG(fp_regs.vregs[i]= ), q); #endif - reg.id =3D AARCH64_SIMD_CORE_REG(fp_regs.vregs[i]); - ret =3D kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); if (ret) { return ret; } @@ -759,14 +753,11 @@ static int kvm_arch_put_sve(CPUState *cs) CPUARMState *env =3D &cpu->env; uint64_t tmp[ARM_MAX_VQ * 2]; uint64_t *r; - struct kvm_one_reg reg; int n, ret; =20 for (n =3D 0; n < KVM_ARM64_SVE_NUM_ZREGS; ++n) { r =3D sve_bswap64(tmp, &env->vfp.zregs[n].d[0], cpu->sve_max_vq * = 2); - reg.addr =3D (uintptr_t)r; - reg.id =3D KVM_REG_ARM64_SVE_ZREG(n, 0); - ret =3D kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); + ret =3D kvm_set_one_reg(cs, KVM_REG_ARM64_SVE_ZREG(n, 0), r); if (ret) { return ret; } @@ -775,9 +766,7 @@ static int kvm_arch_put_sve(CPUState *cs) for (n =3D 0; n < KVM_ARM64_SVE_NUM_PREGS; ++n) { r =3D sve_bswap64(tmp, r =3D &env->vfp.pregs[n].p[0], DIV_ROUND_UP(cpu->sve_max_vq * 2, 8)); - reg.addr =3D (uintptr_t)r; - reg.id =3D KVM_REG_ARM64_SVE_PREG(n, 0); - ret =3D kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); + ret =3D kvm_set_one_reg(cs, KVM_REG_ARM64_SVE_PREG(n, 0), r); if (ret) { return ret; } @@ -785,9 +774,7 @@ static int kvm_arch_put_sve(CPUState *cs) =20 r =3D sve_bswap64(tmp, &env->vfp.pregs[FFR_PRED_NUM].p[0], DIV_ROUND_UP(cpu->sve_max_vq * 2, 8)); - reg.addr =3D (uintptr_t)r; - reg.id =3D KVM_REG_ARM64_SVE_FFR(0); - ret =3D kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); + ret =3D kvm_set_one_reg(cs, KVM_REG_ARM64_SVE_FFR(0), r); if (ret) { return ret; } @@ -797,7 +784,6 @@ static int kvm_arch_put_sve(CPUState *cs) =20 int kvm_arch_put_registers(CPUState *cs, int level) { - struct kvm_one_reg reg; uint64_t val; uint32_t fpr; int i, ret; @@ -814,9 +800,8 @@ int kvm_arch_put_registers(CPUState *cs, int level) } =20 for (i =3D 0; i < 31; i++) { - reg.id =3D AARCH64_CORE_REG(regs.regs[i]); - reg.addr =3D (uintptr_t) &env->xregs[i]; - ret =3D kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); + ret =3D kvm_set_one_reg(cs, AARCH64_CORE_REG(regs.regs[i]), + &env->xregs[i]); if (ret) { return ret; } @@ -827,16 +812,12 @@ int kvm_arch_put_registers(CPUState *cs, int level) */ aarch64_save_sp(env, 1); =20 - reg.id =3D AARCH64_CORE_REG(regs.sp); - reg.addr =3D (uintptr_t) &env->sp_el[0]; - ret =3D kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); + ret =3D kvm_set_one_reg(cs, AARCH64_CORE_REG(regs.sp), &env->sp_el[0]); if (ret) { return ret; } =20 - reg.id =3D AARCH64_CORE_REG(sp_el1); - reg.addr =3D (uintptr_t) &env->sp_el[1]; - ret =3D kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); + ret =3D kvm_set_one_reg(cs, AARCH64_CORE_REG(sp_el1), &env->sp_el[1]); if (ret) { return ret; } @@ -847,23 +828,17 @@ int kvm_arch_put_registers(CPUState *cs, int level) } else { val =3D cpsr_read(env); } - reg.id =3D AARCH64_CORE_REG(regs.pstate); - reg.addr =3D (uintptr_t) &val; - ret =3D kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); + ret =3D kvm_set_one_reg(cs, AARCH64_CORE_REG(regs.pstate), &val); if (ret) { return ret; } =20 - reg.id =3D AARCH64_CORE_REG(regs.pc); - reg.addr =3D (uintptr_t) &env->pc; - ret =3D kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); + ret =3D kvm_set_one_reg(cs, AARCH64_CORE_REG(regs.pc), &env->pc); if (ret) { return ret; } =20 - reg.id =3D AARCH64_CORE_REG(elr_el1); - reg.addr =3D (uintptr_t) &env->elr_el[1]; - ret =3D kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); + ret =3D kvm_set_one_reg(cs, AARCH64_CORE_REG(elr_el1), &env->elr_el[1]= ); if (ret) { return ret; } @@ -882,9 +857,8 @@ int kvm_arch_put_registers(CPUState *cs, int level) =20 /* KVM 0-4 map to QEMU banks 1-5 */ for (i =3D 0; i < KVM_NR_SPSR; i++) { - reg.id =3D AARCH64_CORE_REG(spsr[i]); - reg.addr =3D (uintptr_t) &env->banked_spsr[i + 1]; - ret =3D kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); + ret =3D kvm_set_one_reg(cs, AARCH64_CORE_REG(spsr[i]), + &env->banked_spsr[i + 1]); if (ret) { return ret; } @@ -899,18 +873,14 @@ int kvm_arch_put_registers(CPUState *cs, int level) return ret; } =20 - reg.addr =3D (uintptr_t)(&fpr); fpr =3D vfp_get_fpsr(env); - reg.id =3D AARCH64_SIMD_CTRL_REG(fp_regs.fpsr); - ret =3D kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); + ret =3D kvm_set_one_reg(cs, AARCH64_SIMD_CTRL_REG(fp_regs.fpsr), &fpr); if (ret) { return ret; } =20 - reg.addr =3D (uintptr_t)(&fpr); fpr =3D vfp_get_fpcr(env); - reg.id =3D AARCH64_SIMD_CTRL_REG(fp_regs.fpcr); - ret =3D kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); + ret =3D kvm_set_one_reg(cs, AARCH64_SIMD_CTRL_REG(fp_regs.fpcr), &fpr); if (ret) { return ret; } --=20 2.34.1