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[176.131.216.177]) by smtp.gmail.com with ESMTPSA id r16-20020a05600c459000b00405391f485fsm4456618wmo.41.2023.10.19.06.10.07 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 19 Oct 2023 06:10:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1697721009; x=1698325809; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=RG5zLlWN/LC4pJbPVJoFLnGQz4i0tpH2bVvTXsYTeOI=; b=RWD6Xe2o+7QqJPE/q0O/ioZ6oa6/FeioX42H3ci+ZkC0xlXqvGcWUdZPtG6DohKyMM 4YXeJ/ZyYJcXuxV6Y5ANEfh1Sw/qDjFkvcpMk67/FfQDC29D31VHzpnFrGCfowrKI7BM DdVxZEetBnixBT1MLTp7waEkZ218k9hZACsybrywvFrjReWYGhNVTjjirNJWU6DUzwQ3 iKjj1szTRt7THElIGZYDXPxe5vRSjNRY34IDpCFGQIasITr6uWGtlX5mAbcxhrNe7/Si IJKKSscCj/qxnuJ71sudOtkctqbuaozrYKo7eFD1BYlxu1kibz4mggJMFNgu+5ltpHSK Ch3A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697721009; x=1698325809; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=RG5zLlWN/LC4pJbPVJoFLnGQz4i0tpH2bVvTXsYTeOI=; b=LW6m9ZdOV8a5A8kqw7Anu+SjIlNbVrH/Q5O+eqr0TeMNncvj5cN8eKdpZuVVHMBA7w 50tDYUIVjyc1IpnU+jqPJaaD0+ronBiFx873rBVLMB8k+ylD8xsA2dxLc90Ow654eEqS a5jnxOwaxFM7V1tnb0t08vQk18oB3UItKe+LnbwVgN5E5a5mfjYsjZwY4+hdM3QuHG0k Vw6M28XD2vnBUqSCLbThN3UFsIICSvrYcvIXvw14o81hx+Ra0ON73cdGBh+hyoT2FpXF QC6SpeL8YSN/UyMhqI/qUWNdPZTAeuLwuSRUKoOprjwMXpuBLRS2Ew9aos8uqwl9mzSW +7FQ== X-Gm-Message-State: AOJu0YzvVlc5M/qS3qjGvEMzouI3lpoMqytCkLxx5ZZYbpu6N/I4hv17 6VmdKfx7h0vIJxTPzs3ZA6mSW3mMuwsfuX2AsV2Ycw== X-Google-Smtp-Source: AGHT+IGguIz8HbEEBSOgkoYgF/ZH0ySW9aMvXrUwrP1ergEhLHkHT1zMRiSJKeZZiU21k24B/gca1w== X-Received: by 2002:a05:600c:a07:b0:408:3f64:6553 with SMTP id z7-20020a05600c0a0700b004083f646553mr1746777wmp.16.1697721008600; Thu, 19 Oct 2023 06:10:08 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Peter Maydell , qemu-arm@nongnu.org, Thomas Huth , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v2 7/9] hw/intc/pxa2xx: Pass CPU reference using QOM link property Date: Thu, 19 Oct 2023 15:09:22 +0200 Message-ID: <20231019130925.18744-8-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231019130925.18744-1-philmd@linaro.org> References: <20231019130925.18744-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=philmd@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697725245812100003 QOM objects shouldn't access each other internals fields except using the QOM API. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/arm/pxa2xx_pic.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/hw/arm/pxa2xx_pic.c b/hw/arm/pxa2xx_pic.c index 2eb869a605..7e180635c2 100644 --- a/hw/arm/pxa2xx_pic.c +++ b/hw/arm/pxa2xx_pic.c @@ -15,6 +15,7 @@ #include "cpu.h" #include "hw/arm/pxa.h" #include "hw/sysbus.h" +#include "hw/qdev-properties.h" #include "migration/vmstate.h" #include "qom/object.h" #include "target/arm/cpregs.h" @@ -288,7 +289,8 @@ DeviceState *pxa2xx_pic_init(hwaddr base, ARMCPU *cpu) DeviceState *dev =3D qdev_new(TYPE_PXA2XX_PIC); PXA2xxPICState *s =3D PXA2XX_PIC(dev); =20 - s->cpu =3D cpu; + object_property_set_link(OBJECT(dev), "arm-cpu", + OBJECT(cpu), &error_abort); =20 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); =20 @@ -321,11 +323,18 @@ static const VMStateDescription vmstate_pxa2xx_pic_re= gs =3D { }, }; =20 +static Property pxa2xx_pic_properties[] =3D { + DEFINE_PROP_LINK("arm-cpu", PXA2xxPICState, cpu, + TYPE_ARM_CPU, ARMCPU *), + DEFINE_PROP_END_OF_LIST(), +}; + static void pxa2xx_pic_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); ResettableClass *rc =3D RESETTABLE_CLASS(klass); =20 + device_class_set_props(dc, pxa2xx_pic_properties); dc->desc =3D "PXA2xx PIC"; dc->vmsd =3D &vmstate_pxa2xx_pic_regs; rc->phases.hold =3D pxa2xx_pic_reset_hold; --=20 2.41.0