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[176.131.216.177]) by smtp.gmail.com with ESMTPSA id bt14-20020a056000080e00b0032da4f70756sm4518629wrb.5.2023.10.19.06.10.01 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 19 Oct 2023 06:10:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1697721003; x=1698325803; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=LSmy0AQ2ctzt4sBy/4+sAM4ntN11b2Cq/iHR2Msv118=; b=qkr/v8nXIhz3SoD89Vr1W3sHlI/AXRfkyxtWvpdpwmBXUJYqE0igSD538JhtCDCkmH VKuwEPjOCELSOW0Zzbv+ZaF0SsCBB9DK0UehHrz6zPQPSs90XrOr13vZSLckpqfBkF28 5PSEviougYHkfPxPnxaP901dqXAKaScxh7yT7eVSW7+BDFfvh7wvuH2hMivvPggmLh7D +8YV5R/tRkbT+gL/Q8zVXq4JGOBWrsq8cI2VnrdDOsshG4znZrhaZBPNUUrjETme+nlG HMWSLCrnUn5bnWH8K+8UMcFcCOergOPpT56/MTEKjrNlI0iBBAuhaGwtPbOWroUr4OBI Y+tQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697721003; x=1698325803; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=LSmy0AQ2ctzt4sBy/4+sAM4ntN11b2Cq/iHR2Msv118=; b=MhRjBUWcIvauVI8cYNSpetH4bxwOQ8C0ZKEsu6xrvnqzA50cKCR0ANpnupGeqPfLXu ig9+XueZ8OwYUA7aWwThE7i42mq+qSSWnKQ1gkRnmXUTXu1p11gjFGchSQP+JKA2VtkC zQBgJpdtezVGO05LhAcbYir+mdngrwMuj0U1oajZ6ajP3QPZAjJWGR90hwi6xAhFpwfK o9J60ZRFeXEFTiQxB4ke0mQcd38fFFGvTw0SeYyYxvMbSrwTX07PrmWQnXV/ldvtpCwe 32FZa15+EjCZ7SMutPYU0v109xXEtARA66vTW7FJ8Mc92zUC9yGFsP/DxbrX13zx2xYo oaeA== X-Gm-Message-State: AOJu0YzASH5YBUbcos01WpIcFFrLHcYRA8/+PFxpAF5Kn0SEZowzYfk8 Hm6by3pWaNGENqn3xoTTuzIYnNDgTgEzGo8CngMxTw== X-Google-Smtp-Source: AGHT+IHJIUtLhRXD0auV7zNUFTyWmKx+Y0Cv9FaRsuyLBGRXNoKwf/U4fwW4KYid+DiY6wrewG6fNw== X-Received: by 2002:a05:6512:701:b0:503:655:12e7 with SMTP id b1-20020a056512070100b00503065512e7mr1356840lfs.62.1697721002787; Thu, 19 Oct 2023 06:10:02 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Peter Maydell , qemu-arm@nongnu.org, Thomas Huth , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v2 6/9] hw/intc/pxa2xx: Convert to Resettable interface Date: Thu, 19 Oct 2023 15:09:21 +0200 Message-ID: <20231019130925.18744-7-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231019130925.18744-1-philmd@linaro.org> References: <20231019130925.18744-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::136; envelope-from=philmd@linaro.org; helo=mail-lf1-x136.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697725058907100005 Factor reset code out of the DeviceRealize() handler. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/arm/pxa2xx_pic.c | 17 ++++++++++++----- 1 file changed, 12 insertions(+), 5 deletions(-) diff --git a/hw/arm/pxa2xx_pic.c b/hw/arm/pxa2xx_pic.c index 47132ab982..2eb869a605 100644 --- a/hw/arm/pxa2xx_pic.c +++ b/hw/arm/pxa2xx_pic.c @@ -271,12 +271,9 @@ static int pxa2xx_pic_post_load(void *opaque, int vers= ion_id) return 0; } =20 -DeviceState *pxa2xx_pic_init(hwaddr base, ARMCPU *cpu) +static void pxa2xx_pic_reset_hold(Object *obj) { - DeviceState *dev =3D qdev_new(TYPE_PXA2XX_PIC); - PXA2xxPICState *s =3D PXA2XX_PIC(dev); - - s->cpu =3D cpu; + PXA2xxPICState *s =3D PXA2XX_PIC(obj); =20 s->int_pending[0] =3D 0; s->int_pending[1] =3D 0; @@ -284,6 +281,14 @@ DeviceState *pxa2xx_pic_init(hwaddr base, ARMCPU *cpu) s->int_enabled[1] =3D 0; s->is_fiq[0] =3D 0; s->is_fiq[1] =3D 0; +} + +DeviceState *pxa2xx_pic_init(hwaddr base, ARMCPU *cpu) +{ + DeviceState *dev =3D qdev_new(TYPE_PXA2XX_PIC); + PXA2xxPICState *s =3D PXA2XX_PIC(dev); + + s->cpu =3D cpu; =20 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); =20 @@ -319,9 +324,11 @@ static const VMStateDescription vmstate_pxa2xx_pic_reg= s =3D { static void pxa2xx_pic_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); + ResettableClass *rc =3D RESETTABLE_CLASS(klass); =20 dc->desc =3D "PXA2xx PIC"; dc->vmsd =3D &vmstate_pxa2xx_pic_regs; + rc->phases.hold =3D pxa2xx_pic_reset_hold; } =20 static const TypeInfo pxa2xx_pic_info =3D { --=20 2.41.0