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Thu, 19 Oct 2023 03:48:12 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHWVJX0cVHDjtBovShecgySY+GnSNhB50tMah6Ktril1i2IzXK/XxG/8jiMIRLmI9UlJskGyw== X-Received: by 2002:a17:907:c16:b0:9ae:56da:6068 with SMTP id ga22-20020a1709070c1600b009ae56da6068mr1462006ejc.57.1697712491905; Thu, 19 Oct 2023 03:48:11 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Subject: [PATCH v2 17/19] target/i386: move remaining conditional operations to new decoder Date: Thu, 19 Oct 2023 12:48:05 +0200 Message-ID: <20231019104807.390468-3-pbonzini@redhat.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231019104648.389942-1-pbonzini@redhat.com> References: <20231019104648.389942-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1697712569730100001 Content-Type: text/plain; charset="utf-8" Move long-displacement Jcc, SETcc and CMOVcc to the new decoder. While filling in the tables makes the code seem longer, the new emitters are all just one line of code. Signed-off-by: Paolo Bonzini --- target/i386/tcg/decode-new.c.inc | 56 ++++++++++++++++++++++++++++++++ target/i386/tcg/decode-new.h | 1 + target/i386/tcg/emit.c.inc | 10 ++++++ target/i386/tcg/translate.c | 4 ++- 4 files changed, 70 insertions(+), 1 deletion(-) diff --git a/target/i386/tcg/decode-new.c.inc b/target/i386/tcg/decode-new.= c.inc index d0baf972208..e68f5ae068e 100644 --- a/target/i386/tcg/decode-new.c.inc +++ b/target/i386/tcg/decode-new.c.inc @@ -944,6 +944,15 @@ static const X86OpEntry opcodes_0F[256] =3D { /* Incorrectly listed as Mq,Vq in the manual */ [0x17] =3D X86_OP_ENTRY3(VMOVHPx_st, M,q, None,None, V,dq, vex5 p_00_= 66), =20 + [0x40] =3D X86_OP_ENTRY2(CMOVcc, G,v, E,v, cpuid(CMOV)), + [0x41] =3D X86_OP_ENTRY2(CMOVcc, G,v, E,v, cpuid(CMOV)), + [0x42] =3D X86_OP_ENTRY2(CMOVcc, G,v, E,v, cpuid(CMOV)), + [0x43] =3D X86_OP_ENTRY2(CMOVcc, G,v, E,v, cpuid(CMOV)), + [0x44] =3D X86_OP_ENTRY2(CMOVcc, G,v, E,v, cpuid(CMOV)), + [0x45] =3D X86_OP_ENTRY2(CMOVcc, G,v, E,v, cpuid(CMOV)), + [0x46] =3D X86_OP_ENTRY2(CMOVcc, G,v, E,v, cpuid(CMOV)), + [0x47] =3D X86_OP_ENTRY2(CMOVcc, G,v, E,v, cpuid(CMOV)), + [0x50] =3D X86_OP_ENTRY3(MOVMSK, G,y, None,None, U,x, vex7 p_00_66= ), [0x51] =3D X86_OP_GROUP3(sse_unary, V,x, H,x, W,x, vex2_rep3 p_00_66_= f3_f2), /* sqrtps */ [0x52] =3D X86_OP_GROUP3(sse_unary, V,x, H,x, W,x, vex4_rep5 p_00_f3)= , /* rsqrtps */ @@ -971,6 +980,24 @@ static const X86OpEntry opcodes_0F[256] =3D { [0x76] =3D X86_OP_ENTRY3(PCMPEQD, V,x, H,x, W,x, vex4 mmx avx2_256= p_00_66), [0x77] =3D X86_OP_GROUP0(0F77), =20 + [0x80] =3D X86_OP_ENTRYr(Jcc, J,z), + [0x81] =3D X86_OP_ENTRYr(Jcc, J,z), + [0x82] =3D X86_OP_ENTRYr(Jcc, J,z), + [0x83] =3D X86_OP_ENTRYr(Jcc, J,z), + [0x84] =3D X86_OP_ENTRYr(Jcc, J,z), + [0x85] =3D X86_OP_ENTRYr(Jcc, J,z), + [0x86] =3D X86_OP_ENTRYr(Jcc, J,z), + [0x87] =3D X86_OP_ENTRYr(Jcc, J,z), + + [0x90] =3D X86_OP_ENTRYw(SETcc, E,b), + [0x91] =3D X86_OP_ENTRYw(SETcc, E,b), + [0x92] =3D X86_OP_ENTRYw(SETcc, E,b), + [0x93] =3D X86_OP_ENTRYw(SETcc, E,b), + [0x94] =3D X86_OP_ENTRYw(SETcc, E,b), + [0x95] =3D X86_OP_ENTRYw(SETcc, E,b), + [0x96] =3D X86_OP_ENTRYw(SETcc, E,b), + [0x97] =3D X86_OP_ENTRYw(SETcc, E,b), + [0x28] =3D X86_OP_ENTRY3(MOVDQ, V,x, None,None, W,x, vex1 p_00_6= 6), /* MOVAPS */ [0x29] =3D X86_OP_ENTRY3(MOVDQ, W,x, None,None, V,x, vex1 p_00_6= 6), /* MOVAPS */ [0x2A] =3D X86_OP_GROUP0(0F2A), @@ -983,6 +1010,15 @@ static const X86OpEntry opcodes_0F[256] =3D { [0x38] =3D X86_OP_GROUP0(0F38), [0x3a] =3D X86_OP_GROUP0(0F3A), =20 + [0x48] =3D X86_OP_ENTRY2(CMOVcc, G,v, E,v, cpuid(CMOV)), + [0x49] =3D X86_OP_ENTRY2(CMOVcc, G,v, E,v, cpuid(CMOV)), + [0x4a] =3D X86_OP_ENTRY2(CMOVcc, G,v, E,v, cpuid(CMOV)), + [0x4b] =3D X86_OP_ENTRY2(CMOVcc, G,v, E,v, cpuid(CMOV)), + [0x4c] =3D X86_OP_ENTRY2(CMOVcc, G,v, E,v, cpuid(CMOV)), + [0x4d] =3D X86_OP_ENTRY2(CMOVcc, G,v, E,v, cpuid(CMOV)), + [0x4e] =3D X86_OP_ENTRY2(CMOVcc, G,v, E,v, cpuid(CMOV)), + [0x4f] =3D X86_OP_ENTRY2(CMOVcc, G,v, E,v, cpuid(CMOV)), + [0x58] =3D X86_OP_ENTRY3(VADD, V,x, H,x, W,x, vex2_rep3 p_00_66_= f3_f2), [0x59] =3D X86_OP_ENTRY3(VMUL, V,x, H,x, W,x, vex2_rep3 p_00_66_= f3_f2), [0x5a] =3D X86_OP_GROUP0(0F5A), @@ -1008,6 +1044,24 @@ static const X86OpEntry opcodes_0F[256] =3D { [0x7e] =3D X86_OP_GROUP0(0F7E), [0x7f] =3D X86_OP_GROUP0(0F7F), =20 + [0x88] =3D X86_OP_ENTRYr(Jcc, J,z), + [0x89] =3D X86_OP_ENTRYr(Jcc, J,z), + [0x8a] =3D X86_OP_ENTRYr(Jcc, J,z), + [0x8b] =3D X86_OP_ENTRYr(Jcc, J,z), + [0x8c] =3D X86_OP_ENTRYr(Jcc, J,z), + [0x8d] =3D X86_OP_ENTRYr(Jcc, J,z), + [0x8e] =3D X86_OP_ENTRYr(Jcc, J,z), + [0x8f] =3D X86_OP_ENTRYr(Jcc, J,z), + + [0x98] =3D X86_OP_ENTRYw(SETcc, E,b), + [0x99] =3D X86_OP_ENTRYw(SETcc, E,b), + [0x9a] =3D X86_OP_ENTRYw(SETcc, E,b), + [0x9b] =3D X86_OP_ENTRYw(SETcc, E,b), + [0x9c] =3D X86_OP_ENTRYw(SETcc, E,b), + [0x9d] =3D X86_OP_ENTRYw(SETcc, E,b), + [0x9e] =3D X86_OP_ENTRYw(SETcc, E,b), + [0x9f] =3D X86_OP_ENTRYw(SETcc, E,b), + [0xae] =3D X86_OP_GROUP0(group15), =20 [0xc2] =3D X86_OP_ENTRY4(VCMP, V,x, H,x, W,x, vex2_rep3 p_= 00_66_f3_f2), @@ -1743,6 +1797,8 @@ static bool has_cpuid_feature(DisasContext *s, X86CPU= IDFeature cpuid) switch (cpuid) { case X86_FEAT_None: return true; + case X86_FEAT_CMOV: + return (s->cpuid_features & CPUID_CMOV); case X86_FEAT_F16C: return (s->cpuid_ext_features & CPUID_EXT_F16C); case X86_FEAT_FMA: diff --git a/target/i386/tcg/decode-new.h b/target/i386/tcg/decode-new.h index 32396630865..119de3bf342 100644 --- a/target/i386/tcg/decode-new.h +++ b/target/i386/tcg/decode-new.h @@ -105,6 +105,7 @@ typedef enum X86CPUIDFeature { X86_FEAT_AVX2, X86_FEAT_BMI1, X86_FEAT_BMI2, + X86_FEAT_CMOV, X86_FEAT_CMPCCXADD, X86_FEAT_F16C, X86_FEAT_FMA, diff --git a/target/i386/tcg/emit.c.inc b/target/i386/tcg/emit.c.inc index 267f4fe383a..05e1fb16844 100644 --- a/target/i386/tcg/emit.c.inc +++ b/target/i386/tcg/emit.c.inc @@ -1636,6 +1636,16 @@ static void gen_Jcc(DisasContext *s, CPUX86State *en= v, X86DecodedInsn *decode) gen_jcc(s, decode->b & 0xf, decode->immediate); } =20 +static void gen_SETcc(DisasContext *s, CPUX86State *env, X86DecodedInsn *d= ecode) +{ + gen_setcc1(s, decode->b & 0xf, s->T0); +} + +static void gen_CMOVcc(DisasContext *s, CPUX86State *env, X86DecodedInsn *= decode) +{ + gen_cmovcc1(s, decode->b & 0xf, s->T0, s->T1); +} + static void gen_LAHF(DisasContext *s, CPUX86State *env, X86DecodedInsn *de= code) { if (CODE64(s) && !(s->cpuid_ext3_features & CPUID_EXT3_LAHF_LM)) { diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 2c4e680a69e..1f3cc6361c0 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -3186,7 +3186,9 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) #ifndef CONFIG_USER_ONLY use_new &=3D b <=3D limit; #endif - if (use_new && 0) { + if (use_new && + ((b >=3D 0x140 && b <=3D 0x14f) || + (b >=3D 0x180 && b <=3D 0x19f))) { disas_insn_new(s, cpu, b); return true; } --=20 2.41.0