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Thu, 19 Oct 2023 03:48:10 -0700 (PDT) X-Google-Smtp-Source: AGHT+IH56xMRwCPRo5trlv9K71mRSwMEkMwuTHovGdi4o0YkH5GZQetquo40Gg208Wzir9MlkAI9DQ== X-Received: by 2002:a17:907:2cc4:b0:9a1:c991:a521 with SMTP id hg4-20020a1709072cc400b009a1c991a521mr1340944ejc.4.1697712490569; Thu, 19 Oct 2023 03:48:10 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Subject: [PATCH v2 16/19] target/i386: move operand load and writeback out of gen_cmovcc1 Date: Thu, 19 Oct 2023 12:48:04 +0200 Message-ID: <20231019104807.390468-2-pbonzini@redhat.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231019104648.389942-1-pbonzini@redhat.com> References: <20231019104648.389942-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1697712621906100002 Content-Type: text/plain; charset="utf-8" Similar to gen_setcc1, make gen_cmovcc1 receive TCGv. This is more friendly to simultaneous implementation in the old and the new decoder. A small wart is that s->T0 of CMOV is currently the *second* argument (which would ordinarily be in T1). Therefore, the condition as to be inverted in order to overwrite s->T0 with cpu_regs[reg] if the MOV is not performed. This only applies to the old decoder, and this code will go away soon. Signed-off-by: Paolo Bonzini --- target/i386/tcg/translate.c | 20 ++++++++------------ 1 file changed, 8 insertions(+), 12 deletions(-) diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 9c799b5a980..2c4e680a69e 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -2503,26 +2503,20 @@ static void gen_jcc(DisasContext *s, int b, int dif= f) gen_jmp_rel(s, s->dflag, diff, 0); } =20 -static void gen_cmovcc1(CPUX86State *env, DisasContext *s, MemOp ot, int b, - int modrm, int reg) +static void gen_cmovcc1(DisasContext *s, int b, TCGv dest, TCGv src) { CCPrepare cc; =20 - gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0); - - cc =3D gen_prepare_cc(s, b, s->T1); + cc =3D gen_prepare_cc(s, b, s->tmp4); if (cc.mask !=3D -1) { - TCGv t0 =3D tcg_temp_new(); - tcg_gen_andi_tl(t0, cc.reg, cc.mask); - cc.reg =3D t0; + tcg_gen_andi_tl(s->tmp4, cc.reg, cc.mask); + cc.reg =3D s->tmp4; } if (!cc.use_reg2) { cc.reg2 =3D tcg_constant_tl(cc.imm); } =20 - tcg_gen_movcond_tl(cc.cond, s->T0, cc.reg, cc.reg2, - s->T0, cpu_regs[reg]); - gen_op_mov_reg_v(s, ot, reg, s->T0); + tcg_gen_movcond_tl(cc.cond, dest, cc.reg, cc.reg2, src, dest); } =20 static inline void gen_op_movl_T0_seg(DisasContext *s, X86Seg seg_reg) @@ -5265,7 +5259,9 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) ot =3D dflag; modrm =3D x86_ldub_code(env, s); reg =3D ((modrm >> 3) & 7) | REX_R(s); - gen_cmovcc1(env, s, ot, b, modrm, reg); + gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0); + gen_cmovcc1(s, b ^ 1, s->T0, cpu_regs[reg]); + gen_op_mov_reg_v(s, ot, reg, s->T0); break; =20 /************************/ --=20 2.41.0