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Thu, 19 Oct 2023 03:47:04 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHM++O382ORZPRaq4XqvfIixcgckYoXPdlJZqes6/iSzwdHkX9PlrtDgPz81C/Zv4mMRYeEbg== X-Received: by 2002:a17:906:d552:b0:9c6:64be:a3c9 with SMTP id cr18-20020a170906d55200b009c664bea3c9mr1325305ejc.39.1697712424476; Thu, 19 Oct 2023 03:47:04 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Subject: [PATCH v2 08/19] target/i386: implement CMPccXADD Date: Thu, 19 Oct 2023 12:46:37 +0200 Message-ID: <20231019104648.389942-9-pbonzini@redhat.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231019104648.389942-1-pbonzini@redhat.com> References: <20231019104648.389942-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1697712501484100007 Content-Type: text/plain; charset="utf-8" The main difficulty here is that a page fault when writing to the destinati= on must not overwrite the flags. Therefore, the compute-flags helper must be called with a temporary destination instead of using gen_jcc1*. For simplicity, I am using an unconditional cmpxchg operation, that becomes a NOP if the comparison fails. Signed-off-by: Paolo Bonzini --- target/i386/cpu.c | 2 +- target/i386/tcg/decode-new.c.inc | 30 ++++++++++ target/i386/tcg/decode-new.h | 2 + target/i386/tcg/emit.c.inc | 98 ++++++++++++++++++++++++++++++++ target/i386/tcg/translate.c | 2 + 5 files changed, 133 insertions(+), 1 deletion(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 070c02000fe..15fc9d44e35 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -738,7 +738,7 @@ void x86_cpu_vendor_words2str(char *dst, uint32_t vendo= r1, #define TCG_7_0_EDX_FEATURES (CPUID_7_0_EDX_FSRM | CPUID_7_0_EDX_KERNEL_FE= ATURES) =20 #define TCG_7_1_EAX_FEATURES (CPUID_7_1_EAX_FZRM | CPUID_7_1_EAX_FSRS | \ - CPUID_7_1_EAX_FSRC) + CPUID_7_1_EAX_FSRC | CPUID_7_1_EAX_CMPCCXADD) #define TCG_7_1_EDX_FEATURES 0 #define TCG_7_2_EDX_FEATURES 0 #define TCG_APM_FEATURES 0 diff --git a/target/i386/tcg/decode-new.c.inc b/target/i386/tcg/decode-new.= c.inc index 0a2aebf2ebb..57a5014bc8a 100644 --- a/target/i386/tcg/decode-new.c.inc +++ b/target/i386/tcg/decode-new.c.inc @@ -516,6 +516,28 @@ static const X86OpEntry opcodes_0F38_00toEF[240] =3D { [0xdd] =3D X86_OP_ENTRY3(VAESENCLAST, V,x, H,x, W,x, vex4 cpui= d(AES) p_66), [0xde] =3D X86_OP_ENTRY3(VAESDEC, V,x, H,x, W,x, vex4 cpui= d(AES) p_66), [0xdf] =3D X86_OP_ENTRY3(VAESDECLAST, V,x, H,x, W,x, vex4 cpui= d(AES) p_66), + + /* + * REG selects srcdest2 operand, VEX.vvvv selects src3. VEX class not= found + * in manual, assumed to be 13 from the VEX.L0 =3D constraint. + */ + [0xe0] =3D X86_OP_ENTRY3(CMPccXADD, EM,y, G,y, B,y, vex13 xchg chk(= o64) cpuid(CMPCCXADD) p_66), + [0xe1] =3D X86_OP_ENTRY3(CMPccXADD, EM,y, G,y, B,y, vex13 xchg chk(= o64) cpuid(CMPCCXADD) p_66), + [0xe2] =3D X86_OP_ENTRY3(CMPccXADD, EM,y, G,y, B,y, vex13 xchg chk(= o64) cpuid(CMPCCXADD) p_66), + [0xe3] =3D X86_OP_ENTRY3(CMPccXADD, EM,y, G,y, B,y, vex13 xchg chk(= o64) cpuid(CMPCCXADD) p_66), + [0xe4] =3D X86_OP_ENTRY3(CMPccXADD, EM,y, G,y, B,y, vex13 xchg chk(= o64) cpuid(CMPCCXADD) p_66), + [0xe5] =3D X86_OP_ENTRY3(CMPccXADD, EM,y, G,y, B,y, vex13 xchg chk(= o64) cpuid(CMPCCXADD) p_66), + [0xe6] =3D X86_OP_ENTRY3(CMPccXADD, EM,y, G,y, B,y, vex13 xchg chk(= o64) cpuid(CMPCCXADD) p_66), + [0xe7] =3D X86_OP_ENTRY3(CMPccXADD, EM,y, G,y, B,y, vex13 xchg chk(= o64) cpuid(CMPCCXADD) p_66), + + [0xe8] =3D X86_OP_ENTRY3(CMPccXADD, EM,y, G,y, B,y, vex13 xchg chk(= o64) cpuid(CMPCCXADD) p_66), + [0xe9] =3D X86_OP_ENTRY3(CMPccXADD, EM,y, G,y, B,y, vex13 xchg chk(= o64) cpuid(CMPCCXADD) p_66), + [0xea] =3D X86_OP_ENTRY3(CMPccXADD, EM,y, G,y, B,y, vex13 xchg chk(= o64) cpuid(CMPCCXADD) p_66), + [0xeb] =3D X86_OP_ENTRY3(CMPccXADD, EM,y, G,y, B,y, vex13 xchg chk(= o64) cpuid(CMPCCXADD) p_66), + [0xec] =3D X86_OP_ENTRY3(CMPccXADD, EM,y, G,y, B,y, vex13 xchg chk(= o64) cpuid(CMPCCXADD) p_66), + [0xed] =3D X86_OP_ENTRY3(CMPccXADD, EM,y, G,y, B,y, vex13 xchg chk(= o64) cpuid(CMPCCXADD) p_66), + [0xee] =3D X86_OP_ENTRY3(CMPccXADD, EM,y, G,y, B,y, vex13 xchg chk(= o64) cpuid(CMPCCXADD) p_66), + [0xef] =3D X86_OP_ENTRY3(CMPccXADD, EM,y, G,y, B,y, vex13 xchg chk(= o64) cpuid(CMPCCXADD) p_66), }; =20 /* five rows for no prefix, 66, F3, F2, 66+F2 */ @@ -1273,8 +1295,13 @@ static bool decode_op(DisasContext *s, CPUX86State *= env, X86DecodedInsn *decode, =20 case X86_TYPE_WM: /* modrm byte selects an XMM/YMM memory operand */ op->unit =3D X86_OP_SSE; + goto get_modrm_mem; + + case X86_TYPE_EM: /* modrm byte selects an ALU memory operand */ + op->unit =3D X86_OP_INT; /* fall through */ case X86_TYPE_M: /* modrm byte selects a memory operand */ + get_modrm_mem: modrm =3D get_modrm(s, env); if ((modrm >> 6) =3D=3D 3) { return false; @@ -1511,6 +1538,9 @@ static bool has_cpuid_feature(DisasContext *s, X86CPU= IDFeature cpuid) return (s->cpuid_7_0_ebx_features & CPUID_7_0_EBX_AVX2); case X86_FEAT_SHA_NI: return (s->cpuid_7_0_ebx_features & CPUID_7_0_EBX_SHA_NI); + + case X86_FEAT_CMPCCXADD: + return (s->cpuid_7_1_eax_features & CPUID_7_1_EAX_CMPCCXADD); } g_assert_not_reached(); } diff --git a/target/i386/tcg/decode-new.h b/target/i386/tcg/decode-new.h index 4258db19899..15233fad62f 100644 --- a/target/i386/tcg/decode-new.h +++ b/target/i386/tcg/decode-new.h @@ -47,6 +47,7 @@ typedef enum X86OpType { X86_TYPE_Y, /* string destination */ =20 /* Custom */ + X86_TYPE_EM, /* modrm byte selects an ALU memory operand */ X86_TYPE_WM, /* modrm byte selects an XMM/YMM memory operand */ X86_TYPE_2op, /* 2-operand RMW instruction */ X86_TYPE_LoBits, /* encoded in bits 0-2 of the operand + REX.B */ @@ -104,6 +105,7 @@ typedef enum X86CPUIDFeature { X86_FEAT_AVX2, X86_FEAT_BMI1, X86_FEAT_BMI2, + X86_FEAT_CMPCCXADD, X86_FEAT_F16C, X86_FEAT_FMA, X86_FEAT_MOVBE, diff --git a/target/i386/tcg/emit.c.inc b/target/i386/tcg/emit.c.inc index 90da1401745..dd77a8c5511 100644 --- a/target/i386/tcg/emit.c.inc +++ b/target/i386/tcg/emit.c.inc @@ -1172,6 +1172,104 @@ static void gen_BZHI(DisasContext *s, CPUX86State *= env, X86DecodedInsn *decode) prepare_update1_cc(decode, s, CC_OP_BMILGB + ot); } =20 +static void gen_CMPccXADD(DisasContext *s, CPUX86State *env, X86DecodedIns= n *decode) +{ + TCGv z_tl =3D tcg_constant_tl(0); + TCGLabel *label_top =3D gen_new_label(); + TCGLabel *label_bottom =3D gen_new_label(); + TCGv oldv =3D tcg_temp_new(); + TCGv newv =3D tcg_temp_new(); + TCGv cmpv =3D tcg_temp_new(); + TCGv tmp_cc =3D tcg_temp_new(); + + TCGv cmp_lhs, cmp_rhs; + MemOp ot, ot_full; + + int jcc_op =3D (decode->b >> 1) & 7; + static const uint8_t cond[16] =3D { + TCG_COND_NE, /* o, just test OF=3D1 */ + TCG_COND_EQ, /* no, just test OF=3D0 */ + TCG_COND_LTU, /* b */ + TCG_COND_GEU, /* ae (nb) */ + TCG_COND_EQ, /* z */ + TCG_COND_NE, /* nz */ + TCG_COND_LEU, /* be */ + TCG_COND_GTU, /* a (nbe) */ + TCG_COND_LT, /* s, compares result against 0 */ + TCG_COND_GE, /* ns, compares result against 0 */ + TCG_COND_NE, /* p, just test PF=3D1 */ + TCG_COND_EQ, /* np, just test PF=3D0 */ + TCG_COND_LT, /* l */ + TCG_COND_GE, /* ge (nl) */ + TCG_COND_LE, /* le */ + TCG_COND_GT, /* g (nle) */ + }; + + ot =3D decode->op[0].ot; + ot_full =3D ot | MO_LE; + if (jcc_op >=3D JCC_S) { + /* + * Sign-extend values before subtracting for S, P (zero/sign exten= sion + * does not matter there) L, LE and their inverses. + */ + ot_full |=3D MO_SIGN; + } + + gen_ext_tl(cmpv, cpu_regs[decode->op[1].n], ot_full); + + /* + * Cmpxchg loop starts here. + * - s->T1: addition operand (from decoder) + * - s->A0: dest address (from decoder) + * - s->cc_srcT: memory operand (lhs for comparison) + * - cmpv: rhs for comparison (will be in cc_src except for o/no/p/np); + */ + gen_set_label(label_top); + gen_op_ld_v(s, ot_full, s->cc_srcT, s->A0); + tcg_gen_sub_tl(s->T0, s->cc_srcT, cmpv); + + /* Compute comparison result but do not clobber cc_* yet. */ + switch (jcc_op) { + case JCC_O: + case JCC_P: + gen_helper_cc_compute_all(tmp_cc, s->T0, cmpv, z_tl, + tcg_constant_i32(CC_OP_SUBB + ot)); + decode->cc_src =3D tmp_cc; + decode->cc_op =3D CC_OP_EFLAGS; + + tcg_gen_andi_tl(s->T0, tmp_cc, (jcc_op =3D=3D JCC_O ? CC_O : CC_P)= ); + cmp_lhs =3D s->T0, cmp_rhs =3D z_tl; + break; + + case JCC_S: + cmp_lhs =3D s->T0, cmp_rhs =3D z_tl; + goto cc_sub; + + default: + cmp_lhs =3D s->cc_srcT, cmp_rhs =3D cmpv; + cc_sub: + decode->cc_dst =3D s->T0; + decode->cc_src =3D cmpv; + decode->cc_op =3D CC_OP_SUBB + ot; + break; + } + + /* Compute new value: if condition does not hold, just store back s->c= c_srcT */ + tcg_gen_add_tl(newv, s->cc_srcT, s->T1); + tcg_gen_movcond_tl(cond[decode->b & 15], newv, cmp_lhs, cmp_rhs, newv,= s->cc_srcT); + tcg_gen_atomic_cmpxchg_tl(oldv, s->A0, s->cc_srcT, newv, s->mem_index,= ot_full); + + /* Exit unconditionally if cmpxchg succeeded. */ + tcg_gen_brcond_tl(TCG_COND_EQ, oldv, s->cc_srcT, label_bottom); + + /* Try again if there was actually a store to make. */ + tcg_gen_brcond_tl(cond[decode->b & 15], cmp_lhs, cmp_rhs, label_top); + gen_set_label(label_bottom); + + /* Store old value to registers only after a successful store. */ + gen_writeback(s, decode, 1, s->cc_srcT); +} + static void gen_CRC32(DisasContext *s, CPUX86State *env, X86DecodedInsn *d= ecode) { MemOp ot =3D decode->op[2].ot; diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index d7d6c85877d..038151a8c3e 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -122,6 +122,7 @@ typedef struct DisasContext { int cpuid_ext3_features; int cpuid_7_0_ebx_features; int cpuid_7_0_ecx_features; + int cpuid_7_1_eax_features; int cpuid_xsave_features; =20 /* TCG local temps */ @@ -6957,6 +6958,7 @@ static void i386_tr_init_disas_context(DisasContextBa= se *dcbase, CPUState *cpu) dc->cpuid_ext3_features =3D env->features[FEAT_8000_0001_ECX]; dc->cpuid_7_0_ebx_features =3D env->features[FEAT_7_0_EBX]; dc->cpuid_7_0_ecx_features =3D env->features[FEAT_7_0_ECX]; + dc->cpuid_7_1_eax_features =3D env->features[FEAT_7_1_EAX]; dc->cpuid_xsave_features =3D env->features[FEAT_XSAVE]; dc->jmp_opt =3D !((cflags & CF_NO_GOTO_TB) || (flags & (HF_TF_MASK | HF_INHIBIT_IRQ_MASK))); --=20 2.41.0