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Thu, 19 Oct 2023 03:47:01 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFH9SdduFAXh6+GboKOMKn4MG67ftjAUZv8iJoxjdDXF0BKljXa1FoRUdKCgl9BCbieZPP55A== X-Received: by 2002:a17:907:97c3:b0:9c3:87ff:67b8 with SMTP id js3-20020a17090797c300b009c387ff67b8mr1621765ejc.2.1697712420882; Thu, 19 Oct 2023 03:47:00 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Subject: [PATCH v2 06/19] target/i386: accept full MemOp in gen_ext_tl Date: Thu, 19 Oct 2023 12:46:35 +0200 Message-ID: <20231019104648.389942-7-pbonzini@redhat.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231019104648.389942-1-pbonzini@redhat.com> References: <20231019104648.389942-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1697712501440100003 Content-Type: text/plain; charset="utf-8" Use MO_SIGN to indicate signed vs. unsigned extension, and filter out bits other than MO_SIGN and MO_SIZE. Signed-off-by: Paolo Bonzini --- target/i386/tcg/translate.c | 30 +++++++++++++++--------------- 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 4f6f9fa7e52..d7d6c85877d 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -699,18 +699,18 @@ static inline void gen_op_movl_T0_Dshift(DisasContext= *s, MemOp ot) tcg_gen_shli_tl(s->T0, s->T0, ot); }; =20 -static TCGv gen_ext_tl(TCGv dst, TCGv src, MemOp size, bool sign) +static TCGv gen_ext_tl(TCGv dst, TCGv src, MemOp ot) { - switch (size) { + switch (ot & MO_SIZE) { case MO_8: - if (sign) { + if (ot & MO_SIGN) { tcg_gen_ext8s_tl(dst, src); } else { tcg_gen_ext8u_tl(dst, src); } return dst; case MO_16: - if (sign) { + if (ot & MO_SIGN) { tcg_gen_ext16s_tl(dst, src); } else { tcg_gen_ext16u_tl(dst, src); @@ -718,7 +718,7 @@ static TCGv gen_ext_tl(TCGv dst, TCGv src, MemOp size, = bool sign) return dst; #ifdef TARGET_X86_64 case MO_32: - if (sign) { + if (ot & MO_SIGN) { tcg_gen_ext32s_tl(dst, src); } else { tcg_gen_ext32u_tl(dst, src); @@ -732,12 +732,12 @@ static TCGv gen_ext_tl(TCGv dst, TCGv src, MemOp size= , bool sign) =20 static void gen_extu(MemOp ot, TCGv reg) { - gen_ext_tl(reg, reg, ot, false); + gen_ext_tl(reg, reg, ot); } =20 static void gen_exts(MemOp ot, TCGv reg) { - gen_ext_tl(reg, reg, ot, true); + gen_ext_tl(reg, reg, ot | MO_SIGN); } =20 static void gen_op_j_ecx(DisasContext *s, TCGCond cond, TCGLabel *label1) @@ -926,7 +926,7 @@ static CCPrepare gen_prepare_eflags_c(DisasContext *s, = TCGv reg) case CC_OP_SUBB ... CC_OP_SUBQ: /* (DATA_TYPE)CC_SRCT < (DATA_TYPE)CC_SRC */ size =3D s->cc_op - CC_OP_SUBB; - t1 =3D gen_ext_tl(s->tmp0, cpu_cc_src, size, false); + t1 =3D gen_ext_tl(s->tmp0, cpu_cc_src, size); /* If no temporary was used, be careful not to alias t1 and t0. */ t0 =3D t1 =3D=3D cpu_cc_src ? s->tmp0 : reg; tcg_gen_mov_tl(t0, s->cc_srcT); @@ -936,8 +936,8 @@ static CCPrepare gen_prepare_eflags_c(DisasContext *s, = TCGv reg) case CC_OP_ADDB ... CC_OP_ADDQ: /* (DATA_TYPE)CC_DST < (DATA_TYPE)CC_SRC */ size =3D s->cc_op - CC_OP_ADDB; - t1 =3D gen_ext_tl(s->tmp0, cpu_cc_src, size, false); - t0 =3D gen_ext_tl(reg, cpu_cc_dst, size, false); + t1 =3D gen_ext_tl(s->tmp0, cpu_cc_src, size); + t0 =3D gen_ext_tl(reg, cpu_cc_dst, size); add_sub: return (CCPrepare) { .cond =3D TCG_COND_LTU, .reg =3D t0, .reg2 =3D t1, .mask =3D -1, .use_reg2 =3D tru= e }; @@ -965,7 +965,7 @@ static CCPrepare gen_prepare_eflags_c(DisasContext *s, = TCGv reg) =20 case CC_OP_BMILGB ... CC_OP_BMILGQ: size =3D s->cc_op - CC_OP_BMILGB; - t0 =3D gen_ext_tl(reg, cpu_cc_src, size, false); + t0 =3D gen_ext_tl(reg, cpu_cc_src, size); return (CCPrepare) { .cond =3D TCG_COND_EQ, .reg =3D t0, .mask =3D= -1 }; =20 case CC_OP_ADCX: @@ -1017,7 +1017,7 @@ static CCPrepare gen_prepare_eflags_s(DisasContext *s= , TCGv reg) default: { MemOp size =3D (s->cc_op - CC_OP_ADDB) & 3; - TCGv t0 =3D gen_ext_tl(reg, cpu_cc_dst, size, true); + TCGv t0 =3D gen_ext_tl(reg, cpu_cc_dst, size | MO_SIGN); return (CCPrepare) { .cond =3D TCG_COND_LT, .reg =3D t0, .mask= =3D -1 }; } } @@ -1062,7 +1062,7 @@ static CCPrepare gen_prepare_eflags_z(DisasContext *s= , TCGv reg) default: { MemOp size =3D (s->cc_op - CC_OP_ADDB) & 3; - TCGv t0 =3D gen_ext_tl(reg, cpu_cc_dst, size, false); + TCGv t0 =3D gen_ext_tl(reg, cpu_cc_dst, size); return (CCPrepare) { .cond =3D TCG_COND_EQ, .reg =3D t0, .mask= =3D -1 }; } } @@ -1088,7 +1088,7 @@ static CCPrepare gen_prepare_cc(DisasContext *s, int = b, TCGv reg) case JCC_BE: tcg_gen_mov_tl(s->tmp4, s->cc_srcT); gen_extu(size, s->tmp4); - t0 =3D gen_ext_tl(s->tmp0, cpu_cc_src, size, false); + t0 =3D gen_ext_tl(s->tmp0, cpu_cc_src, size); cc =3D (CCPrepare) { .cond =3D TCG_COND_LEU, .reg =3D s->tmp4, .reg2 =3D t0, .mask =3D -1, .use_reg2 =3D t= rue }; break; @@ -1101,7 +1101,7 @@ static CCPrepare gen_prepare_cc(DisasContext *s, int = b, TCGv reg) fast_jcc_l: tcg_gen_mov_tl(s->tmp4, s->cc_srcT); gen_exts(size, s->tmp4); - t0 =3D gen_ext_tl(s->tmp0, cpu_cc_src, size, true); + t0 =3D gen_ext_tl(s->tmp0, cpu_cc_src, size | MO_SIGN); cc =3D (CCPrepare) { .cond =3D cond, .reg =3D s->tmp4, .reg2 =3D t0, .mask =3D -1, .use_reg2 =3D t= rue }; break; --=20 2.41.0