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decoder Date: Thu, 19 Oct 2023 12:46:40 +0200 Message-ID: <20231019104648.389942-12-pbonzini@redhat.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231019104648.389942-1-pbonzini@redhat.com> References: <20231019104648.389942-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1697712549629100003 Content-Type: text/plain; charset="utf-8" Signed-off-by: Paolo Bonzini --- target/i386/tcg/decode-new.c.inc | 116 ++++++++++++++++++ target/i386/tcg/decode-new.h | 3 + target/i386/tcg/emit.c.inc | 203 +++++++++++++++++++++++++++++++ target/i386/tcg/translate.c | 2 +- 4 files changed, 323 insertions(+), 1 deletion(-) diff --git a/target/i386/tcg/decode-new.c.inc b/target/i386/tcg/decode-new.= c.inc index 2f614e2a6f0..dc596ba9f7a 100644 --- a/target/i386/tcg/decode-new.c.inc +++ b/target/i386/tcg/decode-new.c.inc @@ -102,6 +102,8 @@ =20 #define X86_OP_GROUP2(op, op0, s0, op1, s1, ...) \ X86_OP_GROUP3(op, op0, s0, 2op, s0, op1, s1, ## __VA_ARGS__) +#define X86_OP_GROUPw(op, op0, s0, ...) \ + X86_OP_GROUP3(op, op0, s0, None, None, None, None, ## __VA_ARGS__) #define X86_OP_GROUP0(op, ...) \ X86_OP_GROUP3(op, None, None, None, None, None, None, ## __VA_ARGS__) =20 @@ -127,10 +129,13 @@ X86_OP_ENTRY3(op, op0, s0, None, None, None, None, ## __VA_ARGS__) #define X86_OP_ENTRYr(op, op0, s0, ...) \ X86_OP_ENTRY3(op, None, None, None, None, op0, s0, ## __VA_ARGS__) +#define X86_OP_ENTRY1(op, op0, s0, ...) \ + X86_OP_ENTRY3(op, op0, s0, 2op, s0, None, None, ## __VA_ARGS__) #define X86_OP_ENTRY0(op, ...) \ X86_OP_ENTRY3(op, None, None, None, None, None, None, ## __VA_ARGS__) =20 #define cpuid(feat) .cpuid =3D X86_FEAT_##feat, +#define nowb .special =3D X86_SPECIAL_NoWriteback, #define xchg .special =3D X86_SPECIAL_Locked, #define mmx .special =3D X86_SPECIAL_MMX, #define zext0 .special =3D X86_SPECIAL_ZExtOp0, @@ -1074,7 +1079,114 @@ static void decode_0F(DisasContext *s, CPUX86State = *env, X86OpEntry *entry, uint } =20 static const X86OpEntry opcodes_root[256] =3D { + [0x00] =3D X86_OP_ENTRY2(ADD, E,b, G,b), + [0x01] =3D X86_OP_ENTRY2(ADD, E,v, G,v), + [0x02] =3D X86_OP_ENTRY2(ADD, G,b, E,b), + [0x03] =3D X86_OP_ENTRY2(ADD, G,v, E,v), + [0x04] =3D X86_OP_ENTRY2(ADD, 0,b, I,b), /* AL, Ib */ + [0x05] =3D X86_OP_ENTRY2(ADD, 0,v, I,z), /* rAX, Iz */ + [0x06] =3D X86_OP_ENTRYr(PUSH, ES, w, chk(i64)), + [0x07] =3D X86_OP_ENTRYw(POP, ES, w, chk(i64)), + + [0x10] =3D X86_OP_ENTRY2(ADC, E,b, G,b), + [0x11] =3D X86_OP_ENTRY2(ADC, E,v, G,v), + [0x12] =3D X86_OP_ENTRY2(ADC, G,b, E,b), + [0x13] =3D X86_OP_ENTRY2(ADC, G,v, E,v), + [0x14] =3D X86_OP_ENTRY2(ADC, 0,b, I,b), /* AL, Ib */ + [0x15] =3D X86_OP_ENTRY2(ADC, 0,v, I,z), /* rAX, Iz */ + [0x16] =3D X86_OP_ENTRYr(PUSH, SS, w, chk(i64)), + [0x17] =3D X86_OP_ENTRYw(POP, SS, w, chk(i64)), + + [0x20] =3D X86_OP_ENTRY2(AND, E,b, G,b), + [0x21] =3D X86_OP_ENTRY2(AND, E,v, G,v), + [0x22] =3D X86_OP_ENTRY2(AND, G,b, E,b), + [0x23] =3D X86_OP_ENTRY2(AND, G,v, E,v), + [0x24] =3D X86_OP_ENTRY2(AND, 0,b, I,b), /* AL, Ib */ + [0x25] =3D X86_OP_ENTRY2(AND, 0,v, I,z), /* rAX, Iz */ + [0x26] =3D {}, + [0x27] =3D X86_OP_ENTRY0(DAA, chk(i64)), + + [0x30] =3D X86_OP_ENTRY2(XOR, E,b, G,b), + [0x31] =3D X86_OP_ENTRY2(XOR, E,v, G,v), + [0x32] =3D X86_OP_ENTRY2(XOR, G,b, E,b), + [0x33] =3D X86_OP_ENTRY2(XOR, G,v, E,v), + [0x34] =3D X86_OP_ENTRY2(XOR, 0,b, I,b), /* AL, Ib */ + [0x35] =3D X86_OP_ENTRY2(XOR, 0,v, I,z), /* rAX, Iz */ + [0x36] =3D {}, + [0x37] =3D X86_OP_ENTRY0(AAA, chk(i64)), + + [0x40] =3D X86_OP_ENTRY1(INC, 0,v, chk(i64)), + [0x41] =3D X86_OP_ENTRY1(INC, 1,v, chk(i64)), + [0x42] =3D X86_OP_ENTRY1(INC, 2,v, chk(i64)), + [0x43] =3D X86_OP_ENTRY1(INC, 3,v, chk(i64)), + [0x44] =3D X86_OP_ENTRY1(INC, 4,v, chk(i64)), + [0x45] =3D X86_OP_ENTRY1(INC, 5,v, chk(i64)), + [0x46] =3D X86_OP_ENTRY1(INC, 6,v, chk(i64)), + [0x47] =3D X86_OP_ENTRY1(INC, 7,v, chk(i64)), + + [0x50] =3D X86_OP_ENTRYr(PUSH, LoBits,d64), + [0x51] =3D X86_OP_ENTRYr(PUSH, LoBits,d64), + [0x52] =3D X86_OP_ENTRYr(PUSH, LoBits,d64), + [0x53] =3D X86_OP_ENTRYr(PUSH, LoBits,d64), + [0x54] =3D X86_OP_ENTRYr(PUSH, LoBits,d64), + [0x55] =3D X86_OP_ENTRYr(PUSH, LoBits,d64), + [0x56] =3D X86_OP_ENTRYr(PUSH, LoBits,d64), + [0x57] =3D X86_OP_ENTRYr(PUSH, LoBits,d64), + + + [0x08] =3D X86_OP_ENTRY2(OR, E,b, G,b), + [0x09] =3D X86_OP_ENTRY2(OR, E,v, G,v), + [0x0A] =3D X86_OP_ENTRY2(OR, G,b, E,b), + [0x0B] =3D X86_OP_ENTRY2(OR, G,v, E,v), + [0x0C] =3D X86_OP_ENTRY2(OR, 0,b, I,b), /* AL, Ib */ + [0x0D] =3D X86_OP_ENTRY2(OR, 0,v, I,z), /* rAX, Iz */ + [0x0E] =3D X86_OP_ENTRYr(PUSH, CS, w, chk(i64)), [0x0F] =3D X86_OP_GROUP0(0F), + + [0x18] =3D X86_OP_ENTRY2(SBB, E,b, G,b), + [0x19] =3D X86_OP_ENTRY2(SBB, E,v, G,v), + [0x1A] =3D X86_OP_ENTRY2(SBB, G,b, E,b), + [0x1B] =3D X86_OP_ENTRY2(SBB, G,v, E,v), + [0x1C] =3D X86_OP_ENTRY2(SBB, 0,b, I,b), /* AL, Ib */ + [0x1D] =3D X86_OP_ENTRY2(SBB, 0,v, I,z), /* rAX, Iz */ + [0x1E] =3D X86_OP_ENTRYr(PUSH, DS, w, chk(i64)), + [0x1F] =3D X86_OP_ENTRYw(POP, DS, w, chk(i64)), + + [0x28] =3D X86_OP_ENTRY2(SUB, E,b, G,b), + [0x29] =3D X86_OP_ENTRY2(SUB, E,v, G,v), + [0x2A] =3D X86_OP_ENTRY2(SUB, G,b, E,b), + [0x2B] =3D X86_OP_ENTRY2(SUB, G,v, E,v), + [0x2C] =3D X86_OP_ENTRY2(SUB, 0,b, I,b), /* AL, Ib */ + [0x2D] =3D X86_OP_ENTRY2(SUB, 0,v, I,z), /* rAX, Iz */ + [0x2E] =3D {}, + [0x2F] =3D X86_OP_ENTRY0(DAS, chk(i64)), + + [0x38] =3D X86_OP_ENTRY2(SUB, E,b, G,b, nowb), + [0x39] =3D X86_OP_ENTRY2(SUB, E,v, G,v, nowb), + [0x3A] =3D X86_OP_ENTRY2(SUB, G,b, E,b, nowb), + [0x3B] =3D X86_OP_ENTRY2(SUB, G,v, E,v, nowb), + [0x3C] =3D X86_OP_ENTRY2(SUB, 0,b, I,b, nowb), /* AL, Ib */ + [0x3D] =3D X86_OP_ENTRY2(SUB, 0,v, I,z, nowb), /* rAX, Iz */ + [0x3E] =3D {}, + [0x3F] =3D X86_OP_ENTRY0(AAS, chk(i64)), + + [0x48] =3D X86_OP_ENTRY1(DEC, 0,v, chk(i64)), + [0x49] =3D X86_OP_ENTRY1(DEC, 1,v, chk(i64)), + [0x4A] =3D X86_OP_ENTRY1(DEC, 2,v, chk(i64)), + [0x4B] =3D X86_OP_ENTRY1(DEC, 3,v, chk(i64)), + [0x4C] =3D X86_OP_ENTRY1(DEC, 4,v, chk(i64)), + [0x4D] =3D X86_OP_ENTRY1(DEC, 5,v, chk(i64)), + [0x4E] =3D X86_OP_ENTRY1(DEC, 6,v, chk(i64)), + [0x4F] =3D X86_OP_ENTRY1(DEC, 7,v, chk(i64)), + + [0x58] =3D X86_OP_ENTRYw(POP, LoBits,d64), + [0x59] =3D X86_OP_ENTRYw(POP, LoBits,d64), + [0x5A] =3D X86_OP_ENTRYw(POP, LoBits,d64), + [0x5B] =3D X86_OP_ENTRYw(POP, LoBits,d64), + [0x5C] =3D X86_OP_ENTRYw(POP, LoBits,d64), + [0x5D] =3D X86_OP_ENTRYw(POP, LoBits,d64), + [0x5E] =3D X86_OP_ENTRYw(POP, LoBits,d64), + [0x5F] =3D X86_OP_ENTRYw(POP, LoBits,d64), }; =20 #undef mmx @@ -1898,6 +2010,10 @@ static void disas_insn_new(DisasContext *s, CPUState= *cpu, int b) } break; =20 + case X86_SPECIAL_NoWriteback: + decode.op[0].unit =3D X86_OP_SKIP; + break; + case X86_SPECIAL_ZExtOp0: assert(decode.op[0].unit =3D=3D X86_OP_INT); if (!decode.op[0].has_ea) { diff --git a/target/i386/tcg/decode-new.h b/target/i386/tcg/decode-new.h index 15233fad62f..a3983794ac5 100644 --- a/target/i386/tcg/decode-new.h +++ b/target/i386/tcg/decode-new.h @@ -161,6 +161,9 @@ typedef enum X86InsnSpecial { /* Always locked if it has a memory operand (XCHG) */ X86_SPECIAL_Locked, =20 + /* Writeback not needed or done manually in the callback */ + X86_SPECIAL_NoWriteback, + /* * Register operand 0/2 is zero extended to 32 bits. Rd/Mb or Rd/Mw * in the manual. diff --git a/target/i386/tcg/emit.c.inc b/target/i386/tcg/emit.c.inc index dd77a8c5511..6b9f518cc94 100644 --- a/target/i386/tcg/emit.c.inc +++ b/target/i386/tcg/emit.c.inc @@ -329,6 +329,27 @@ static void prepare_update1_cc(X86DecodedInsn *decode,= DisasContext *s, CCOp op) decode->cc_op =3D op; } =20 +static void prepare_update2_cc(X86DecodedInsn *decode, DisasContext *s, CC= Op op) +{ + decode->cc_src =3D s->T1; + decode->cc_dst =3D s->T0; + decode->cc_op =3D op; +} + +static void prepare_update_cc_incdec(X86DecodedInsn *decode, DisasContext = *s, CCOp op) +{ + gen_compute_eflags_c(s, s->T1); + prepare_update2_cc(decode, s, op); +} + +static void prepare_update3_cc(X86DecodedInsn *decode, DisasContext *s, CC= Op op, TCGv reg) +{ + decode->cc_src2 =3D reg; + decode->cc_src =3D s->T1; + decode->cc_dst =3D s->T0; + decode->cc_op =3D op; +} + static void gen_store_sse(DisasContext *s, X86DecodedInsn *decode, int src= _ofs) { MemOp ot =3D decode->op[0].ot; @@ -1017,6 +1038,36 @@ static void gen_##uname(DisasContext *s, CPUX86State= *env, X86DecodedInsn *decod VSIB_AVX(VPGATHERD, vpgatherd) VSIB_AVX(VPGATHERQ, vpgatherq) =20 +static void gen_AAA(DisasContext *s, CPUX86State *env, X86DecodedInsn *dec= ode) +{ + gen_update_cc_op(s); + gen_helper_aaa(tcg_env); + set_cc_op(s, CC_OP_EFLAGS); +} + +static void gen_AAS(DisasContext *s, CPUX86State *env, X86DecodedInsn *dec= ode) +{ + gen_update_cc_op(s); + gen_helper_aas(tcg_env); + set_cc_op(s, CC_OP_EFLAGS); +} + +static void gen_ADC(DisasContext *s, CPUX86State *env, X86DecodedInsn *dec= ode) +{ + MemOp ot =3D decode->op[0].ot; + + gen_compute_eflags_c(s, s->tmp4); + if (s->prefix & PREFIX_LOCK) { + tcg_gen_add_tl(s->T0, s->tmp4, s->T1); + tcg_gen_atomic_add_fetch_tl(s->T0, s->A0, s->T0, + s->mem_index, ot | MO_LE); + } else { + tcg_gen_add_tl(s->T0, s->T0, s->T1); + tcg_gen_add_tl(s->T0, s->T0, s->tmp4); + } + prepare_update3_cc(decode, s, CC_OP_ADCB + ot, s->tmp4); +} + /* ADCX/ADOX do not have memory operands and can use set_cc_op. */ static void gen_ADCOX(DisasContext *s, CPUX86State *env, MemOp ot, int cc_= op) { @@ -1070,11 +1121,37 @@ static void gen_ADCX(DisasContext *s, CPUX86State *= env, X86DecodedInsn *decode) gen_ADCOX(s, env, decode->op[0].ot, CC_OP_ADCX); } =20 +static void gen_ADD(DisasContext *s, CPUX86State *env, X86DecodedInsn *dec= ode) +{ + MemOp ot =3D decode->op[0].ot; + + if (s->prefix & PREFIX_LOCK) { + tcg_gen_atomic_add_fetch_tl(s->T0, s->A0, s->T1, + s->mem_index, ot | MO_LE); + } else { + tcg_gen_add_tl(s->T0, s->T0, s->T1); + } + prepare_update2_cc(decode, s, CC_OP_ADDB + ot); +} + static void gen_ADOX(DisasContext *s, CPUX86State *env, X86DecodedInsn *de= code) { gen_ADCOX(s, env, decode->op[0].ot, CC_OP_ADOX); } =20 +static void gen_AND(DisasContext *s, CPUX86State *env, X86DecodedInsn *dec= ode) +{ + MemOp ot =3D decode->op[0].ot; + + if (s->prefix & PREFIX_LOCK) { + tcg_gen_atomic_and_fetch_tl(s->T0, s->A0, s->T1, + s->mem_index, ot | MO_LE); + } else { + tcg_gen_and_tl(s->T0, s->T0, s->T1); + } + prepare_update1_cc(decode, s, CC_OP_LOGICB + ot); +} + static void gen_ANDN(DisasContext *s, CPUX86State *env, X86DecodedInsn *de= code) { MemOp ot =3D decode->op[0].ot; @@ -1308,6 +1385,34 @@ static void gen_CVTTPx2PI(DisasContext *s, CPUX86Sta= te *env, X86DecodedInsn *dec } } =20 +static void gen_DAA(DisasContext *s, CPUX86State *env, X86DecodedInsn *dec= ode) +{ + gen_update_cc_op(s); + gen_helper_daa(tcg_env); + set_cc_op(s, CC_OP_EFLAGS); +} + +static void gen_DAS(DisasContext *s, CPUX86State *env, X86DecodedInsn *dec= ode) +{ + gen_update_cc_op(s); + gen_helper_das(tcg_env); + set_cc_op(s, CC_OP_EFLAGS); +} + +static void gen_DEC(DisasContext *s, CPUX86State *env, X86DecodedInsn *dec= ode) +{ + MemOp ot =3D decode->op[0].ot; + + tcg_gen_movi_tl(s->T1, -1); + if (s->prefix & PREFIX_LOCK) { + tcg_gen_atomic_add_fetch_tl(s->T0, s->A0, s->T1, + s->mem_index, ot | MO_LE); + } else { + tcg_gen_add_tl(s->T0, s->T0, s->T1); + } + prepare_update_cc_incdec(decode, s, CC_OP_DECB + ot); +} + static void gen_EMMS(DisasContext *s, CPUX86State *env, X86DecodedInsn *de= code) { gen_helper_emms(tcg_env); @@ -1326,6 +1431,20 @@ static void gen_EXTRQ_r(DisasContext *s, CPUX86State= *env, X86DecodedInsn *decod gen_helper_extrq_r(tcg_env, OP_PTR0, OP_PTR2); } =20 +static void gen_INC(DisasContext *s, CPUX86State *env, X86DecodedInsn *dec= ode) +{ + MemOp ot =3D decode->op[0].ot; + + tcg_gen_movi_tl(s->T1, 1); + if (s->prefix & PREFIX_LOCK) { + tcg_gen_atomic_add_fetch_tl(s->T0, s->A0, s->T1, + s->mem_index, ot | MO_LE); + } else { + tcg_gen_add_tl(s->T0, s->T0, s->T1); + } + prepare_update_cc_incdec(decode, s, CC_OP_INCB + ot); +} + static void gen_INSERTQ_i(DisasContext *s, CPUX86State *env, X86DecodedIns= n *decode) { TCGv_i32 length =3D tcg_constant_i32(decode->immediate & 63); @@ -1477,6 +1596,19 @@ static void gen_MULX(DisasContext *s, CPUX86State *e= nv, X86DecodedInsn *decode) =20 } =20 +static void gen_OR(DisasContext *s, CPUX86State *env, X86DecodedInsn *deco= de) +{ + MemOp ot =3D decode->op[0].ot; + + if (s->prefix & PREFIX_LOCK) { + tcg_gen_atomic_or_fetch_tl(s->T0, s->A0, s->T1, + s->mem_index, ot | MO_LE); + } else { + tcg_gen_or_tl(s->T0, s->T0, s->T1); + } + prepare_update1_cc(decode, s, CC_OP_LOGICB + ot); +} + static void gen_PALIGNR(DisasContext *s, CPUX86State *env, X86DecodedInsn = *decode) { TCGv_i32 imm =3D tcg_constant8u_i32(decode->immediate); @@ -1728,6 +1860,18 @@ static void gen_PMOVMSKB(DisasContext *s, CPUX86Stat= e *env, X86DecodedInsn *deco } } =20 +static void gen_POP(DisasContext *s, CPUX86State *env, X86DecodedInsn *dec= ode) +{ + MemOp ot =3D gen_pop_T0(s); + if (decode->op[0].has_ea) { + /* NOTE: order is important for MMU exceptions */ + gen_op_st_v(s, ot, s->T0, s->A0); + decode->op[0].unit =3D X86_OP_SKIP; + } + /* NOTE: writing back registers after update is important for pop %sp = */ + gen_pop_update(s, ot); +} + static void gen_PSHUFW(DisasContext *s, CPUX86State *env, X86DecodedInsn *= decode) { TCGv_i32 imm =3D tcg_constant8u_i32(decode->immediate); @@ -1874,6 +2018,11 @@ static void gen_PSLLDQ_i(DisasContext *s, CPUX86Stat= e *env, X86DecodedInsn *deco } } =20 +static void gen_PUSH(DisasContext *s, CPUX86State *env, X86DecodedInsn *de= code) +{ + gen_push_v(s, s->T1); +} + static void gen_RORX(DisasContext *s, CPUX86State *env, X86DecodedInsn *de= code) { MemOp ot =3D decode->op[0].ot; @@ -1901,6 +2050,23 @@ static void gen_SARX(DisasContext *s, CPUX86State *e= nv, X86DecodedInsn *decode) tcg_gen_sar_tl(s->T0, s->T0, s->T1); } =20 +static void gen_SBB(DisasContext *s, CPUX86State *env, X86DecodedInsn *dec= ode) +{ + MemOp ot =3D decode->op[0].ot; + + gen_compute_eflags_c(s, s->tmp4); + if (s->prefix & PREFIX_LOCK) { + tcg_gen_add_tl(s->T0, s->T1, s->tmp4); + tcg_gen_neg_tl(s->T0, s->T0); + tcg_gen_atomic_add_fetch_tl(s->T0, s->A0, s->T0, + s->mem_index, ot | MO_LE); + } else { + tcg_gen_sub_tl(s->T0, s->T0, s->T1); + tcg_gen_sub_tl(s->T0, s->T0, s->tmp4); + } + prepare_update3_cc(decode, s, CC_OP_SBBB + ot, s->tmp4); +} + static void gen_SHA1NEXTE(DisasContext *s, CPUX86State *env, X86DecodedIns= n *decode) { gen_helper_sha1nexte(OP_PTR0, OP_PTR1, OP_PTR2); @@ -1991,6 +2157,22 @@ static void gen_STMXCSR(DisasContext *s, CPUX86State= *env, X86DecodedInsn *decod tcg_gen_ld32u_tl(s->T0, tcg_env, offsetof(CPUX86State, mxcsr)); } =20 +static void gen_SUB(DisasContext *s, CPUX86State *env, X86DecodedInsn *dec= ode) +{ + MemOp ot =3D decode->op[0].ot; + + if (s->prefix & PREFIX_LOCK) { + tcg_gen_neg_tl(s->T0, s->T1); + tcg_gen_atomic_fetch_add_tl(s->cc_srcT, s->A0, s->T0, + s->mem_index, ot | MO_LE); + tcg_gen_sub_tl(s->T0, s->cc_srcT, s->T1); + } else { + tcg_gen_mov_tl(s->cc_srcT, s->T0); + tcg_gen_sub_tl(s->T0, s->T0, s->T1); + } + prepare_update2_cc(decode, s, CC_OP_SUBB + ot); +} + static void gen_VAESIMC(DisasContext *s, CPUX86State *env, X86DecodedInsn = *decode) { assert(!s->vex_l); @@ -2470,3 +2652,24 @@ static void gen_VZEROUPPER(DisasContext *s, CPUX86St= ate *env, X86DecodedInsn *de tcg_gen_gvec_dup_imm(MO_64, offset, 16, 16, 0); } } + +static void gen_XOR(DisasContext *s, CPUX86State *env, X86DecodedInsn *dec= ode) +{ + /* special case XOR reg, reg */ + if (decode->op[1].unit =3D=3D X86_OP_INT && + decode->op[2].unit =3D=3D X86_OP_INT && + decode->op[1].n =3D=3D decode->op[2].n) { + tcg_gen_movi_tl(s->T0, 0); + set_cc_op(s, CC_OP_CLR); + } else { + MemOp ot =3D decode->op[0].ot; + + if (s->prefix & PREFIX_LOCK) { + tcg_gen_atomic_xor_fetch_tl(s->T0, s->A0, s->T1, + s->mem_index, ot | MO_LE); + } else { + tcg_gen_xor_tl(s->T0, s->T0, s->T1); + } + prepare_update1_cc(decode, s, CC_OP_LOGICB + ot); + } +} diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 080b56840da..e13bf7df591 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -3156,7 +3156,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) #ifndef CONFIG_USER_ONLY use_new &=3D b <=3D limit; #endif - if (use_new && 0) { + if (use_new && b <=3D 0x5f) { disas_insn_new(s, cpu, b); return true; } --=20 2.41.0