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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=bcain@quicinc.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @quicinc.com) X-ZM-MESSAGEID: 1697681918500100003 Of the changes in this commit, the changes in `HELPER(commit_hvx_stores)()` are less obvious. They are required because of some macro invocations like SCATTER_OP_WRITE_TO_MEM(). e.g.: In file included from ../target/hexagon/op_helper.c:31: ../target/hexagon/mmvec/macros.h:205:18: error: declaration of =E2=80= =98i=E2=80=99 shadows a previous local [-Werror=3Dshadow=3Dcompatible-local] 205 | for (int i =3D 0; i < sizeof(MMVector); i +=3D sizeof(T= YPE)) { \ | ^ ../target/hexagon/op_helper.c:157:17: note: in expansion of macro =E2= =80=98SCATTER_OP_WRITE_TO_MEM=E2=80=99 157 | SCATTER_OP_WRITE_TO_MEM(uint16_t); | ^~~~~~~~~~~~~~~~~~~~~~~ ../target/hexagon/op_helper.c:135:9: note: shadowed declaration is here 135 | int i; | ^ In file included from ../target/hexagon/op_helper.c:31: ../target/hexagon/mmvec/macros.h:204:19: error: declaration of =E2=80= =98ra=E2=80=99 shadows a previous local [-Werror=3Dshadow=3Dcompatible-loca= l] 204 | uintptr_t ra =3D GETPC(); \ | ^~ ../target/hexagon/op_helper.c:160:17: note: in expansion of macro =E2= =80=98SCATTER_OP_WRITE_TO_MEM=E2=80=99 160 | SCATTER_OP_WRITE_TO_MEM(uint32_t); | ^~~~~~~~~~~~~~~~~~~~~~~ ../target/hexagon/op_helper.c:134:15: note: shadowed declaration is here 134 | uintptr_t ra =3D GETPC(); | ^~ Reviewed-by: Matheus Tavares Bernardino Signed-off-by: Brian Cain Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20231008220945.983643-3-bcain@quicinc.com> --- target/hexagon/imported/alu.idef | 6 +++--- target/hexagon/mmvec/macros.h | 2 +- target/hexagon/op_helper.c | 9 +++------ target/hexagon/translate.c | 10 +++++----- 4 files changed, 12 insertions(+), 15 deletions(-) diff --git a/target/hexagon/imported/alu.idef b/target/hexagon/imported/alu= .idef index 12d2aac5d4..b855676989 100644 --- a/target/hexagon/imported/alu.idef +++ b/target/hexagon/imported/alu.idef @@ -1142,9 +1142,9 @@ Q6INSN(A4_cround_rr,"Rd32=3Dcround(Rs32,Rt32)",ATTRIB= S(),"Convergent Round", {RdV tmp128 =3D fSHIFTR128(tmp128, SHIFT);\ DST =3D fCAST16S_8S(tmp128);\ } else {\ - size16s_t rndbit_128 =3D fCAST8S_16S((1LL << (SHIFT - 1))); \ - size16s_t src_128 =3D fCAST8S_16S(SRC); \ - size16s_t tmp128 =3D fADD128(src_128, rndbit_128);\ + rndbit_128 =3D fCAST8S_16S((1LL << (SHIFT - 1))); \ + src_128 =3D fCAST8S_16S(SRC); \ + tmp128 =3D fADD128(src_128, rndbit_128);\ tmp128 =3D fSHIFTR128(tmp128, SHIFT);\ DST =3D fCAST16S_8S(tmp128);\ } diff --git a/target/hexagon/mmvec/macros.h b/target/hexagon/mmvec/macros.h index a655634fd1..1ceb9453ee 100644 --- a/target/hexagon/mmvec/macros.h +++ b/target/hexagon/mmvec/macros.h @@ -201,7 +201,7 @@ } while (0) #define SCATTER_OP_WRITE_TO_MEM(TYPE) \ do { \ - uintptr_t ra =3D GETPC(); \ + ra =3D GETPC(); \ for (int i =3D 0; i < sizeof(MMVector); i +=3D sizeof(TYPE)) { \ if (test_bit(i, env->vtcm_log.mask)) { \ TYPE dst =3D 0; \ diff --git a/target/hexagon/op_helper.c b/target/hexagon/op_helper.c index 8ca3976a65..da10ac5847 100644 --- a/target/hexagon/op_helper.c +++ b/target/hexagon/op_helper.c @@ -132,10 +132,9 @@ void HELPER(gather_store)(CPUHexagonState *env, uint32= _t addr, int slot) void HELPER(commit_hvx_stores)(CPUHexagonState *env) { uintptr_t ra =3D GETPC(); - int i; =20 /* Normal (possibly masked) vector store */ - for (i =3D 0; i < VSTORES_MAX; i++) { + for (int i =3D 0; i < VSTORES_MAX; i++) { if (env->vstore_pending[i]) { env->vstore_pending[i] =3D 0; target_ulong va =3D env->vstore[i].va; @@ -162,7 +161,7 @@ void HELPER(commit_hvx_stores)(CPUHexagonState *env) g_assert_not_reached(); } } else { - for (i =3D 0; i < sizeof(MMVector); i++) { + for (int i =3D 0; i < sizeof(MMVector); i++) { if (test_bit(i, env->vtcm_log.mask)) { cpu_stb_data_ra(env, env->vtcm_log.va[i], env->vtcm_log.data.ub[i], ra); @@ -505,10 +504,8 @@ void HELPER(probe_pkt_scalar_store_s0)(CPUHexagonState= *env, int args) static void probe_hvx_stores(CPUHexagonState *env, int mmu_idx, uintptr_t retaddr) { - int i; - /* Normal (possibly masked) vector store */ - for (i =3D 0; i < VSTORES_MAX; i++) { + for (int i =3D 0; i < VSTORES_MAX; i++) { if (env->vstore_pending[i]) { target_ulong va =3D env->vstore[i].va; int size =3D env->vstore[i].size; diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c index 663b7bbc3a..666c061180 100644 --- a/target/hexagon/translate.c +++ b/target/hexagon/translate.c @@ -553,7 +553,7 @@ static void gen_start_packet(DisasContext *ctx) /* Preload the predicated registers into get_result_gpr(ctx, i) */ if (ctx->need_commit && !bitmap_empty(ctx->predicated_regs, TOTAL_PER_THREAD_REGS)) { - int i =3D find_first_bit(ctx->predicated_regs, TOTAL_PER_THREAD_RE= GS); + i =3D find_first_bit(ctx->predicated_regs, TOTAL_PER_THREAD_REGS); while (i < TOTAL_PER_THREAD_REGS) { tcg_gen_mov_tl(get_result_gpr(ctx, i), hex_gpr[i]); i =3D find_next_bit(ctx->predicated_regs, TOTAL_PER_THREAD_REG= S, @@ -566,7 +566,7 @@ static void gen_start_packet(DisasContext *ctx) * Only endloop instructions conditionally write to pred registers */ if (ctx->need_commit && pkt->pkt_has_endloop) { - for (int i =3D 0; i < ctx->preg_log_idx; i++) { + for (i =3D 0; i < ctx->preg_log_idx; i++) { int pred_num =3D ctx->preg_log[i]; ctx->new_pred_value[pred_num] =3D tcg_temp_new(); tcg_gen_mov_tl(ctx->new_pred_value[pred_num], hex_pred[pred_nu= m]); @@ -575,7 +575,7 @@ static void gen_start_packet(DisasContext *ctx) =20 /* Preload the predicated HVX registers into future_VRegs and tmp_VReg= s */ if (!bitmap_empty(ctx->predicated_future_vregs, NUM_VREGS)) { - int i =3D find_first_bit(ctx->predicated_future_vregs, NUM_VREGS); + i =3D find_first_bit(ctx->predicated_future_vregs, NUM_VREGS); while (i < NUM_VREGS) { const intptr_t VdV_off =3D ctx_future_vreg_off(ctx, i, 1, true); @@ -588,7 +588,7 @@ static void gen_start_packet(DisasContext *ctx) } } if (!bitmap_empty(ctx->predicated_tmp_vregs, NUM_VREGS)) { - int i =3D find_first_bit(ctx->predicated_tmp_vregs, NUM_VREGS); + i =3D find_first_bit(ctx->predicated_tmp_vregs, NUM_VREGS); while (i < NUM_VREGS) { const intptr_t VdV_off =3D ctx_tmp_vreg_off(ctx, i, 1, true); @@ -1228,7 +1228,7 @@ void hexagon_translate_init(void) offsetof(CPUHexagonState, mem_log_stores[i].data64), store_val64_names[i]); } - for (int i =3D 0; i < VSTORES_MAX; i++) { + for (i =3D 0; i < VSTORES_MAX; i++) { snprintf(vstore_addr_names[i], NAME_LEN, "vstore_addr_%d", i); hex_vstore_addr[i] =3D tcg_global_mem_new(tcg_env, offsetof(CPUHexagonState, vstore[i].va), --=20 2.25.1