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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697668046296100002 Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target.c.inc | 161 ++++++++++++++++++------------------- 1 file changed, 79 insertions(+), 82 deletions(-) diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index 4ef9ac3d5b..fbee43d3b0 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -46,9 +46,7 @@ /* A scratch register that may be be used throughout the backend. */ #define TCG_TMP0 TCG_REG_R1 =20 -#ifndef CONFIG_SOFTMMU #define TCG_GUEST_BASE_REG TCG_REG_R13 -#endif =20 /* All of the following instructions are prefixed with their instruction format, and are defined as 8- or 16-bit quantities, even when the two @@ -1768,94 +1766,95 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGConte= xt *s, HostAddress *h, h->aa =3D atom_and_align_for_opc(s, opc, MO_ATOM_IFALIGN, s_bits =3D= =3D MO_128); a_mask =3D (1 << h->aa.align) - 1; =20 -#ifdef CONFIG_SOFTMMU - unsigned s_mask =3D (1 << s_bits) - 1; - int mem_index =3D get_mmuidx(oi); - int fast_off =3D tlb_mask_table_ofs(s, mem_index); - int mask_off =3D fast_off + offsetof(CPUTLBDescFast, mask); - int table_off =3D fast_off + offsetof(CPUTLBDescFast, table); - int ofs, a_off; - uint64_t tlb_mask; + if (tcg_use_softmmu) { + unsigned s_mask =3D (1 << s_bits) - 1; + int mem_index =3D get_mmuidx(oi); + int fast_off =3D tlb_mask_table_ofs(s, mem_index); + int mask_off =3D fast_off + offsetof(CPUTLBDescFast, mask); + int table_off =3D fast_off + offsetof(CPUTLBDescFast, table); + int ofs, a_off; + uint64_t tlb_mask; =20 - ldst =3D new_ldst_label(s); - ldst->is_ld =3D is_ld; - ldst->oi =3D oi; - ldst->addrlo_reg =3D addr_reg; - - tcg_out_sh64(s, RSY_SRLG, TCG_TMP0, addr_reg, TCG_REG_NONE, - s->page_bits - CPU_TLB_ENTRY_BITS); - - tcg_out_insn(s, RXY, NG, TCG_TMP0, TCG_AREG0, TCG_REG_NONE, mask_off); - tcg_out_insn(s, RXY, AG, TCG_TMP0, TCG_AREG0, TCG_REG_NONE, table_off); - - /* - * For aligned accesses, we check the first byte and include the align= ment - * bits within the address. For unaligned access, we check that we do= n't - * cross pages using the address of the last byte of the access. - */ - a_off =3D (a_mask >=3D s_mask ? 0 : s_mask - a_mask); - tlb_mask =3D (uint64_t)s->page_mask | a_mask; - if (a_off =3D=3D 0) { - tgen_andi_risbg(s, TCG_REG_R0, addr_reg, tlb_mask); - } else { - tcg_out_insn(s, RX, LA, TCG_REG_R0, addr_reg, TCG_REG_NONE, a_off); - tgen_andi(s, addr_type, TCG_REG_R0, tlb_mask); - } - - if (is_ld) { - ofs =3D offsetof(CPUTLBEntry, addr_read); - } else { - ofs =3D offsetof(CPUTLBEntry, addr_write); - } - if (addr_type =3D=3D TCG_TYPE_I32) { - ofs +=3D HOST_BIG_ENDIAN * 4; - tcg_out_insn(s, RX, C, TCG_REG_R0, TCG_TMP0, TCG_REG_NONE, ofs); - } else { - tcg_out_insn(s, RXY, CG, TCG_REG_R0, TCG_TMP0, TCG_REG_NONE, ofs); - } - - tcg_out16(s, RI_BRC | (S390_CC_NE << 4)); - ldst->label_ptr[0] =3D s->code_ptr++; - - h->index =3D TCG_TMP0; - tcg_out_insn(s, RXY, LG, h->index, TCG_TMP0, TCG_REG_NONE, - offsetof(CPUTLBEntry, addend)); - - if (addr_type =3D=3D TCG_TYPE_I32) { - tcg_out_insn(s, RRE, ALGFR, h->index, addr_reg); - h->base =3D TCG_REG_NONE; - } else { - h->base =3D addr_reg; - } - h->disp =3D 0; -#else - if (a_mask) { ldst =3D new_ldst_label(s); ldst->is_ld =3D is_ld; ldst->oi =3D oi; ldst->addrlo_reg =3D addr_reg; =20 - /* We are expecting a_bits to max out at 7, much lower than TMLL. = */ - tcg_debug_assert(a_mask <=3D 0xffff); - tcg_out_insn(s, RI, TMLL, addr_reg, a_mask); + tcg_out_sh64(s, RSY_SRLG, TCG_TMP0, addr_reg, TCG_REG_NONE, + s->page_bits - CPU_TLB_ENTRY_BITS); =20 - tcg_out16(s, RI_BRC | (7 << 4)); /* CC in {1,2,3} */ + tcg_out_insn(s, RXY, NG, TCG_TMP0, TCG_AREG0, TCG_REG_NONE, mask_o= ff); + tcg_out_insn(s, RXY, AG, TCG_TMP0, TCG_AREG0, TCG_REG_NONE, table_= off); + + /* + * For aligned accesses, we check the first byte and include the + * alignment bits within the address. For unaligned access, we + * check that we don't cross pages using the address of the last + * byte of the access. + */ + a_off =3D (a_mask >=3D s_mask ? 0 : s_mask - a_mask); + tlb_mask =3D (uint64_t)s->page_mask | a_mask; + if (a_off =3D=3D 0) { + tgen_andi_risbg(s, TCG_REG_R0, addr_reg, tlb_mask); + } else { + tcg_out_insn(s, RX, LA, TCG_REG_R0, addr_reg, TCG_REG_NONE, a_= off); + tgen_andi(s, addr_type, TCG_REG_R0, tlb_mask); + } + + if (is_ld) { + ofs =3D offsetof(CPUTLBEntry, addr_read); + } else { + ofs =3D offsetof(CPUTLBEntry, addr_write); + } + if (addr_type =3D=3D TCG_TYPE_I32) { + ofs +=3D HOST_BIG_ENDIAN * 4; + tcg_out_insn(s, RX, C, TCG_REG_R0, TCG_TMP0, TCG_REG_NONE, ofs= ); + } else { + tcg_out_insn(s, RXY, CG, TCG_REG_R0, TCG_TMP0, TCG_REG_NONE, o= fs); + } + + tcg_out16(s, RI_BRC | (S390_CC_NE << 4)); ldst->label_ptr[0] =3D s->code_ptr++; - } =20 - h->base =3D addr_reg; - if (addr_type =3D=3D TCG_TYPE_I32) { - tcg_out_ext32u(s, TCG_TMP0, addr_reg); - h->base =3D TCG_TMP0; - } - if (guest_base < 0x80000) { - h->index =3D TCG_REG_NONE; - h->disp =3D guest_base; - } else { - h->index =3D TCG_GUEST_BASE_REG; + h->index =3D TCG_TMP0; + tcg_out_insn(s, RXY, LG, h->index, TCG_TMP0, TCG_REG_NONE, + offsetof(CPUTLBEntry, addend)); + + if (addr_type =3D=3D TCG_TYPE_I32) { + tcg_out_insn(s, RRE, ALGFR, h->index, addr_reg); + h->base =3D TCG_REG_NONE; + } else { + h->base =3D addr_reg; + } h->disp =3D 0; + } else { + if (a_mask) { + ldst =3D new_ldst_label(s); + ldst->is_ld =3D is_ld; + ldst->oi =3D oi; + ldst->addrlo_reg =3D addr_reg; + + /* We are expecting a_bits to max out at 7, much lower than TM= LL. */ + tcg_debug_assert(a_mask <=3D 0xffff); + tcg_out_insn(s, RI, TMLL, addr_reg, a_mask); + + tcg_out16(s, RI_BRC | (7 << 4)); /* CC in {1,2,3} */ + ldst->label_ptr[0] =3D s->code_ptr++; + } + + h->base =3D addr_reg; + if (addr_type =3D=3D TCG_TYPE_I32) { + tcg_out_ext32u(s, TCG_TMP0, addr_reg); + h->base =3D TCG_TMP0; + } + if (guest_base < 0x80000) { + h->index =3D TCG_REG_NONE; + h->disp =3D guest_base; + } else { + h->index =3D TCG_GUEST_BASE_REG; + h->disp =3D 0; + } } -#endif =20 return ldst; } @@ -3453,12 +3452,10 @@ static void tcg_target_qemu_prologue(TCGContext *s) TCG_STATIC_CALL_ARGS_SIZE + TCG_TARGET_CALL_STACK_OFFSET, CPU_TEMP_BUF_NLONGS * sizeof(long)); =20 -#ifndef CONFIG_SOFTMMU - if (guest_base >=3D 0x80000) { + if (!tcg_use_softmmu && guest_base >=3D 0x80000) { tcg_out_movi(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base); tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG); } -#endif =20 tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]); =20 --=20 2.34.1