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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697668006448100005 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target.c.inc | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index 5c873b2161..5cecc6ed95 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -221,7 +221,7 @@ static inline bool in_range_b(tcg_target_long target) } =20 static uint32_t reloc_pc24_val(const tcg_insn_unit *pc, - const tcg_insn_unit *target) + const tcg_insn_unit *target) { ptrdiff_t disp =3D tcg_ptr_byte_diff(target, pc); tcg_debug_assert(in_range_b(disp)); @@ -241,7 +241,7 @@ static bool reloc_pc24(tcg_insn_unit *src_rw, const tcg= _insn_unit *target) } =20 static uint16_t reloc_pc14_val(const tcg_insn_unit *pc, - const tcg_insn_unit *target) + const tcg_insn_unit *target) { ptrdiff_t disp =3D tcg_ptr_byte_diff(target, pc); tcg_debug_assert(disp =3D=3D (int16_t) disp); @@ -3645,7 +3645,7 @@ static void expand_vec_mul(TCGType type, unsigned vec= e, TCGv_vec v0, tcgv_vec_arg(t1), tcgv_vec_arg(t2)); vec_gen_3(INDEX_op_ppc_pkum_vec, type, vece, tcgv_vec_arg(v0), tcgv_vec_arg(v0), tcgv_vec_arg(t1)); - break; + break; =20 case MO_32: tcg_debug_assert(!have_isa_2_07); --=20 2.34.1 From nobody Wed Nov 27 17:32:24 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id 13-20020a170902c24d00b001b9d95945afsm431058plg.155.2023.10.18.15.26.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Oct 2023 15:26:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1697667961; x=1698272761; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=kPve6f7zLeYUZnfvyB8rknIVGRQNk3b6m8Mg7HCCt/Y=; b=LyqoCBKSXgOhNbFpNyFcfdyaUoJkRNT6j5UddR8E7CzsoyNFfcodk2uFIAPG58mP16 37Ro+FCgQUdETT0+oAiyUBaYSGmBetBze048O+ExcSS1k/7tLSQeMplqaQSt21dXhD1u RQUIJgXpoh1QYm9SoN4wb3sA/gOZs2F+tRBWZw601Sxxks4TCFevot8mBfuycTLfzzCh 3qvDcYFmTfz0/KLn0g8qGEpUNSxH10fdoP++OOTdpRqSsymw9xexjvw0e9E1RN1k+LaR pLJnSzIfwttxWk3vAvPAvkulhkh+tbCkIj+Kb9UXF+KZpIInyIoliKtYL79+B2xp0Khx mYfg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697667961; x=1698272761; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=kPve6f7zLeYUZnfvyB8rknIVGRQNk3b6m8Mg7HCCt/Y=; b=Oqdi7xAoF+JIqLWzFZXToTgZYZlyviNVZvP1IZdgyAYzXYKHGNtcW+e4k/PxB490KU 5EA0Ab3J/wp6Uik12R6l5KFlciJozqX3NRqCTcw5dM0jRT7B1Xa0yUDx/29ITkrr13F1 dojYgx1q95/Dbqsfx0zV0N4PNXUH2YW3+CDZeO29oLbS7o7B6Ahgf+/c43pehP8ddZX+ mjJm9uALYDLG0IXvtkUSOstyjfkVjwJXqJYnlZOOJnfoQT7gmHgNSQJWlioi2Ewmk2Ax 0gJKJpywC3zM7rD52QrtpAQru5qY4LrevgjJi4ye0ZPLD1sexADBMF4mnSa/+3Caksze 4m9Q== X-Gm-Message-State: AOJu0YxMHkHHSXPYX2qZPVV7ZgKhFrUZRcp8vOc19jwaOMh9M9Rfkb83 Rmn9EbfWldjTAf4VUopdnbWNzsX8uq21/t7/N2I= X-Google-Smtp-Source: AGHT+IHUF7TbNMAlf7TBvanqhJidbhc+e5abNlYPu5dK+LN38NeW4kN97JV9VLLIpSQDAb7onTJLIA== X-Received: by 2002:a17:903:228b:b0:1c9:b196:d294 with SMTP id b11-20020a170903228b00b001c9b196d294mr887746plh.20.1697667960944; Wed, 18 Oct 2023 15:26:00 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Jordan Niethe Subject: [PULL 02/29] tcg/ppc: Enable direct branching tcg_out_goto_tb with TCG_REG_TB Date: Wed, 18 Oct 2023 15:25:30 -0700 Message-Id: <20231018222557.1562065-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231018222557.1562065-1-richard.henderson@linaro.org> References: <20231018222557.1562065-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697668122637100001 Content-Type: text/plain; charset="utf-8" From: Jordan Niethe Direct branch patching was disabled when using TCG_REG_TB in commit 736a1588c1 ("tcg/ppc: Fix race in goto_tb implementation"). The issue with direct branch patching with TCG_REG_TB is the lack of synchronization between the new TCG_REG_TB being established and the direct branch being patched in. If each translation block is responsible for establishing its own TCG_REG_TB then there can be no synchronization issue. Make each translation block begin by setting up its own TCG_REG_TB. Use the preferred 'bcl 20,31,$+4' sequence. Signed-off-by: Jordan Niethe [rth: Split out tcg_out_tb_start, power9 addpcis] Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target.c.inc | 48 ++++++++++++++-------------------------- 1 file changed, 17 insertions(+), 31 deletions(-) diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index 5cecc6ed95..9197cfd6c6 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -2509,9 +2509,6 @@ static void tcg_target_qemu_prologue(TCGContext *s) =20 tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]); tcg_out32(s, MTSPR | RS(tcg_target_call_iarg_regs[1]) | CTR); - if (USE_REG_TB) { - tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB, tcg_target_call_iarg_regs= [1]); - } tcg_out32(s, BCCTR | BO_ALWAYS); =20 /* Epilogue */ @@ -2529,7 +2526,13 @@ static void tcg_target_qemu_prologue(TCGContext *s) =20 static void tcg_out_tb_start(TCGContext *s) { - /* nothing to do */ + /* Load TCG_REG_TB. */ + if (USE_REG_TB) { + /* bcl 20,31,$+4 (preferred form for getting nia) */ + tcg_out32(s, BC | BO_ALWAYS | BI(7, CR_SO) | 0x4 | LK); + tcg_out32(s, MFSPR | RT(TCG_REG_TB) | LR); + tcg_out32(s, ADDI | TAI(TCG_REG_TB, TCG_REG_TB, -4)); + } } =20 static void tcg_out_exit_tb(TCGContext *s, uintptr_t arg) @@ -2542,32 +2545,22 @@ static void tcg_out_goto_tb(TCGContext *s, int whic= h) { uintptr_t ptr =3D get_jmp_target_addr(s, which); =20 + /* Direct branch will be patched by tb_target_set_jmp_target. */ + set_jmp_insn_offset(s, which); + tcg_out32(s, NOP); + + /* When branch is out of range, fall through to indirect. */ if (USE_REG_TB) { ptrdiff_t offset =3D tcg_tbrel_diff(s, (void *)ptr); - tcg_out_mem_long(s, LD, LDX, TCG_REG_TB, TCG_REG_TB, offset); - =20 - /* TODO: Use direct branches when possible. */ - set_jmp_insn_offset(s, which); - tcg_out32(s, MTSPR | RS(TCG_REG_TB) | CTR); - - tcg_out32(s, BCCTR | BO_ALWAYS); - - /* For the unlinked case, need to reset TCG_REG_TB. */ - set_jmp_reset_offset(s, which); - tcg_out_mem_long(s, ADDI, ADD, TCG_REG_TB, TCG_REG_TB, - -tcg_current_code_size(s)); + tcg_out_mem_long(s, LD, LDX, TCG_REG_TMP1, TCG_REG_TB, offset); } else { - /* Direct branch will be patched by tb_target_set_jmp_target. */ - set_jmp_insn_offset(s, which); - tcg_out32(s, NOP); - - /* When branch is out of range, fall through to indirect. */ tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP1, ptr - (int16_t)ptr); tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, TCG_REG_TMP1, (int16_t)p= tr); - tcg_out32(s, MTSPR | RS(TCG_REG_TMP1) | CTR); - tcg_out32(s, BCCTR | BO_ALWAYS); - set_jmp_reset_offset(s, which); } + + tcg_out32(s, MTSPR | RS(TCG_REG_TMP1) | CTR); + tcg_out32(s, BCCTR | BO_ALWAYS); + set_jmp_reset_offset(s, which); } =20 void tb_target_set_jmp_target(const TranslationBlock *tb, int n, @@ -2577,10 +2570,6 @@ void tb_target_set_jmp_target(const TranslationBlock= *tb, int n, intptr_t diff =3D addr - jmp_rx; tcg_insn_unit insn; =20 - if (USE_REG_TB) { - return; - } - if (in_range_b(diff)) { insn =3D B | (diff & 0x3fffffc); } else { @@ -2600,9 +2589,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, switch (opc) { case INDEX_op_goto_ptr: tcg_out32(s, MTSPR | RS(args[0]) | CTR); - if (USE_REG_TB) { - tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB, args[0]); - } tcg_out32(s, ADDI | TAI(TCG_REG_R3, 0, 0)); tcg_out32(s, BCCTR | BO_ALWAYS); break; --=20 2.34.1 From nobody Wed Nov 27 17:32:24 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1697668360; cv=none; d=zohomail.com; s=zohoarc; b=UqPyT8gMCwYYoegdlyxLUQ9Ub9LmD9DP4ZFJ+X6+qGWolrtMy/Tf988oFxWqrVfmdBhuCBa3XMUc/KLAAfJwcz7vUaNcsbavVLu/uqb33oYRqzX+1oOIEjHH/Gu3/mc06Z8zQrZhYjOaRo/SZp0L64hOe5inAvnDFAKF9mRaryA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1697668360; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id 13-20020a170902c24d00b001b9d95945afsm431058plg.155.2023.10.18.15.26.01 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Oct 2023 15:26:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1697667962; x=1698272762; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=3KCQIgln5kN/33Jyz8B+r1A500q3A4Jm4TEcmcp8vS8=; b=mVigu8Kp9SA8yT2LI8jyFYPC+KY3z7/tBOTkMPNiA0G6XVF8hVcfPJKj6Ax83ZZbHy adMQZMOXWMruGl5kgbvAvIhhwf8Swi2mKEnDAa8EA6pyLpuN4IKtgnm+71g7UdtYRria dp6KbGZ8JBmKYd9b+DhJqBxXzJ6Zdyyzh52nzBby4HwDIAAVwdZPkusSjwHAaiouPVAo EcSn5amWN6b+EC9U/PsK2G3OJmc+yDec3cvVJ7X6IJNsE3J5CUyX8/ZlYftsz0O7B+iU 9UIF0oeR7/CWdch0nTkXgKzF5uvfWAktb5zCOsAPUgDMyMF8uVFRVmPUpKEimxdRuGrW taKg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697667962; x=1698272762; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=3KCQIgln5kN/33Jyz8B+r1A500q3A4Jm4TEcmcp8vS8=; b=UFMB0ziXz5nQdGz3F6QBinVSfEk36kDENGrOOxd0RbaBI8Wta2no3sH/7QzcnLZaUL 8Jz/r1SBPt1bmuBdyQTBMBqhsm8bJXi9kaQr3ZEaEf3I6hqcWNTlfRZk5Z1H9I1mK5gI OWc9C20FPZfwKTCiy7kOnDQYhLD6Lqyec/rnUM8owdBIft6FIK1b3QXXJNM/uw8XVVuy 5ZO9exznjfS0iONVk1SY/Lvx3Okf/RM/xwFlZu183cxeMI8HaNcG3WcDHgIC7y+uPz05 uwETyus5+fR+RfoSau/jciQA3wVSoQOKnMLwzIOnwx6qSBUuneTl1sk/OLZoLMLWVRwy twyQ== X-Gm-Message-State: AOJu0YznNYsCegk5nkvToc5WgZ1uY021K1KOSKPa/PMV2w5afZJtiXTz boNmM0eCMsoumRNZpjeMXht7TqYlFUxeAWNOpM8= X-Google-Smtp-Source: AGHT+IGuZ/CzxNXTYxYbO2n8DpimxEgr35tCRESsytN+NO1Vc8WTbRtaZXwDaIywji7hVYVXPdSy0g== X-Received: by 2002:a17:902:ec85:b0:1b8:954c:1f6 with SMTP id x5-20020a170902ec8500b001b8954c01f6mr669586plg.36.1697667961760; Wed, 18 Oct 2023 15:26:01 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 03/29] tcg/ppc: Reinterpret tb-relative to TB+4 Date: Wed, 18 Oct 2023 15:25:31 -0700 Message-Id: <20231018222557.1562065-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231018222557.1562065-1-richard.henderson@linaro.org> References: <20231018222557.1562065-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697668361666100007 Content-Type: text/plain; charset="utf-8" It saves one insn to load the address of TB+4 instead of TB. Adjust all of the indexing to match. Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target.c.inc | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index 9197cfd6c6..aafbf2db4e 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -215,6 +215,12 @@ static const int tcg_target_callee_save_regs[] =3D { TCG_REG_R31 }; =20 +/* For PPC, we use TB+4 instead of TB as the base. */ +static inline ptrdiff_t ppc_tbrel_diff(TCGContext *s, const void *target) +{ + return tcg_tbrel_diff(s, target) - 4; +} + static inline bool in_range_b(tcg_target_long target) { return target =3D=3D sextract64(target, 0, 26); @@ -991,7 +997,7 @@ static void tcg_out_movi_int(TCGContext *s, TCGType typ= e, TCGReg ret, } =20 /* Load addresses within the TB with one insn. */ - tb_diff =3D tcg_tbrel_diff(s, (void *)arg); + tb_diff =3D ppc_tbrel_diff(s, (void *)arg); if (!in_prologue && USE_REG_TB && tb_diff =3D=3D (int16_t)tb_diff) { tcg_out32(s, ADDI | TAI(ret, TCG_REG_TB, tb_diff)); return; @@ -1044,7 +1050,7 @@ static void tcg_out_movi_int(TCGContext *s, TCGType t= ype, TCGReg ret, /* Use the constant pool, if possible. */ if (!in_prologue && USE_REG_TB) { new_pool_label(s, arg, R_PPC_ADDR16, s->code_ptr, - tcg_tbrel_diff(s, NULL)); + ppc_tbrel_diff(s, NULL)); tcg_out32(s, LD | TAI(ret, TCG_REG_TB, 0)); return; } @@ -1104,7 +1110,7 @@ static void tcg_out_dupi_vec(TCGContext *s, TCGType t= ype, unsigned vece, */ if (USE_REG_TB) { rel =3D R_PPC_ADDR16; - add =3D tcg_tbrel_diff(s, NULL); + add =3D ppc_tbrel_diff(s, NULL); } else { rel =3D R_PPC_ADDR32; add =3D 0; @@ -2531,7 +2537,6 @@ static void tcg_out_tb_start(TCGContext *s) /* bcl 20,31,$+4 (preferred form for getting nia) */ tcg_out32(s, BC | BO_ALWAYS | BI(7, CR_SO) | 0x4 | LK); tcg_out32(s, MFSPR | RT(TCG_REG_TB) | LR); - tcg_out32(s, ADDI | TAI(TCG_REG_TB, TCG_REG_TB, -4)); } } =20 @@ -2551,7 +2556,7 @@ static void tcg_out_goto_tb(TCGContext *s, int which) =20 /* When branch is out of range, fall through to indirect. */ if (USE_REG_TB) { - ptrdiff_t offset =3D tcg_tbrel_diff(s, (void *)ptr); + ptrdiff_t offset =3D ppc_tbrel_diff(s, (void *)ptr); tcg_out_mem_long(s, LD, LDX, TCG_REG_TMP1, TCG_REG_TB, offset); } else { tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP1, ptr - (int16_t)ptr); --=20 2.34.1 From nobody Wed Nov 27 17:32:24 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1697668381; cv=none; d=zohomail.com; s=zohoarc; b=SkgCKoNrSyNyJ4qTeKlMWWVaF87KxFN8b8HuDk8gZ2UGxj5LYQW+TPGCktb/SjCsXtnhpXmOMKbgbX2STlkk+wpLlMHQRjRkjlIAHmQN3IEvivuatf/HLkrG/PPBmpvhbQdx5ZCVjpEcCGTdX3VhEAZqfAKd1IOwfkHuNt0xjz4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1697668381; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=ll1AHH/tNyWuM8OWYdUz/S/zYn03mj8222BJRAroDbQ=; b=RrAxqRrX67/zCeuFpPOcC9F4olUIdnMfgNF3sb2cFfhZ4+SrI46gl/ITSiYK+uLmZyYAkFo21zfk/76JMXhxd+6byKrxccBiW8mub0mOcZxX+5fJPqIknKmT9vP7syheIwGFEu3l7IEhbJbs0CWDWBjGJuUgzTxqY07GGNeUDp4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1697668381951530.0434702444761; Wed, 18 Oct 2023 15:33:01 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qtEzP-00083v-K7; Wed, 18 Oct 2023 18:26:07 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qtEzN-00082N-CG for qemu-devel@nongnu.org; Wed, 18 Oct 2023 18:26:05 -0400 Received: from mail-pl1-x62f.google.com ([2607:f8b0:4864:20::62f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qtEzL-0002S9-M9 for qemu-devel@nongnu.org; Wed, 18 Oct 2023 18:26:05 -0400 Received: by mail-pl1-x62f.google.com with SMTP id d9443c01a7336-1ca72f8ff3aso28054915ad.0 for ; Wed, 18 Oct 2023 15:26:03 -0700 (PDT) Received: from stoup.. ([71.212.149.95]) by smtp.gmail.com with ESMTPSA id 13-20020a170902c24d00b001b9d95945afsm431058plg.155.2023.10.18.15.26.01 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Oct 2023 15:26:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1697667962; x=1698272762; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=ll1AHH/tNyWuM8OWYdUz/S/zYn03mj8222BJRAroDbQ=; b=htZQrut+kscvqV6XTHK9BlBpuw5Zj/b3SGv0R4/ehx3rqPhoLQpbQuOexDHIgblTgL 7xqDCc/LYfGReol9hP/tXBeyXiGAmhvb4EGFsoN2/RvlUYKTxEYrsa8crNzRH4a0zdev qLNjRHknHOuXejQqhJnAetiIIziEHYMmzi66SDNOhfrQ6ba/LrHxIXrkVq5JUyVu2prb +7iRnnRPKT2NlRZwSh22GDc2xERu7Gv61L19IySdOnTz5z9wt9/Ywv2gZwICHrO9kLdy csOBMQjOL/A83z7hpJUT1rxl24HByh4Sta1znZicUEb0zzpLBqWfDx0XgJFwzX0QqjHr hRjA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697667962; x=1698272762; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ll1AHH/tNyWuM8OWYdUz/S/zYn03mj8222BJRAroDbQ=; b=hqfv86bjrpPn/XmvSLcON0T1wY3R7hdhW9vLGiCs2pakNDzVOm1CsCK2gt4giW3ze5 HxXU2XMkFpmQGtSqNbvkVugAEK1m/WyNx2jX3yVaDKYQ4QqJ18LTJfKFGxDr8NQMzVgM Mbj9M+EnkcH1AJjChWz4HklxKtJRJA/KpUH55OCxetW1ngIloeey1Fn2YpZ/OyDhG6EW rE92G5RZ/n06xvtrsLvpOGlj/EKZqrWqKuJcbNJ06YzNeeC463sbaFglVQnsKfy+ETTD Cn9nYBJ4/LYm6mjon/sA0f9ven39W1CO0yeHm0CPFsO8ksnBc/WDPbg0UlrexMbaWQvM F1Ag== X-Gm-Message-State: AOJu0Yz/7BvYZ3ni8b760mABcE/7DdBQ61ArOH1JXZZTCrGSoQn5AEvb CAPTAoCGXcFf/mM2tTmtymwfTveHFHpNpIA4rEk= X-Google-Smtp-Source: AGHT+IFpyxBEZs6tLNJHz5/QrgDo/KN8fpny3gnMMd+Fe2lmyiyYOIghIbDD06rQ9M6iok8fDq0Reg== X-Received: by 2002:a17:903:22c7:b0:1c3:2df4:8791 with SMTP id y7-20020a17090322c700b001c32df48791mr824107plg.27.1697667962471; Wed, 18 Oct 2023 15:26:02 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 04/29] tcg/ppc: Use ADDPCIS in tcg_out_tb_start Date: Wed, 18 Oct 2023 15:25:32 -0700 Message-Id: <20231018222557.1562065-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231018222557.1562065-1-richard.henderson@linaro.org> References: <20231018222557.1562065-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697668383730100003 Content-Type: text/plain; charset="utf-8" With ISA v3.0, we can use ADDPCIS instead of BCL+MFLR to load NIA. Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target.c.inc | 25 ++++++++++++++++++++++--- 1 file changed, 22 insertions(+), 3 deletions(-) diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index aafbf2db4e..b0b8cd2390 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -362,6 +362,7 @@ static bool tcg_target_const_match(int64_t val, TCGType= type, int ct, int vece) #define CRNAND XO19(225) #define CROR XO19(449) #define CRNOR XO19( 33) +#define ADDPCIS XO19( 2) =20 #define EXTSB XO31(954) #define EXTSH XO31(922) @@ -859,6 +860,19 @@ static inline void tcg_out_sari64(TCGContext *s, TCGRe= g dst, TCGReg src, int c) tcg_out32(s, SRADI | RA(dst) | RS(src) | SH(c & 0x1f) | ((c >> 4) & 2)= ); } =20 +static void tcg_out_addpcis(TCGContext *s, TCGReg dst, intptr_t imm) +{ + uint32_t d0, d1, d2; + + tcg_debug_assert((imm & 0xffff) =3D=3D 0); + tcg_debug_assert(imm =3D=3D (int32_t)imm); + + d2 =3D extract32(imm, 16, 1); + d1 =3D extract32(imm, 17, 5); + d0 =3D extract32(imm, 22, 10); + tcg_out32(s, ADDPCIS | RT(dst) | (d1 << 16) | (d0 << 6) | d2); +} + static void tcg_out_bswap16(TCGContext *s, TCGReg dst, TCGReg src, int fla= gs) { TCGReg tmp =3D dst =3D=3D src ? TCG_REG_R0 : dst; @@ -2534,9 +2548,14 @@ static void tcg_out_tb_start(TCGContext *s) { /* Load TCG_REG_TB. */ if (USE_REG_TB) { - /* bcl 20,31,$+4 (preferred form for getting nia) */ - tcg_out32(s, BC | BO_ALWAYS | BI(7, CR_SO) | 0x4 | LK); - tcg_out32(s, MFSPR | RT(TCG_REG_TB) | LR); + if (have_isa_3_00) { + /* lnia REG_TB */ + tcg_out_addpcis(s, TCG_REG_TB, 0); + } else { + /* bcl 20,31,$+4 (preferred form for getting nia) */ + tcg_out32(s, BC | BO_ALWAYS | BI(7, CR_SO) | 0x4 | LK); + tcg_out32(s, MFSPR | RT(TCG_REG_TB) | LR); + } } } =20 --=20 2.34.1 From nobody Wed Nov 27 17:32:24 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1697668287; cv=none; d=zohomail.com; s=zohoarc; b=RLEO/LvgNtQloMU6i5aI38plKiIafvTq2wHtEQFNEl7FgrHBBe42idHXX1I2MsDsHQNIMuiOoQGnAgMANF0mmKM5sZEvG4kLdNGhUj5mYGZjIU6q8pPodbps7uJhQjHRy/58miX6APhYgqoxfr3Hxi+PS+jwOy92eWJrvs6LiK8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1697668287; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=kj+TKk2K3WfpkaNPPr/v3KoLmzqb4EREhy9sjMrwx20=; b=GBP10UQoD0THVCmiiPy3XO/mVx6AdayCkbuD6UDtnKCbL4kgN/UtiyE2oec0B0pVBKJwV4q0ghl9JggJGlQpOr+dtTRBPy78lucQbEZsiya2EAa2MpRRyCLe0eg3zzCyxHsxGwIDh56SgFcAkUBkoAFQUe4Fe11ZTvbioDjJg18= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1697668287814157.09634447718292; Wed, 18 Oct 2023 15:31:27 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qtEzO-00083P-QD; Wed, 18 Oct 2023 18:26:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qtEzO-00082l-10 for qemu-devel@nongnu.org; Wed, 18 Oct 2023 18:26:06 -0400 Received: from mail-pl1-x62b.google.com ([2607:f8b0:4864:20::62b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qtEzM-0002SU-IA for qemu-devel@nongnu.org; Wed, 18 Oct 2023 18:26:05 -0400 Received: by mail-pl1-x62b.google.com with SMTP id d9443c01a7336-1c9de3f66e5so47679365ad.3 for ; Wed, 18 Oct 2023 15:26:04 -0700 (PDT) Received: from stoup.. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697668289477100003 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target.c.inc | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index b0b8cd2390..226b5598ac 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -1055,6 +1055,19 @@ static void tcg_out_movi_int(TCGContext *s, TCGType = type, TCGReg ret, return; } =20 + /* Load addresses within 2GB with 2 insns. */ + if (have_isa_3_00) { + intptr_t hi =3D tcg_pcrel_diff(s, (void *)arg) - 4; + int16_t lo =3D hi; + + hi -=3D lo; + if (hi =3D=3D (int32_t)hi) { + tcg_out_addpcis(s, TCG_REG_TMP2, hi); + tcg_out32(s, ADDI | TAI(ret, TCG_REG_TMP2, lo)); + return; + } + } + /* Load addresses within 2GB of TB with 2 (or rarely 3) insns. */ if (!in_prologue && USE_REG_TB && tb_diff =3D=3D (int32_t)tb_diff) { tcg_out_mem_long(s, ADDI, ADD, ret, TCG_REG_TB, tb_diff); --=20 2.34.1 From nobody Wed Nov 27 17:32:24 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1697668045; cv=none; d=zohomail.com; s=zohoarc; b=Gx/f+n6jDeGMVGd7vT5gpVZ2kBZN7gMfwEShgjnMiwMQllLLkt5BgvU0aRqW24kL5RiQ+BjDo6+vkVgsD1rVAsI+jjiWOBamipjiX+kAcgdDgkT5g1Pjjuqbvlj5cC/v6GkKZsREJQy8HZq4zmCQowbXtwV4+32DiHpY2ZFZTO4= ARC-Message-Signature: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697668046272100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target.c.inc | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index 226b5598ac..720f92ff33 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -1081,6 +1081,12 @@ static void tcg_out_movi_int(TCGContext *s, TCGType = type, TCGReg ret, tcg_out32(s, LD | TAI(ret, TCG_REG_TB, 0)); return; } + if (have_isa_3_00) { + tcg_out_addpcis(s, TCG_REG_TMP2, 0); + new_pool_label(s, arg, R_PPC_REL14, s->code_ptr, 0); + tcg_out32(s, LD | TAI(ret, TCG_REG_TMP2, 0)); + return; + } =20 tmp =3D arg >> 31 >> 1; tcg_out_movi(s, TCG_TYPE_I32, ret, tmp); @@ -1138,6 +1144,10 @@ static void tcg_out_dupi_vec(TCGContext *s, TCGType = type, unsigned vece, if (USE_REG_TB) { rel =3D R_PPC_ADDR16; add =3D ppc_tbrel_diff(s, NULL); + } else if (have_isa_3_00) { + tcg_out_addpcis(s, TCG_REG_TMP1, 0); + rel =3D R_PPC_REL14; + add =3D 0; } else { rel =3D R_PPC_ADDR32; add =3D 0; @@ -1164,6 +1174,8 @@ static void tcg_out_dupi_vec(TCGContext *s, TCGType t= ype, unsigned vece, if (USE_REG_TB) { tcg_out32(s, ADDI | TAI(TCG_REG_TMP1, 0, 0)); load_insn |=3D RA(TCG_REG_TB); + } else if (have_isa_3_00) { + tcg_out32(s, ADDI | TAI(TCG_REG_TMP1, TCG_REG_TMP1, 0)); } else { tcg_out32(s, ADDIS | TAI(TCG_REG_TMP1, 0, 0)); tcg_out32(s, ADDI | TAI(TCG_REG_TMP1, TCG_REG_TMP1, 0)); --=20 2.34.1 From nobody Wed Nov 27 17:32:24 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697668142736100003 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target.c.inc | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index 720f92ff33..6337b1e8be 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -2593,6 +2593,7 @@ static void tcg_out_exit_tb(TCGContext *s, uintptr_t = arg) static void tcg_out_goto_tb(TCGContext *s, int which) { uintptr_t ptr =3D get_jmp_target_addr(s, which); + int16_t lo; =20 /* Direct branch will be patched by tb_target_set_jmp_target. */ set_jmp_insn_offset(s, which); @@ -2602,9 +2603,15 @@ static void tcg_out_goto_tb(TCGContext *s, int which) if (USE_REG_TB) { ptrdiff_t offset =3D ppc_tbrel_diff(s, (void *)ptr); tcg_out_mem_long(s, LD, LDX, TCG_REG_TMP1, TCG_REG_TB, offset); + } else if (have_isa_3_00) { + ptrdiff_t offset =3D tcg_pcrel_diff(s, (void *)ptr) - 4; + lo =3D offset; + tcg_out_addpcis(s, TCG_REG_TMP1, offset - lo); + tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, TCG_REG_TMP1, lo); } else { - tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP1, ptr - (int16_t)ptr); - tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, TCG_REG_TMP1, (int16_t)p= tr); + lo =3D ptr; + tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP1, ptr - lo); + tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, TCG_REG_TMP1, lo); } =20 tcg_out32(s, MTSPR | RS(TCG_REG_TMP1) | CTR); --=20 2.34.1 From nobody Wed Nov 27 17:32:24 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id 13-20020a170902c24d00b001b9d95945afsm431058plg.155.2023.10.18.15.26.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Oct 2023 15:26:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1697667965; x=1698272765; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=IcT+t2NWvvAgl7ag7U9fcr97JnnF4drB4JEVTRDmT40=; b=Br+uZt44LqQLFnY7sWum+dgFTNGGc3UtqeB++I2B9vI+GlrkvFT8v1Q0qEnAPuWRyR rRCBvsGScHkMOHIV7TLd3Q8sCubNFyvf2Z5cM/hYA3oqi+hJ93YdV6saw7C6CJmQNMCP ZVKh2neM2SxtiRDjioiDVZhzr562XMPPyYAYvkFRsz7V9K0R1YF1/ejzLndT0r6zjjzs fAi57s6ODorzrbV/5EXK7x2EvLEekS9uz3UfTw3lX3trPRXcA+1F9E97EKc57ME7Lv+V LcdtBUwf4EADDWjEW9W+SUGhZZYUFC6RSpo/CpnW+t/V0rY0kGg8EItQffC+ulEk3CbA 5BIw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697667965; x=1698272765; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=IcT+t2NWvvAgl7ag7U9fcr97JnnF4drB4JEVTRDmT40=; b=d5nDblBkRkC+NQq6wc+hkPvz0Q5U3otjOqkphWfOK7/9PwRfeolnzdwgWjFVk2rbTE HBsT80oQ6CVsWdpUAY78LLVgmwg+LaksrKwGD39CeGsAGgdRhGVkqvW3r4P34/NX0LTE 0RGun0BJw0E/fFnhox5OcRBk6haWmJXNOLHdpqPkrNT4A2aDwQFV/umYN3zRAC7iqWLF ahOW1sIwPjtLKc8wNEOvynSS3n8/INa5KarvEN5uoL2fsqKPl3d8EeFyFO+ugbFLZ9Nv /oDqr0NGLiJeiGyosiEp3dd/TH6/q9Ndtu4K09p+4fuVDw+KaP0f5cTaTmGyxvQOe7sB vz3g== X-Gm-Message-State: AOJu0Yzkdk0T15NIyPYX2dcGXCTd9w9KAmY8O/WZzVBc0bJ5o5zR6EEL Ad3UpEFvintlKtulktLXsfXR8vcLOrbPMW63MaY= X-Google-Smtp-Source: AGHT+IHv+gQklcvjv3kle42MOUSroOcJSFU+l3di9KoEkjqsjm9m2QrIOuwEZ542IVaqOH/iE1LYvw== X-Received: by 2002:a05:6a20:da93:b0:17b:2c56:70b8 with SMTP id iy19-20020a056a20da9300b0017b2c5670b8mr681861pzb.22.1697667965647; Wed, 18 Oct 2023 15:26:05 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Jordan Niethe Subject: [PULL 08/29] tcg/ppc: Use PADDI in tcg_out_movi Date: Wed, 18 Oct 2023 15:25:36 -0700 Message-Id: <20231018222557.1562065-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231018222557.1562065-1-richard.henderson@linaro.org> References: <20231018222557.1562065-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::529; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x529.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697668060316100001 Content-Type: text/plain; charset="utf-8" PADDI can load 34-bit immediates and 34-bit pc-relative addresses. Reviewed-by: Jordan Niethe Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target.c.inc | 51 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 51 insertions(+) diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index 6337b1e8be..f4235383c6 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -719,6 +719,38 @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int t= ype, return true; } =20 +/* Ensure that the prefixed instruction does not cross a 64-byte boundary.= */ +static bool tcg_out_need_prefix_align(TCGContext *s) +{ + return ((uintptr_t)s->code_ptr & 0x3f) =3D=3D 0x3c; +} + +static void tcg_out_prefix_align(TCGContext *s) +{ + if (tcg_out_need_prefix_align(s)) { + tcg_out32(s, NOP); + } +} + +static ptrdiff_t tcg_pcrel_diff_for_prefix(TCGContext *s, const void *targ= et) +{ + return tcg_pcrel_diff(s, target) - (tcg_out_need_prefix_align(s) ? 4 := 0); +} + +/* Output Type 10 Prefix - Modified Load/Store Form (MLS:D) */ +static void tcg_out_mls_d(TCGContext *s, tcg_insn_unit opc, unsigned rt, + unsigned ra, tcg_target_long imm, bool r) +{ + tcg_insn_unit p, i; + + p =3D OPCD(1) | (2 << 24) | (r << 20) | ((imm >> 16) & 0x3ffff); + i =3D opc | TAI(rt, ra, imm); + + tcg_out_prefix_align(s); + tcg_out32(s, p); + tcg_out32(s, i); +} + static void tcg_out_mem_long(TCGContext *s, int opi, int opx, TCGReg rt, TCGReg base, tcg_target_long offset); =20 @@ -1017,6 +1049,25 @@ static void tcg_out_movi_int(TCGContext *s, TCGType = type, TCGReg ret, return; } =20 + /* + * Load values up to 34 bits, and pc-relative addresses, + * with one prefixed insn. + */ + if (have_isa_3_10) { + if (arg =3D=3D sextract64(arg, 0, 34)) { + /* pli ret,value =3D paddi ret,0,value,0 */ + tcg_out_mls_d(s, ADDI, ret, 0, arg, 0); + return; + } + + tmp =3D tcg_pcrel_diff_for_prefix(s, (void *)arg); + if (tmp =3D=3D sextract64(tmp, 0, 34)) { + /* pla ret,value =3D paddi ret,0,value,1 */ + tcg_out_mls_d(s, ADDI, ret, 0, tmp, 1); + return; + } + } + /* Load 32-bit immediates with two insns. Note that we've already eliminated bare ADDIS, so we know both insns are required. */ if (TCG_TARGET_REG_BITS =3D=3D 32 || arg =3D=3D (int32_t)arg) { --=20 2.34.1 From nobody Wed Nov 27 17:32:24 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1697668027; cv=none; d=zohomail.com; s=zohoarc; b=UiZBASB/AoP57Kra4scTlZufEuBvdKkfrLY25oy4kBUjp3Hwlkj0GCbr9j59qst6fwcifD9qj2EzdMk8lH8IsaQftOAfKO827GeVkoAiEs30zzSctkfxHSYkTAQHZgB9XvmvLSZU3i2nc69rqd06fo7uCG8AZpq2Rig/etTfKD4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1697668027; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=CnIEHz3YbyZLNAezqFGknAR6TwEjyjNQhE5DMYmjFw8=; b=azN5j9qQaEIPE1nHkvzuO+o9mHaOx3X+KOotaxd2nXE0NHc/xbPlFku2WiuhZWSblo2hvOiFKVg5+tHiZE2uSUwzPMl105BIRdhaPUqdPsSIX+FiETu00AH6BfAgr7h6nVNsuNDutFHEW9ZwpmenrfIB9mlY5GIpiVeb/bTFpgY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1697668027072868.9018943468112; Wed, 18 Oct 2023 15:27:07 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qtEzS-000859-CR; Wed, 18 Oct 2023 18:26:10 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qtEzR-00084l-Dt for qemu-devel@nongnu.org; Wed, 18 Oct 2023 18:26:09 -0400 Received: from mail-pl1-x62e.google.com ([2607:f8b0:4864:20::62e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qtEzP-0002TQ-Lk for qemu-devel@nongnu.org; Wed, 18 Oct 2023 18:26:09 -0400 Received: by mail-pl1-x62e.google.com with SMTP id d9443c01a7336-1ca052ec63bso49635055ad.1 for ; Wed, 18 Oct 2023 15:26:07 -0700 (PDT) Received: from stoup.. ([71.212.149.95]) by smtp.gmail.com with ESMTPSA id 13-20020a170902c24d00b001b9d95945afsm431058plg.155.2023.10.18.15.26.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Oct 2023 15:26:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1697667966; x=1698272766; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=CnIEHz3YbyZLNAezqFGknAR6TwEjyjNQhE5DMYmjFw8=; b=vIBq9W7cZD5iC1NGLqLebyUUHmGu+Uy5wRZHtdWrvN1K40nlqM24vvUu8L9VE6bVzp seWU8afV95rnfMCBBqlcwTjK5KCQkYJJHRjTTx3l+VX6TsbmlQ1yKmwf0I22D4OJzY+8 wLzQtyT357C0b+tdlFpi3sEG/X0cBORjhSYeiXxrdTDP1GmLtHUfaT6ziBADbXOCdTq4 veEMq5MJqEz7VmFwsQW05sejJWGw6ETXii1vgk3m2XlCStlxcHnMkO+U5TOZWPLBJ0Ht IuSucmtYecKz31i8+c7R4Z9D0ipNkRkcm1QDvwerPXLeQIm8NEzwO2FaPmIfp9tROj7I k2Sw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697667966; x=1698272766; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=CnIEHz3YbyZLNAezqFGknAR6TwEjyjNQhE5DMYmjFw8=; b=ZTjf391o6ci8/YC9Q8K812EuLyE/6k2fCZAmHHUNmFP84Gw5bOELTaSI2swzlRfn8a hm0fgZiOHvk8iwZAYpHWgH35jCIWBdsyjxshYrqmwyX2bM/UBJfJTde+P4r5k3Yi9xNk IhpPsCHuOU7gzTKyFXPQYgNhF7OG5z06R1B4+NN56Bm4rtFtLhRztO7VnYUxxTG+yG+R nCOcejqwIQu6IfZqZ/XO7Yjj7e1x94ylJJxWyG6TTzOx8vii//GbY66GXs8uCDQVmXhY MSShxMlwLu4yS0mQZF4bA//5WSYN3FYPcTiAwB5ifo7GQRz8hUcNtMoK49NKZWvDk4hd X5XA== X-Gm-Message-State: AOJu0YxjiM5ZWwEXlFM9ol3DuGiEwuXN2HlfsrmwETOQinDmPhPhQHuu reEEMWjmyL79JatCUV45bKxV3QO6P7MIISuGP7U= X-Google-Smtp-Source: AGHT+IGu9t4bp0/BUinNp+w4lt/Omv9ZzfZe6h8yzWg7c30oIWpsgWdo9c0R+CaRZsV3dtedJr+tOQ== X-Received: by 2002:a17:903:41c8:b0:1ca:3fa6:4aef with SMTP id u8-20020a17090341c800b001ca3fa64aefmr778713ple.66.1697667966461; Wed, 18 Oct 2023 15:26:06 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Jordan Niethe Subject: [PULL 09/29] tcg/ppc: Use prefixed instructions in tcg_out_mem_long Date: Wed, 18 Oct 2023 15:25:37 -0700 Message-Id: <20231018222557.1562065-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231018222557.1562065-1-richard.henderson@linaro.org> References: <20231018222557.1562065-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697668028221100001 Content-Type: text/plain; charset="utf-8" When the offset is out of range of the non-prefixed insn, but fits the 34-bit immediate of the prefixed insn, use that. Reviewed-by: Jordan Niethe Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target.c.inc | 66 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 66 insertions(+) diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index f4235383c6..34df9144cc 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -329,6 +329,15 @@ static bool tcg_target_const_match(int64_t val, TCGTyp= e type, int ct, int vece) #define STDX XO31(149) #define STQ XO62( 2) =20 +#define PLWA OPCD( 41) +#define PLD OPCD( 57) +#define PLXSD OPCD( 42) +#define PLXV OPCD(25 * 2 + 1) /* force tx=3D1 */ + +#define PSTD OPCD( 61) +#define PSTXSD OPCD( 46) +#define PSTXV OPCD(27 * 2 + 1) /* force sx=3D1 */ + #define ADDIC OPCD( 12) #define ADDI OPCD( 14) #define ADDIS OPCD( 15) @@ -737,6 +746,20 @@ static ptrdiff_t tcg_pcrel_diff_for_prefix(TCGContext = *s, const void *target) return tcg_pcrel_diff(s, target) - (tcg_out_need_prefix_align(s) ? 4 := 0); } =20 +/* Output Type 00 Prefix - 8-Byte Load/Store Form (8LS:D) */ +static void tcg_out_8ls_d(TCGContext *s, tcg_insn_unit opc, unsigned rt, + unsigned ra, tcg_target_long imm, bool r) +{ + tcg_insn_unit p, i; + + p =3D OPCD(1) | (r << 20) | ((imm >> 16) & 0x3ffff); + i =3D opc | TAI(rt, ra, imm); + + tcg_out_prefix_align(s); + tcg_out32(s, p); + tcg_out32(s, i); +} + /* Output Type 10 Prefix - Modified Load/Store Form (MLS:D) */ static void tcg_out_mls_d(TCGContext *s, tcg_insn_unit opc, unsigned rt, unsigned ra, tcg_target_long imm, bool r) @@ -1418,6 +1441,49 @@ static void tcg_out_mem_long(TCGContext *s, int opi,= int opx, TCGReg rt, break; } =20 + /* For unaligned or large offsets, use the prefixed form. */ + if (have_isa_3_10 + && (offset !=3D (int16_t)offset || (offset & align)) + && offset =3D=3D sextract64(offset, 0, 34)) { + /* + * Note that the MLS:D insns retain their un-prefixed opcode, + * while the 8LS:D insns use a different opcode space. + */ + switch (opi) { + case LBZ: + case LHZ: + case LHA: + case LWZ: + case STB: + case STH: + case STW: + case ADDI: + tcg_out_mls_d(s, opi, rt, base, offset, 0); + return; + case LWA: + tcg_out_8ls_d(s, PLWA, rt, base, offset, 0); + return; + case LD: + tcg_out_8ls_d(s, PLD, rt, base, offset, 0); + return; + case STD: + tcg_out_8ls_d(s, PSTD, rt, base, offset, 0); + return; + case LXSD: + tcg_out_8ls_d(s, PLXSD, rt & 31, base, offset, 0); + return; + case STXSD: + tcg_out_8ls_d(s, PSTXSD, rt & 31, base, offset, 0); + return; + case LXV: + tcg_out_8ls_d(s, PLXV, rt & 31, base, offset, 0); + return; + case STXV: + tcg_out_8ls_d(s, PSTXV, rt & 31, base, offset, 0); + return; + } + } + /* For unaligned, or very large offsets, use the indexed form. */ if (offset & align || offset !=3D (int32_t)offset || opi =3D=3D 0) { if (rs =3D=3D base) { --=20 2.34.1 From nobody Wed Nov 27 17:32:24 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1697668005; cv=none; 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id 13-20020a170902c24d00b001b9d95945afsm431058plg.155.2023.10.18.15.26.06 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Oct 2023 15:26:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1697667967; x=1698272767; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=4gXGK6fIVAMAIDlPSRafHxXOFGChnJBeeF+QM2JUpio=; b=kklKVsv4uP8wBr4z+PD5akacKFx/MT+hn1t/CKeHDEHb38ljpTPYYpzU84IWxjoguT tB9Z+VXTuswLvKZU8av/EFmFu/VojmDIsyD+mGUWQ0uQoMC4wRgIbm1ay0tTi7bJOXN4 sMDqnHPCB2oT+DXYoNnC4rIiA8ANytwB0IRkhwcgCPkrJ79SYCNyDmVOc/1xeqp6dzR5 gIOTfa7f1z0/BwfzI0upqAnsGIqwl39NC2z6xDOoexMIhv25ANVqHHF8bwAXBET7CpiM EDPiXTWhLkU3gavwqaFU9QUlCylZKaehwcncX43cMiMZuztxGUBJz5A64Sip+vsn+Nqo 2xfw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697667967; x=1698272767; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=4gXGK6fIVAMAIDlPSRafHxXOFGChnJBeeF+QM2JUpio=; b=ml2vPUwv6BMD88C5WYJNKsukgPk0mSaNDfvyR+klZpKtsOQWBgyuPe7j/3hy7NB0ei /AdfwpH0q44IPz7+60Gv5LnNo29qZTvdPi6D/EHMsfJR5YpUCzQh7/tBZNxpeLukMXVL BsfqRdtJbaemrCP7JnZkPyLILggK9Gab3SCxog8VjK2RbC+9gB0yf9Ur0sET59D6OtRv KLD//7ESk2vz+Dpx21KW6loxiJ3F8QWi364vy5IgyFx4ZU3HCmBuRfbYuux1ulTZZvdA UQWVhfMYAPixJavsWrVDtdo1nt058OqNmdQJcGwU6ln1NhraIpAb+1JztkasL5aws6oY vz2g== X-Gm-Message-State: AOJu0YzQmEjbYV9pviIsSoIUWRtXlaU/7xw0LDCP3pYVb+Vpc8uA8M0F ju5Nxt5Ic4rAVVbT1L5rkq76M4kjKOdFpn4nZnM= X-Google-Smtp-Source: AGHT+IEVxGCGkaNSvdTF93J9ycVR8Mhr6XN2kynjXmoWekUb/hpeLveE1swEKzk0IY0kNYRiL1kWeQ== X-Received: by 2002:a17:902:f9c3:b0:1c6:30d1:7214 with SMTP id kz3-20020a170902f9c300b001c630d17214mr641119plb.55.1697667967188; Wed, 18 Oct 2023 15:26:07 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 10/29] tcg/ppc: Use PLD in tcg_out_movi for constant pool Date: Wed, 18 Oct 2023 15:25:38 -0700 Message-Id: <20231018222557.1562065-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231018222557.1562065-1-richard.henderson@linaro.org> References: <20231018222557.1562065-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697668006451100006 Content-Type: text/plain; charset="utf-8" The prefixed instruction has a pc-relative form to use here. Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target.c.inc | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index 34df9144cc..79e82d2f94 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -101,6 +101,10 @@ #define ALL_GENERAL_REGS 0xffffffffu #define ALL_VECTOR_REGS 0xffffffff00000000ull =20 +#ifndef R_PPC64_PCREL34 +#define R_PPC64_PCREL34 132 +#endif + #define have_isel (cpuinfo & CPUINFO_ISEL) =20 #ifndef CONFIG_SOFTMMU @@ -266,6 +270,19 @@ static bool reloc_pc14(tcg_insn_unit *src_rw, const tc= g_insn_unit *target) return false; } =20 +static bool reloc_pc34(tcg_insn_unit *src_rw, const tcg_insn_unit *target) +{ + const tcg_insn_unit *src_rx =3D tcg_splitwx_to_rx(src_rw); + ptrdiff_t disp =3D tcg_ptr_byte_diff(target, src_rx); + + if (disp =3D=3D sextract64(disp, 0, 34)) { + src_rw[0] =3D (src_rw[0] & ~0x3ffff) | ((disp >> 16) & 0x3ffff); + src_rw[1] =3D (src_rw[1] & ~0xffff) | (disp & 0xffff); + return true; + } + return false; +} + /* test if a constant matches the constraint */ static bool tcg_target_const_match(int64_t val, TCGType type, int ct, int = vece) { @@ -696,6 +713,8 @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int ty= pe, return reloc_pc14(code_ptr, target); case R_PPC_REL24: return reloc_pc24(code_ptr, target); + case R_PPC64_PCREL34: + return reloc_pc34(code_ptr, target); case R_PPC_ADDR16: /* * We are (slightly) abusing this relocation type. In particular, @@ -1155,6 +1174,11 @@ static void tcg_out_movi_int(TCGContext *s, TCGType = type, TCGReg ret, tcg_out32(s, LD | TAI(ret, TCG_REG_TB, 0)); return; } + if (have_isa_3_10) { + tcg_out_8ls_d(s, PLD, ret, 0, 0, 1); + new_pool_label(s, arg, R_PPC64_PCREL34, s->code_ptr - 2, 0); + return; + } if (have_isa_3_00) { tcg_out_addpcis(s, TCG_REG_TMP2, 0); new_pool_label(s, arg, R_PPC_REL14, s->code_ptr, 0); --=20 2.34.1 From nobody Wed Nov 27 17:32:24 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1697668122; cv=none; d=zohomail.com; s=zohoarc; b=XxhIsscFmmLjZXjnrLKpdfWgGQhpVDuLmWyMCB4LeMZZJc3kolDaSVVFPU9fkEoN0l0c+06ZFCIqfpxJ0pZGVn9k++lkYJodryMziBSBOZPTERuzx2SdLffAkXLwTFOeuQN+IRZQj75wLMVTPasoRf7+R8QNp6rl4EAJa7kKMsk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1697668122; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=eJDwvSu5y6aQI1FUpLq82z/uiGp428KQX4VVdh13eIw=; b=OpsjN5fyXesu1i8ACq+zlGNjze0UTK/z7AWY1Dh4iwXvhXCerM2OnPcjGNn3yR+Bu+PM8vgcLoduGiNWFuPuvFlo2NQTFr3UI3HCGht00gbPrfO6Q/qqbo6jK3OMiJRDeVGxMT652pK5h2GD6lfW7nzDMINLSfiNqRYnesduIM8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1697668122785456.85669522774515; Wed, 18 Oct 2023 15:28:42 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qtEzY-00087N-6f; Wed, 18 Oct 2023 18:26:16 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qtEzU-00086f-Qq for qemu-devel@nongnu.org; Wed, 18 Oct 2023 18:26:12 -0400 Received: from mail-pl1-x62b.google.com ([2607:f8b0:4864:20::62b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qtEzS-0002U5-TB for qemu-devel@nongnu.org; Wed, 18 Oct 2023 18:26:12 -0400 Received: by mail-pl1-x62b.google.com with SMTP id d9443c01a7336-1c8a1541232so63879555ad.0 for ; Wed, 18 Oct 2023 15:26:10 -0700 (PDT) Received: from stoup.. ([71.212.149.95]) by smtp.gmail.com with ESMTPSA id 13-20020a170902c24d00b001b9d95945afsm431058plg.155.2023.10.18.15.26.07 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Oct 2023 15:26:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1697667969; x=1698272769; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=eJDwvSu5y6aQI1FUpLq82z/uiGp428KQX4VVdh13eIw=; b=kgyhGm4yR/esohGdJ5PzSpqwAYS2rdE+5onU0lW7VqOJr5BF0HOcd3z4giSDI6tBhB /IXjnyb4GodbRA2FF+AzuN2wBhC9RFOdbroFNJDZyrO6x4514iaMfloWSQKfXjzSvJbA 3Hb9NuTqjvLzPfuz6K8oM4LETIX7hnV0kelR/KIhrGWpdor5ev+WW9r8G4EQA5pfVHIQ BemIzneZwRgTeP1jjik3nmP/0gVVGvz0EtxAZ3uLg3kMDTDJemYVPlB6pAWkfQ2ieKkR qG0ZaYmPKWXxL1LKqYhDB2PqyiPTP4rcpPpleNPSlojqqN9MaM9S4/A3F2ZLRYbegB6Y CfTA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697667969; x=1698272769; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=eJDwvSu5y6aQI1FUpLq82z/uiGp428KQX4VVdh13eIw=; b=GTVKJZKwV8MZoiclyEdSa3qbatWF/FQfsBu7gzoxTSl9nhDRvv023zWlxlQ5Gd4XmQ WfOq+TqmCn1ym0wxDlakZ1WiM0XSjJD88hJN5U8sfnzxSSf4vJOq9ZGmASg51XzSk52m O3qb9PySVgS5XCF0Yig3XhOxZWnQTDBpfpoNG2h43WrUKlm0a1aoPHqZiNeMpoPlE4qc Y1fAE22VSEsDPOP/ZSHi3HDvkzdVSbdxGlug8ITyF5b/Oy09HRHP4fFb5TcL3QSZIrYi aorhi7zJDqQbL4UP15nqSGVwYukcuK7P+G+kG5ch3vZbfb3mDlpqsBYZmS54XRXAGl98 0Bbg== X-Gm-Message-State: AOJu0YxzwS8egClxiriIKIm0LCjVoRmSP6zYYXPDEXRBUN/Fliiyn/zo 54VQ6YvVskqJHmCuMevpbIliO6HqAqrX1w3B24Q= X-Google-Smtp-Source: AGHT+IHSpv9GYsNDXFHGqDsIcMfrqd45VsCgJhpzDLeKzosiWkdGFp8fnPgSuiZfc7L67g1YBy5g3w== X-Received: by 2002:a17:902:f682:b0:1bd:aeb3:9504 with SMTP id l2-20020a170902f68200b001bdaeb39504mr780901plg.15.1697667969689; Wed, 18 Oct 2023 15:26:09 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 11/29] tcg/ppc: Use prefixed instructions in tcg_out_dupi_vec Date: Wed, 18 Oct 2023 15:25:39 -0700 Message-Id: <20231018222557.1562065-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231018222557.1562065-1-richard.henderson@linaro.org> References: <20231018222557.1562065-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697668124552100007 Content-Type: text/plain; charset="utf-8" The prefixed instructions have a pc-relative form to use here. Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target.c.inc | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index 79e82d2f94..db3212083b 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -1242,6 +1242,15 @@ static void tcg_out_dupi_vec(TCGContext *s, TCGType = type, unsigned vece, if (USE_REG_TB) { rel =3D R_PPC_ADDR16; add =3D ppc_tbrel_diff(s, NULL); + } else if (have_isa_3_10) { + if (type =3D=3D TCG_TYPE_V64) { + tcg_out_8ls_d(s, PLXSD, ret & 31, 0, 0, 1); + new_pool_label(s, val, R_PPC64_PCREL34, s->code_ptr - 2, 0); + } else { + tcg_out_8ls_d(s, PLXV, ret & 31, 0, 0, 1); + new_pool_l2(s, R_PPC64_PCREL34, s->code_ptr - 2, 0, val, val); + } + return; } else if (have_isa_3_00) { tcg_out_addpcis(s, TCG_REG_TMP1, 0); rel =3D R_PPC_REL14; --=20 2.34.1 From nobody Wed Nov 27 17:32:24 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1697668135; cv=none; d=zohomail.com; s=zohoarc; b=Z7yQE2R/PFrD4OzpKvT/3AYYk+Va5dUwkpTUUyifEe2nv0LFxEp1ccCUar7LHjeeBz3Csu8Cw7KueUYltAvBTltInyVnGjLmz6ckQ4F2lJxn3adqUMbcey2lHKnrNGNYkQTyHieyQDW5LX/PG2VhURHTmTMI9L72OTE40qDA8a4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1697668135; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=6Sq2XuaUgq1WVJLtCb9vCiBQv+e4IAv+CN8pWqHj0rc=; b=F0exHEV4s8tHujj1KnicCXSa7jMxs2oeM/ntJksp/IhviRdBLWHvhADH9Riw973F4qwH5Vjs8q0kkPDOh5SDL1gRPu0ojinAtr0UOnZoNM2GzSxiQ7dVJG1xBseTTcYs+BYt8t07tZp9Uvl0jfDYhScGif2KozQjcs1jQw1hu/U= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 16976681358601021.3465222724907; Wed, 18 Oct 2023 15:28:55 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qtEzX-00087E-OK; Wed, 18 Oct 2023 18:26:15 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qtEzV-00086p-79 for qemu-devel@nongnu.org; Wed, 18 Oct 2023 18:26:13 -0400 Received: from mail-pl1-x636.google.com ([2607:f8b0:4864:20::636]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qtEzT-0002UC-Fd for qemu-devel@nongnu.org; Wed, 18 Oct 2023 18:26:12 -0400 Received: by mail-pl1-x636.google.com with SMTP id d9443c01a7336-1ca6809fb8aso27744435ad.1 for ; Wed, 18 Oct 2023 15:26:11 -0700 (PDT) Received: from stoup.. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697668136740100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target.c.inc | 3 +++ 1 file changed, 3 insertions(+) diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index db3212083b..6496f76e41 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -2753,6 +2753,9 @@ static void tcg_out_goto_tb(TCGContext *s, int which) if (USE_REG_TB) { ptrdiff_t offset =3D ppc_tbrel_diff(s, (void *)ptr); tcg_out_mem_long(s, LD, LDX, TCG_REG_TMP1, TCG_REG_TB, offset); + } else if (have_isa_3_10) { + ptrdiff_t offset =3D tcg_pcrel_diff_for_prefix(s, (void *)ptr); + tcg_out_8ls_d(s, PLD, TCG_REG_TMP1, 0, offset, 1); } else if (have_isa_3_00) { ptrdiff_t offset =3D tcg_pcrel_diff(s, (void *)ptr) - 4; lo =3D offset; --=20 2.34.1 From nobody Wed Nov 27 17:32:24 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1697668304; cv=none; d=zohomail.com; s=zohoarc; b=SHTil3Kf92+CoioD78Gu5q6Y+WvQrkOH/6IqybcDx0ZiNp+5gLhxLYrf4+H2YnXaU+vR4Fp1QwRV03RayES8g3XA+AdJj4UDoC0fj3iYPsMQTSr4lgAijR0rGEZzTxhC6D/yWe/dTojyqpDI7QcPIgV+jrMZoTCmTafMkOdQ86M= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1697668304; 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id 13-20020a170902c24d00b001b9d95945afsm431058plg.155.2023.10.18.15.26.10 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Oct 2023 15:26:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1697667971; x=1698272771; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=wgo3sS5iUyrU0Dzdzk24htDnmRxHdeX5tUMGq3kg/oc=; b=AeAfFAVkwVfW1Q+ML+uYwP8ihCTBnWK18BBtrz9dLDl0N3H37IMaG2uSdZxvrqSh0Q h0XO1UkBzbtNFkHSMgMVO+qFQJYCc+lBYg7iiic6PwZtCtoZrhzFGLynOpu3tzOPpo90 6KYAT0dbSBEsmFnWKn30dmSlPdoj4xEmLISymNR3RzO835C8PTMXRZlaV0vzPUvmZzn9 9w3Zgp1InZbXBfmX12FtoC45sb2lV37wuVvoNRXYG+hYI8sS/6Zw4Vtum2lPG37hjben +H9Gszuo0FSfNXyYmX65qidckjgNroO8zJnF/IVdYBVTlVJcYslhyDonpNpbWgcRszzT gkgw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697667971; x=1698272771; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=wgo3sS5iUyrU0Dzdzk24htDnmRxHdeX5tUMGq3kg/oc=; b=Q7EX8uWb8mlUe+UNPV5ldN0EnHsOZ6hbqeYY+9OjvbweW3YG5I0kf5WxRKPbbakD/v k1SuJ+s44bFuemFwWfRA1w6dky5BX1dANYM81X99Xy1DArPFrdeErmpS4nA9LdJWgC1n k9BrCENhh2ww/qWYZ55jRGfxYe0M9oSrqsXT0ml/K85RE9QN2t9SNcqkHuHimIe6Qgcz eRHIcKjDDeSrtdlR3no/m6gAnGBXhhW+w5FuOeM//tJm9Zo6HoQ3yr1rJjDiSsYn5nex gYVM1Kd17yF/oDUDohGGEK5CYvUQei3nw5XBcOIOn4hsKQrdFOkSb589vdewaZELvLld 7ZHA== X-Gm-Message-State: AOJu0YzLOIfePHSTTdUiPlK75W8vUqQyDRxM5s+gQWGw25gUy830SCcP 9gIqaYlMj8tRJZcfQU6nYP556UPXzUjC+DI7UAI= X-Google-Smtp-Source: AGHT+IFD0M/517RpMnOx4hNnCQEmBWKCi1Y8OfoumoQoCPSluTw997LU/goPCyh9OfAFtzi/W+sQtA== X-Received: by 2002:a17:902:da8d:b0:1c7:495c:87df with SMTP id j13-20020a170902da8d00b001c7495c87dfmr885184plx.53.1697667971044; Wed, 18 Oct 2023 15:26:11 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 13/29] tcg/ppc: Disable TCG_REG_TB for Power9/Power10 Date: Wed, 18 Oct 2023 15:25:41 -0700 Message-Id: <20231018222557.1562065-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231018222557.1562065-1-richard.henderson@linaro.org> References: <20231018222557.1562065-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697668305511100001 Content-Type: text/plain; charset="utf-8" This appears to slightly improve performance on power9/10. Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target.c.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index 6496f76e41..c31da4da9d 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -83,7 +83,7 @@ #define TCG_VEC_TMP2 TCG_REG_V1 =20 #define TCG_REG_TB TCG_REG_R31 -#define USE_REG_TB (TCG_TARGET_REG_BITS =3D=3D 64) +#define USE_REG_TB (TCG_TARGET_REG_BITS =3D=3D 64 && !have_isa_3_00) =20 /* Shorthand for size of a pointer. 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id 13-20020a170902c24d00b001b9d95945afsm431058plg.155.2023.10.18.15.26.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Oct 2023 15:26:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1697667972; x=1698272772; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=VXDCPRqwkNHEWZB52f+OeRGLQD3oaL6U6LhW5ET5dXA=; b=M3GSem2w/jPkHgHeXslOAw/uV/t332ckk0u6RkvnzcAHkfDicR6buABOIzOkQvTw6t imVmXkNy/uc6dib2tz6AKBtv3A1Dxprm52JVo/wvH8abEBbyOXqMhaj9ZJfElqTEK+ny O+Dt72ra6ewr44hT4iX5oyac8lugeHSs6S/eIwiqIuf1NtMsI+yKbo1qUaxC+TBDDYCz W8Doz17BhC2jVEMc2nW0OswLxQwooo3O5tA6BkwRYjKas1ntDe/+3tFTTYKHBwXUIM5T 3UO1oc+HUc+7mxpmPypaHnj7gmMssAzlOwtvDGolzOOR54Q3kDhMQ7MXp0EpPnH3KJkd NfVQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697667972; x=1698272772; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=VXDCPRqwkNHEWZB52f+OeRGLQD3oaL6U6LhW5ET5dXA=; b=k0gOznO91h6ypqP/C56Ipwo0Q66NltWgqnFmm6WKb0/oWfqSNyEPD0nF0ZeogbPceq SynYgSpyEnqeeG+LoOoPVmSuomcSgKxS/KSMKsSC+kvhRwnD2NVJamOfuZuUxfhRePms DGQDfNKm1VuWQI4tb0Hu9tkuIBqH4dQPO43HsuUZZIVJPrqeO5RTSkPN/WJGGO9cCq6K XjziZYM4hb+1so2f8Ev5e+L1+UmqMtwhQq0JHBeK3n93CbgsMlsF8xeP7cijB1GhxWZ9 hI7U6Rl09M5+B1mxSYubsbSnF7n6gkxsTf6IV4QgMU/usw8RlHduR2RqbsvZ059KA04B N9Fw== X-Gm-Message-State: AOJu0Yz/IdqshwqPamrW2IT6libA3nfm3JzgbLKEvkP/NorFgtkb95Rv Takw74slEXvihuV81zOSdvMcqrgerWgMJY6IvlA= X-Google-Smtp-Source: AGHT+IEWfV4MeprmbUxeCCh7hkWuzXBYT4sngQLMEpmEGyXax6y19rRTYdqhgJZOYzNdVH+hNWUG0A== X-Received: by 2002:a05:6a20:549b:b0:179:f81b:12d9 with SMTP id i27-20020a056a20549b00b00179f81b12d9mr595284pzk.11.1697667971861; Wed, 18 Oct 2023 15:26:11 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 14/29] tcg: Introduce tcg_use_softmmu Date: Wed, 18 Oct 2023 15:25:42 -0700 Message-Id: <20231018222557.1562065-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231018222557.1562065-1-richard.henderson@linaro.org> References: <20231018222557.1562065-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42c; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697668110512100001 Begin disconnecting CONFIG_SOFTMMU from !CONFIG_USER_ONLY. Introduce a variable which can be set at startup to select one method or another for user-only. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- include/tcg/tcg.h | 8 ++++++-- tcg/tcg-op-ldst.c | 14 +++++++------- tcg/tcg.c | 9 ++++++--- 3 files changed, 19 insertions(+), 12 deletions(-) diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index 680ff00722..a9282cdcc6 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -488,11 +488,9 @@ struct TCGContext { int nb_ops; TCGType addr_type; /* TCG_TYPE_I32 or TCG_TYPE_I64 */ =20 -#ifdef CONFIG_SOFTMMU int page_mask; uint8_t page_bits; uint8_t tlb_dyn_max_bits; -#endif uint8_t insn_start_words; TCGBar guest_mo; =20 @@ -573,6 +571,12 @@ static inline bool temp_readonly(TCGTemp *ts) return ts->kind >=3D TEMP_FIXED; } =20 +#ifdef CONFIG_USER_ONLY +extern bool tcg_use_softmmu; +#else +#define tcg_use_softmmu true +#endif + extern __thread TCGContext *tcg_ctx; extern const void *tcg_code_gen_epilogue; extern uintptr_t tcg_splitwx_diff; diff --git a/tcg/tcg-op-ldst.c b/tcg/tcg-op-ldst.c index df4f22c427..2b96687699 100644 --- a/tcg/tcg-op-ldst.c +++ b/tcg/tcg-op-ldst.c @@ -34,13 +34,13 @@ =20 static void check_max_alignment(unsigned a_bits) { -#if defined(CONFIG_SOFTMMU) /* * The requested alignment cannot overlap the TLB flags. * FIXME: Must keep the count up-to-date with "exec/cpu-all.h". */ - tcg_debug_assert(a_bits + 5 <=3D tcg_ctx->page_bits); -#endif + if (tcg_use_softmmu) { + tcg_debug_assert(a_bits + 5 <=3D tcg_ctx->page_bits); + } } =20 static MemOp tcg_canonicalize_memop(MemOp op, bool is64, bool st) @@ -411,10 +411,11 @@ void tcg_gen_qemu_st_i64_chk(TCGv_i64 val, TCGTemp *a= ddr, TCGArg idx, */ static bool use_two_i64_for_i128(MemOp mop) { -#ifdef CONFIG_SOFTMMU /* Two softmmu tlb lookups is larger than one function call. */ - return false; -#else + if (tcg_use_softmmu) { + return false; + } + /* * For user-only, two 64-bit operations may well be smaller than a cal= l. * Determine if that would be legal for the requested atomicity. @@ -432,7 +433,6 @@ static bool use_two_i64_for_i128(MemOp mop) default: g_assert_not_reached(); } -#endif } =20 static void canonicalize_memop_i128_as_i64(MemOp ret[2], MemOp orig) diff --git a/tcg/tcg.c b/tcg/tcg.c index 637b9e6870..d3a4a17ef2 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -226,6 +226,10 @@ static TCGAtomAlign atom_and_align_for_opc(TCGContext = *s, MemOp opc, MemOp host_atom, bool allow_two= _ops) __attribute__((unused)); =20 +#ifdef CONFIG_USER_ONLY +bool tcg_use_softmmu; +#endif + TCGContext tcg_init_ctx; __thread TCGContext *tcg_ctx; =20 @@ -404,13 +408,12 @@ static uintptr_t G_GNUC_UNUSED get_jmp_target_addr(TC= GContext *s, int which) return (uintptr_t)tcg_splitwx_to_rx(&s->gen_tb->jmp_target_addr[which]= ); } =20 -#if defined(CONFIG_SOFTMMU) && !defined(CONFIG_TCG_INTERPRETER) -static int tlb_mask_table_ofs(TCGContext *s, int which) +static int __attribute__((unused)) +tlb_mask_table_ofs(TCGContext *s, int which) { return (offsetof(CPUNegativeOffsetState, tlb.f[which]) - sizeof(CPUNegativeOffsetState)); } -#endif =20 /* Signal overflow, starting over with fewer guest insns. */ static G_NORETURN --=20 2.34.1 From nobody Wed Nov 27 17:32:24 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id 13-20020a170902c24d00b001b9d95945afsm431058plg.155.2023.10.18.15.26.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Oct 2023 15:26:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1697667972; x=1698272772; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=YGlbtLg90LV1uY25eQEYhNteHi+RQnuiWgmb0RTVS6Y=; b=GexO8dz2NDh1NJv+wHDqTyyoLZtCtou9JYjSENpKgfr0HOANba2P6T3g9I4JPzWknX xVqQQzSs/YiqEdWBa8wWeSt97XuPkvWi53vKVzzZ3sVXlwtKrqhHOpTn8RDeUPrXgoL+ SjrHNEivfquiUqACqjZ9VvX3e7CX0ujml6CKsvzMkEKMobVR9KgzZDNN7h5opLyG3saE Dkp7TpFsI2ZDjgvTZtTQatrQW8qjgz5d3kHnmfwDE0xeM6xJW1pAcqRv/2n2nQQXAxUq 1XaUPjoG9BNGLWCdTZPrBRkKRZiWmhTi5cmCCAfnEZqHiAtgcJPweVzg5ewLK4T5FRXg fdDg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697667972; x=1698272772; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=YGlbtLg90LV1uY25eQEYhNteHi+RQnuiWgmb0RTVS6Y=; b=S40q64ooLaOKiHecFSTZ94gEGWiChr8dVSdVF6ik2KjVNVLYJHCdrSSXNejf7pRzhd vRsrlcRMH3srzOz4WSUCEzA3RDSadLguAwUOHKayAEzFmSlKgwm2lscPKM/bkh3VjdkB QBoW5j2RyMRMhUgbq+v15hShtNJlxemuBxv+y4UsNaDsBEFNyjrOGgcK6bxlfWA1HmU5 xcsyWDiFcYHyq57moUpSiGeYq4ma6FjMWOMUqI7R3Pu47mZdkt7uah+bFxwe/8aGvd9W 5DBIfsExfoNm7gcAFN/S51I8k9t0vGtaTN+ZFUyntzV7SIB8ZQ9pRHs4wfW5JBZMxm+M 6FrA== X-Gm-Message-State: AOJu0YwU+1k9KGjybQ57X4roK0zVhaIwQGuoJd6XHf8NBOkLrtgbIr18 FR+52ZqQEjILziTaB0bGG/WThYchy18nY5ww408= X-Google-Smtp-Source: AGHT+IF1C5bw6qmHlZa7boSd2ny2Yyuu0fdwpO6bD/x2DXRIGq7fzQZDJ7mn0aXFHzoNLr12ModcSw== X-Received: by 2002:a17:902:d2cd:b0:1ca:87a1:cdf1 with SMTP id n13-20020a170902d2cd00b001ca87a1cdf1mr784920plc.27.1697667972614; Wed, 18 Oct 2023 15:26:12 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 15/29] tcg: Provide guest_base fallback for system mode Date: Wed, 18 Oct 2023 15:25:43 -0700 Message-Id: <20231018222557.1562065-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231018222557.1562065-1-richard.henderson@linaro.org> References: <20231018222557.1562065-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697668094460100001 Provide a define to allow !tcg_use_softmmu code paths to compile in system mode, but require elimination. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- tcg/tcg.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/tcg/tcg.c b/tcg/tcg.c index d3a4a17ef2..35158a0846 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -178,6 +178,10 @@ static bool tcg_target_const_match(int64_t val, TCGTyp= e type, int ct, int vece); static int tcg_out_ldst_finalize(TCGContext *s); #endif =20 +#ifndef CONFIG_USER_ONLY +#define guest_base ({ qemu_build_not_reached(); (uintptr_t)0; }) +#endif + typedef struct TCGLdstHelperParam { TCGReg (*ra_gen)(TCGContext *s, const TCGLabelQemuLdst *l, int arg_reg= ); unsigned ntmp; --=20 2.34.1 From nobody Wed Nov 27 17:32:24 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1697668125; cv=none; d=zohomail.com; s=zohoarc; b=CgtitUiC+adC9U3nIncSKgnsNu7TQxdF9Zdm38tDfX9gRZJThEJZU0a9GvAftzyQBo+poQ2aKR0WJh5GBry0XdcNjgw/sa3zs8+kNAAH+K6EyG4K6nyLh0uiIYEKp34TpQ7xZOUHowj7A0/LnecIhHo/BBJo7BrOG9pQ/hn4kx0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1697668125; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=Z5Y3YpkqSuB++PQnHqXwQCPjLyzdqqH8F+jPD48ZrG4=; b=ITIAmb56cwURCPy0xNWT+CIyd7uIlD9E7fnQL2ZZMln4sneG3oiMTw2MOFUHiSn+wijy+KiSFDQil/Bp15Yk0k0j2hex4LdqLRl3Z4DfEfhlNJVpT5a8kYEPq480FIkpVOTfcFLqJAsNM+TLkOn+iLRjjOu8nhc7RxPPR5Eiwb0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1697668125772172.48031786289914; Wed, 18 Oct 2023 15:28:45 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qtEzg-0008AU-B7; Wed, 18 Oct 2023 18:26:24 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qtEzZ-00087j-Nd for qemu-devel@nongnu.org; Wed, 18 Oct 2023 18:26:18 -0400 Received: from mail-pl1-x62f.google.com ([2607:f8b0:4864:20::62f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qtEzX-0002V0-BC for qemu-devel@nongnu.org; Wed, 18 Oct 2023 18:26:17 -0400 Received: by mail-pl1-x62f.google.com with SMTP id d9443c01a7336-1c434c33ec0so50460475ad.3 for ; Wed, 18 Oct 2023 15:26:14 -0700 (PDT) Received: from stoup.. ([71.212.149.95]) by smtp.gmail.com with ESMTPSA id 13-20020a170902c24d00b001b9d95945afsm431058plg.155.2023.10.18.15.26.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Oct 2023 15:26:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1697667974; x=1698272774; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Z5Y3YpkqSuB++PQnHqXwQCPjLyzdqqH8F+jPD48ZrG4=; b=wqF0en/woeOixtX6adb2e1lwXVduThJBOBJBlWw/yc9XRBr0CfVYs0Wl1RLxxR3tZp CJY33G/Qo3oSA0gP6iu4/4OX8N9mqae2RDcJE565aydjahi5PwqMrC2vvvMd9Sqe7cBJ VxFZfyoQh/UVESexdbTO96RKTrhA3Gt3nObySiCehwUkcwK18NvwTnt4bvqMxIXQY3wK 9Mr4hdmDK4V8QQtkkfRi1aKXwAlo+ZYR2sBCzcybrBnKWWEhM0331jQ1G9t7OJDPrdi9 TKTEaCrts7E6QOhYMtCz+drnfke+kbxUsfIZK414Bx+SWy06F1Wn5vPnE7XiBJcZixJS MB9g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697667974; x=1698272774; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Z5Y3YpkqSuB++PQnHqXwQCPjLyzdqqH8F+jPD48ZrG4=; b=HC15E8fv7OVBdMWooQyxJ9Ez8lqwv3YxtIN050GR0h94GVVKP5mmJoK94844kySMS3 0tJSCMbylr3V1PdxsegE1FWpEDQC4kQgV0axIrZ8z4lfqRLTjASUCDcESU4bAtOcACUi cXODj97m1CHkisdr56IhhVaRlVAJ+/lWIKZ9Ol7H8JxTB+Ehgo+VlbaxRHoOwFptRRbY YYa77lvAasd0TpftInTfxyM97CrkMj+Yl54Bpwx8wm4sHlbwB91Nwss22pwNat8Ya6wF ZoXhw8J6cO6LEx/+OlpVorzDMYtpDg2rQNrjAVf6d71+/KjwGW6MgA9YAwXUa2qYVnnv n3LA== X-Gm-Message-State: AOJu0Yz5RU/mvvEmMZn1Fw28yxwvt1icU/OXW+Sp8DI6CmjvZ0KsKrVx qBky1mKOwMLCmy6ZfL4PYFnbu16alduZIrN8wQE= X-Google-Smtp-Source: AGHT+IGQHLCjxlYGbgjDdAbjtb0hIZdj+eCJB+nh6nQ/zmmygGSi9yEMvPddaGaqRoVhScdH1+nXrg== X-Received: by 2002:a17:902:fb8b:b0:1c9:d111:9b28 with SMTP id lg11-20020a170902fb8b00b001c9d1119b28mr643020plb.49.1697667973487; Wed, 18 Oct 2023 15:26:13 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 16/29] tcg/arm: Use tcg_use_softmmu Date: Wed, 18 Oct 2023 15:25:44 -0700 Message-Id: <20231018222557.1562065-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231018222557.1562065-1-richard.henderson@linaro.org> References: <20231018222557.1562065-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697668126639100001 Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.c.inc | 203 +++++++++++++++++++-------------------- 1 file changed, 97 insertions(+), 106 deletions(-) diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index 0d9c2d157b..fc78566494 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -89,9 +89,7 @@ static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind = kind, int slot) =20 #define TCG_REG_TMP TCG_REG_R12 #define TCG_VEC_TMP TCG_REG_Q15 -#ifndef CONFIG_SOFTMMU #define TCG_REG_GUEST_BASE TCG_REG_R11 -#endif =20 typedef enum { COND_EQ =3D 0x0, @@ -356,14 +354,8 @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int t= ype, * r0-r3 will be overwritten when reading the tlb entry (system-mode only); * r14 will be overwritten by the BLNE branching to the slow path. */ -#ifdef CONFIG_SOFTMMU #define ALL_QLDST_REGS \ - (ALL_GENERAL_REGS & ~((1 << TCG_REG_R0) | (1 << TCG_REG_R1) | \ - (1 << TCG_REG_R2) | (1 << TCG_REG_R3) | \ - (1 << TCG_REG_R14))) -#else -#define ALL_QLDST_REGS (ALL_GENERAL_REGS & ~(1 << TCG_REG_R14)) -#endif + (ALL_GENERAL_REGS & ~((tcg_use_softmmu ? 0xf : 0) | (1 << TCG_REG_R14)= )) =20 /* * ARM immediates for ALU instructions are made of an unsigned 8-bit @@ -1387,113 +1379,115 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGCon= text *s, HostAddress *h, MemOp opc =3D get_memop(oi); unsigned a_mask; =20 -#ifdef CONFIG_SOFTMMU - *h =3D (HostAddress){ - .cond =3D COND_AL, - .base =3D addrlo, - .index =3D TCG_REG_R1, - .index_scratch =3D true, - }; -#else - *h =3D (HostAddress){ - .cond =3D COND_AL, - .base =3D addrlo, - .index =3D guest_base ? TCG_REG_GUEST_BASE : -1, - .index_scratch =3D false, - }; -#endif + if (tcg_use_softmmu) { + *h =3D (HostAddress){ + .cond =3D COND_AL, + .base =3D addrlo, + .index =3D TCG_REG_R1, + .index_scratch =3D true, + }; + } else { + *h =3D (HostAddress){ + .cond =3D COND_AL, + .base =3D addrlo, + .index =3D guest_base ? TCG_REG_GUEST_BASE : -1, + .index_scratch =3D false, + }; + } =20 h->aa =3D atom_and_align_for_opc(s, opc, MO_ATOM_IFALIGN, false); a_mask =3D (1 << h->aa.align) - 1; =20 -#ifdef CONFIG_SOFTMMU - int mem_index =3D get_mmuidx(oi); - int cmp_off =3D is_ld ? offsetof(CPUTLBEntry, addr_read) - : offsetof(CPUTLBEntry, addr_write); - int fast_off =3D tlb_mask_table_ofs(s, mem_index); - unsigned s_mask =3D (1 << (opc & MO_SIZE)) - 1; - TCGReg t_addr; + if (tcg_use_softmmu) { + int mem_index =3D get_mmuidx(oi); + int cmp_off =3D is_ld ? offsetof(CPUTLBEntry, addr_read) + : offsetof(CPUTLBEntry, addr_write); + int fast_off =3D tlb_mask_table_ofs(s, mem_index); + unsigned s_mask =3D (1 << (opc & MO_SIZE)) - 1; + TCGReg t_addr; =20 - ldst =3D new_ldst_label(s); - ldst->is_ld =3D is_ld; - ldst->oi =3D oi; - ldst->addrlo_reg =3D addrlo; - ldst->addrhi_reg =3D addrhi; + ldst =3D new_ldst_label(s); + ldst->is_ld =3D is_ld; + ldst->oi =3D oi; + ldst->addrlo_reg =3D addrlo; + ldst->addrhi_reg =3D addrhi; =20 - /* Load cpu->neg.tlb.f[mmu_idx].{mask,table} into {r0,r1}. */ - QEMU_BUILD_BUG_ON(offsetof(CPUTLBDescFast, mask) !=3D 0); - QEMU_BUILD_BUG_ON(offsetof(CPUTLBDescFast, table) !=3D 4); - tcg_out_ldrd_8(s, COND_AL, TCG_REG_R0, TCG_AREG0, fast_off); + /* Load cpu->neg.tlb.f[mmu_idx].{mask,table} into {r0,r1}. */ + QEMU_BUILD_BUG_ON(offsetof(CPUTLBDescFast, mask) !=3D 0); + QEMU_BUILD_BUG_ON(offsetof(CPUTLBDescFast, table) !=3D 4); + tcg_out_ldrd_8(s, COND_AL, TCG_REG_R0, TCG_AREG0, fast_off); =20 - /* Extract the tlb index from the address into R0. */ - tcg_out_dat_reg(s, COND_AL, ARITH_AND, TCG_REG_R0, TCG_REG_R0, addrlo, - SHIFT_IMM_LSR(s->page_bits - CPU_TLB_ENTRY_BITS)); + /* Extract the tlb index from the address into R0. */ + tcg_out_dat_reg(s, COND_AL, ARITH_AND, TCG_REG_R0, TCG_REG_R0, add= rlo, + SHIFT_IMM_LSR(s->page_bits - CPU_TLB_ENTRY_BITS)); =20 - /* - * Add the tlb_table pointer, creating the CPUTLBEntry address in R1. - * Load the tlb comparator into R2/R3 and the fast path addend into R1. - */ - QEMU_BUILD_BUG_ON(HOST_BIG_ENDIAN); - if (cmp_off =3D=3D 0) { - if (s->addr_type =3D=3D TCG_TYPE_I32) { - tcg_out_ld32_rwb(s, COND_AL, TCG_REG_R2, TCG_REG_R1, TCG_REG_R= 0); + /* + * Add the tlb_table pointer, creating the CPUTLBEntry address in = R1. + * Load the tlb comparator into R2/R3 and the fast path addend int= o R1. + */ + QEMU_BUILD_BUG_ON(HOST_BIG_ENDIAN); + if (cmp_off =3D=3D 0) { + if (s->addr_type =3D=3D TCG_TYPE_I32) { + tcg_out_ld32_rwb(s, COND_AL, TCG_REG_R2, + TCG_REG_R1, TCG_REG_R0); + } else { + tcg_out_ldrd_rwb(s, COND_AL, TCG_REG_R2, + TCG_REG_R1, TCG_REG_R0); + } } else { - tcg_out_ldrd_rwb(s, COND_AL, TCG_REG_R2, TCG_REG_R1, TCG_REG_R= 0); + tcg_out_dat_reg(s, COND_AL, ARITH_ADD, + TCG_REG_R1, TCG_REG_R1, TCG_REG_R0, 0); + if (s->addr_type =3D=3D TCG_TYPE_I32) { + tcg_out_ld32_12(s, COND_AL, TCG_REG_R2, TCG_REG_R1, cmp_of= f); + } else { + tcg_out_ldrd_8(s, COND_AL, TCG_REG_R2, TCG_REG_R1, cmp_off= ); + } } - } else { - tcg_out_dat_reg(s, COND_AL, ARITH_ADD, - TCG_REG_R1, TCG_REG_R1, TCG_REG_R0, 0); - if (s->addr_type =3D=3D TCG_TYPE_I32) { - tcg_out_ld32_12(s, COND_AL, TCG_REG_R2, TCG_REG_R1, cmp_off); + + /* Load the tlb addend. */ + tcg_out_ld32_12(s, COND_AL, TCG_REG_R1, TCG_REG_R1, + offsetof(CPUTLBEntry, addend)); + + /* + * Check alignment, check comparators. + * Do this in 2-4 insns. Use MOVW for v7, if possible, + * to reduce the number of sequential conditional instructions. + * Almost all guests have at least 4k pages, which means that we n= eed + * to clear at least 9 bits even for an 8-byte memory, which means= it + * isn't worth checking for an immediate operand for BIC. + * + * For unaligned accesses, test the page of the last unit of align= ment. + * This leaves the least significant alignment bits unchanged, and= of + * course must be zero. + */ + t_addr =3D addrlo; + if (a_mask < s_mask) { + t_addr =3D TCG_REG_R0; + tcg_out_dat_imm(s, COND_AL, ARITH_ADD, t_addr, + addrlo, s_mask - a_mask); + } + if (use_armv7_instructions && s->page_bits <=3D 16) { + tcg_out_movi32(s, COND_AL, TCG_REG_TMP, ~(s->page_mask | a_mas= k)); + tcg_out_dat_reg(s, COND_AL, ARITH_BIC, TCG_REG_TMP, + t_addr, TCG_REG_TMP, 0); + tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0, + TCG_REG_R2, TCG_REG_TMP, 0); } else { - tcg_out_ldrd_8(s, COND_AL, TCG_REG_R2, TCG_REG_R1, cmp_off); + if (a_mask) { + tcg_debug_assert(a_mask <=3D 0xff); + tcg_out_dat_imm(s, COND_AL, ARITH_TST, 0, addrlo, a_mask); + } + tcg_out_dat_reg(s, COND_AL, ARITH_MOV, TCG_REG_TMP, 0, t_addr, + SHIFT_IMM_LSR(s->page_bits)); + tcg_out_dat_reg(s, (a_mask ? COND_EQ : COND_AL), ARITH_CMP, + 0, TCG_REG_R2, TCG_REG_TMP, + SHIFT_IMM_LSL(s->page_bits)); } - } =20 - /* Load the tlb addend. */ - tcg_out_ld32_12(s, COND_AL, TCG_REG_R1, TCG_REG_R1, - offsetof(CPUTLBEntry, addend)); - - /* - * Check alignment, check comparators. - * Do this in 2-4 insns. Use MOVW for v7, if possible, - * to reduce the number of sequential conditional instructions. - * Almost all guests have at least 4k pages, which means that we need - * to clear at least 9 bits even for an 8-byte memory, which means it - * isn't worth checking for an immediate operand for BIC. - * - * For unaligned accesses, test the page of the last unit of alignment. - * This leaves the least significant alignment bits unchanged, and of - * course must be zero. - */ - t_addr =3D addrlo; - if (a_mask < s_mask) { - t_addr =3D TCG_REG_R0; - tcg_out_dat_imm(s, COND_AL, ARITH_ADD, t_addr, - addrlo, s_mask - a_mask); - } - if (use_armv7_instructions && s->page_bits <=3D 16) { - tcg_out_movi32(s, COND_AL, TCG_REG_TMP, ~(s->page_mask | a_mask)); - tcg_out_dat_reg(s, COND_AL, ARITH_BIC, TCG_REG_TMP, - t_addr, TCG_REG_TMP, 0); - tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0, TCG_REG_R2, TCG_REG_TMP,= 0); - } else { - if (a_mask) { - tcg_debug_assert(a_mask <=3D 0xff); - tcg_out_dat_imm(s, COND_AL, ARITH_TST, 0, addrlo, a_mask); + if (s->addr_type !=3D TCG_TYPE_I32) { + tcg_out_dat_reg(s, COND_EQ, ARITH_CMP, 0, TCG_REG_R3, addrhi, = 0); } - tcg_out_dat_reg(s, COND_AL, ARITH_MOV, TCG_REG_TMP, 0, t_addr, - SHIFT_IMM_LSR(s->page_bits)); - tcg_out_dat_reg(s, (a_mask ? COND_EQ : COND_AL), ARITH_CMP, - 0, TCG_REG_R2, TCG_REG_TMP, - SHIFT_IMM_LSL(s->page_bits)); - } - - if (s->addr_type !=3D TCG_TYPE_I32) { - tcg_out_dat_reg(s, COND_EQ, ARITH_CMP, 0, TCG_REG_R3, addrhi, 0); - } -#else - if (a_mask) { + } else if (a_mask) { ldst =3D new_ldst_label(s); ldst->is_ld =3D is_ld; ldst->oi =3D oi; @@ -1505,7 +1499,6 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext= *s, HostAddress *h, /* tst addr, #mask */ tcg_out_dat_imm(s, COND_AL, ARITH_TST, 0, addrlo, a_mask); } -#endif =20 return ldst; } @@ -2931,12 +2924,10 @@ static void tcg_target_qemu_prologue(TCGContext *s) =20 tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]); =20 -#ifndef CONFIG_SOFTMMU - if (guest_base) { + if (!tcg_use_softmmu && guest_base) { tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_GUEST_BASE, guest_base); tcg_regset_set_reg(s->reserved_regs, TCG_REG_GUEST_BASE); } -#endif =20 tcg_out_b_reg(s, COND_AL, tcg_target_call_iarg_regs[1]); =20 --=20 2.34.1 From nobody Wed Nov 27 17:32:24 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1697668274; cv=none; d=zohomail.com; s=zohoarc; b=Z+1FrZivloWFtRhjn2NP0fdYPhkQzM4xyHT/9+258HgJh6N6JOKryJdmDNEYzag0MRVV/IqxXxpyMTKlo+SoBbLKLgDnZJji42Aw8H1piPf4aEQiXTy6FyigC6deLnh+TZsL3rGvf+6DSsVsZ7/l9ebegcSrxM5BvPKJhQfBR7M= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1697668274; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=H+PnCNXxM75sZlgHHFx2OEqwx4bspJhNCS0HMsehl/Y=; b=BoNidL7kvQEL9C7kCd5DMYQQPmwbprphaeB0MT4TQh9MfwHkP93+FzaZfc3iolILh60apzGX3hJuKmi3yVB3rUkbeob29OPb/yOB6AoScy0chxrrO9/qmudfG/wqcAJHuK4NiGVb8yHaGc3AS8g2o0vxpkF2N6DYrHieTN5FbVI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1697668274319296.09223647433294; Wed, 18 Oct 2023 15:31:14 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qtEzf-0008AH-EN; Wed, 18 Oct 2023 18:26:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qtEza-00087k-67 for qemu-devel@nongnu.org; Wed, 18 Oct 2023 18:26:18 -0400 Received: from mail-pl1-x634.google.com ([2607:f8b0:4864:20::634]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qtEzY-0002V3-74 for qemu-devel@nongnu.org; Wed, 18 Oct 2023 18:26:17 -0400 Received: by mail-pl1-x634.google.com with SMTP id d9443c01a7336-1c9c5a1b87bso52640735ad.3 for ; Wed, 18 Oct 2023 15:26:15 -0700 (PDT) Received: from stoup.. ([71.212.149.95]) by smtp.gmail.com with ESMTPSA id 13-20020a170902c24d00b001b9d95945afsm431058plg.155.2023.10.18.15.26.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Oct 2023 15:26:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1697667974; x=1698272774; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=H+PnCNXxM75sZlgHHFx2OEqwx4bspJhNCS0HMsehl/Y=; b=DeIy5+s0wNdYGXBmqFQ2Xv+a0uLNMyhNSgEU8zNexRdffIzacjTbKdpNszvvKNCrzM dZNk7zaMlApn68Sdxf6GtZJGNGBD5Q6AMAcvhnvnyLS3pt4jQX3T/g0sjenS++XULEqq p5eM6KGBTXfMh7e1dKQEJE8w5q4wln6NH+B8XvjOJPRnONEEgVyUzAs9lqPrTYzP4cS5 V8AsVh7brvLTPCJNAC0FvGnkmg+JPmlwtLbqjTZ3+CnH7mx/TdDQhSmJTl67tWhA7x0h 97Do8ZmPlmNdb2V8YqTkCUYxDI8xxo4PU1wOKLY+xpv0Dw47AFPEYp7aNZFo3Z2YK5yV Qg1g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697667974; x=1698272774; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=H+PnCNXxM75sZlgHHFx2OEqwx4bspJhNCS0HMsehl/Y=; b=XDSyXesVOxYjEhCbZIXN8WS+ACj+mK+/ozFhf8gkBS2sJfPLs5Dq6QZ2iMt9fkd9sl mGr2WjfTgHbQO7K9FSKnq6e+aDyOa2Qo7reebP9iEFqY+Dt43Vay19x/7tPtA5T8dTDk ptt8bU8pEwfPfvXvn8gWv8O+kMlZ5tFedDLCXutI6bmJO4ev7WlusiYyZZPdBKYQGAXb 5c6QUZNbVlGkmGLRbmGj2hW+6Vyc+iBxXBWiboCosYPpPBwobjPm5G6iET3we+EFeh1d OyAUvryzrj3MtAuHi9KfJezl/uHSd0UKU54U9p0mZgTFKdukgrSswsy79pmn8dXnco7d IpeA== X-Gm-Message-State: AOJu0YxmFP86jAAGWAR/tYrBvYUjeXyjCabTwJjoP4Vkrpxzu8O9jBf4 ktvStyg0vSq1J2VZAyzB6b5aW7WlDcJFP7pCXdM= X-Google-Smtp-Source: AGHT+IHdmrTUo3EflmGq4LSeyBNtbktdtfs4HX7DWUf1nz1G3Di378qY9HE/LQUE/NU1s75ZBcBTFg== X-Received: by 2002:a17:902:f385:b0:1c7:365a:566d with SMTP id f5-20020a170902f38500b001c7365a566dmr515297ple.66.1697667974462; Wed, 18 Oct 2023 15:26:14 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 17/29] tcg/aarch64: Use tcg_use_softmmu Date: Wed, 18 Oct 2023 15:25:45 -0700 Message-Id: <20231018222557.1562065-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231018222557.1562065-1-richard.henderson@linaro.org> References: <20231018222557.1562065-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697668275467100002 Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.c.inc | 177 +++++++++++++++++------------------ 1 file changed, 88 insertions(+), 89 deletions(-) diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index 3afb896a3a..a3efa1e67a 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -77,9 +77,7 @@ static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind = kind, int slot) #define TCG_REG_TMP2 TCG_REG_X30 #define TCG_VEC_TMP0 TCG_REG_V31 =20 -#ifndef CONFIG_SOFTMMU #define TCG_REG_GUEST_BASE TCG_REG_X28 -#endif =20 static bool reloc_pc26(tcg_insn_unit *src_rw, const tcg_insn_unit *target) { @@ -1664,97 +1662,98 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGConte= xt *s, HostAddress *h, s_bits =3D=3D MO_128); a_mask =3D (1 << h->aa.align) - 1; =20 -#ifdef CONFIG_SOFTMMU - unsigned s_mask =3D (1u << s_bits) - 1; - unsigned mem_index =3D get_mmuidx(oi); - TCGReg addr_adj; - TCGType mask_type; - uint64_t compare_mask; + if (tcg_use_softmmu) { + unsigned s_mask =3D (1u << s_bits) - 1; + unsigned mem_index =3D get_mmuidx(oi); + TCGReg addr_adj; + TCGType mask_type; + uint64_t compare_mask; =20 - ldst =3D new_ldst_label(s); - ldst->is_ld =3D is_ld; - ldst->oi =3D oi; - ldst->addrlo_reg =3D addr_reg; - - mask_type =3D (s->page_bits + s->tlb_dyn_max_bits > 32 - ? TCG_TYPE_I64 : TCG_TYPE_I32); - - /* Load cpu->neg.tlb.f[mmu_idx].{mask,table} into {tmp0,tmp1}. */ - QEMU_BUILD_BUG_ON(offsetof(CPUTLBDescFast, mask) !=3D 0); - QEMU_BUILD_BUG_ON(offsetof(CPUTLBDescFast, table) !=3D 8); - tcg_out_insn(s, 3314, LDP, TCG_REG_TMP0, TCG_REG_TMP1, TCG_AREG0, - tlb_mask_table_ofs(s, mem_index), 1, 0); - - /* Extract the TLB index from the address into X0. */ - tcg_out_insn(s, 3502S, AND_LSR, mask_type =3D=3D TCG_TYPE_I64, - TCG_REG_TMP0, TCG_REG_TMP0, addr_reg, - s->page_bits - CPU_TLB_ENTRY_BITS); - - /* Add the tlb_table pointer, forming the CPUTLBEntry address in TMP1.= */ - tcg_out_insn(s, 3502, ADD, 1, TCG_REG_TMP1, TCG_REG_TMP1, TCG_REG_TMP0= ); - - /* Load the tlb comparator into TMP0, and the fast path addend into TM= P1. */ - QEMU_BUILD_BUG_ON(HOST_BIG_ENDIAN); - tcg_out_ld(s, addr_type, TCG_REG_TMP0, TCG_REG_TMP1, - is_ld ? offsetof(CPUTLBEntry, addr_read) - : offsetof(CPUTLBEntry, addr_write)); - tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, TCG_REG_TMP1, - offsetof(CPUTLBEntry, addend)); - - /* - * For aligned accesses, we check the first byte and include the align= ment - * bits within the address. For unaligned access, we check that we do= n't - * cross pages using the address of the last byte of the access. - */ - if (a_mask >=3D s_mask) { - addr_adj =3D addr_reg; - } else { - addr_adj =3D TCG_REG_TMP2; - tcg_out_insn(s, 3401, ADDI, addr_type, - addr_adj, addr_reg, s_mask - a_mask); - } - compare_mask =3D (uint64_t)s->page_mask | a_mask; - - /* Store the page mask part of the address into TMP2. */ - tcg_out_logicali(s, I3404_ANDI, addr_type, TCG_REG_TMP2, - addr_adj, compare_mask); - - /* Perform the address comparison. */ - tcg_out_cmp(s, addr_type, TCG_REG_TMP0, TCG_REG_TMP2, 0); - - /* If not equal, we jump to the slow path. */ - ldst->label_ptr[0] =3D s->code_ptr; - tcg_out_insn(s, 3202, B_C, TCG_COND_NE, 0); - - h->base =3D TCG_REG_TMP1; - h->index =3D addr_reg; - h->index_ext =3D addr_type; -#else - if (a_mask) { ldst =3D new_ldst_label(s); - ldst->is_ld =3D is_ld; ldst->oi =3D oi; ldst->addrlo_reg =3D addr_reg; =20 - /* tst addr, #mask */ - tcg_out_logicali(s, I3404_ANDSI, 0, TCG_REG_XZR, addr_reg, a_mask); + mask_type =3D (s->page_bits + s->tlb_dyn_max_bits > 32 + ? TCG_TYPE_I64 : TCG_TYPE_I32); =20 - /* b.ne slow_path */ + /* Load cpu->neg.tlb.f[mmu_idx].{mask,table} into {tmp0,tmp1}. */ + QEMU_BUILD_BUG_ON(offsetof(CPUTLBDescFast, mask) !=3D 0); + QEMU_BUILD_BUG_ON(offsetof(CPUTLBDescFast, table) !=3D 8); + tcg_out_insn(s, 3314, LDP, TCG_REG_TMP0, TCG_REG_TMP1, TCG_AREG0, + tlb_mask_table_ofs(s, mem_index), 1, 0); + + /* Extract the TLB index from the address into X0. */ + tcg_out_insn(s, 3502S, AND_LSR, mask_type =3D=3D TCG_TYPE_I64, + TCG_REG_TMP0, TCG_REG_TMP0, addr_reg, + s->page_bits - CPU_TLB_ENTRY_BITS); + + /* Add the tlb_table pointer, forming the CPUTLBEntry address. */ + tcg_out_insn(s, 3502, ADD, 1, TCG_REG_TMP1, TCG_REG_TMP1, TCG_REG_= TMP0); + + /* Load the tlb comparator into TMP0, and the fast path addend. */ + QEMU_BUILD_BUG_ON(HOST_BIG_ENDIAN); + tcg_out_ld(s, addr_type, TCG_REG_TMP0, TCG_REG_TMP1, + is_ld ? offsetof(CPUTLBEntry, addr_read) + : offsetof(CPUTLBEntry, addr_write)); + tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, TCG_REG_TMP1, + offsetof(CPUTLBEntry, addend)); + + /* + * For aligned accesses, we check the first byte and include + * the alignment bits within the address. For unaligned access, + * we check that we don't cross pages using the address of the + * last byte of the access. + */ + if (a_mask >=3D s_mask) { + addr_adj =3D addr_reg; + } else { + addr_adj =3D TCG_REG_TMP2; + tcg_out_insn(s, 3401, ADDI, addr_type, + addr_adj, addr_reg, s_mask - a_mask); + } + compare_mask =3D (uint64_t)s->page_mask | a_mask; + + /* Store the page mask part of the address into TMP2. */ + tcg_out_logicali(s, I3404_ANDI, addr_type, TCG_REG_TMP2, + addr_adj, compare_mask); + + /* Perform the address comparison. */ + tcg_out_cmp(s, addr_type, TCG_REG_TMP0, TCG_REG_TMP2, 0); + + /* If not equal, we jump to the slow path. */ ldst->label_ptr[0] =3D s->code_ptr; tcg_out_insn(s, 3202, B_C, TCG_COND_NE, 0); - } =20 - if (guest_base || addr_type =3D=3D TCG_TYPE_I32) { - h->base =3D TCG_REG_GUEST_BASE; + h->base =3D TCG_REG_TMP1; h->index =3D addr_reg; h->index_ext =3D addr_type; } else { - h->base =3D addr_reg; - h->index =3D TCG_REG_XZR; - h->index_ext =3D TCG_TYPE_I64; + if (a_mask) { + ldst =3D new_ldst_label(s); + + ldst->is_ld =3D is_ld; + ldst->oi =3D oi; + ldst->addrlo_reg =3D addr_reg; + + /* tst addr, #mask */ + tcg_out_logicali(s, I3404_ANDSI, 0, TCG_REG_XZR, addr_reg, a_m= ask); + + /* b.ne slow_path */ + ldst->label_ptr[0] =3D s->code_ptr; + tcg_out_insn(s, 3202, B_C, TCG_COND_NE, 0); + } + + if (guest_base || addr_type =3D=3D TCG_TYPE_I32) { + h->base =3D TCG_REG_GUEST_BASE; + h->index =3D addr_reg; + h->index_ext =3D addr_type; + } else { + h->base =3D addr_reg; + h->index =3D TCG_REG_XZR; + h->index_ext =3D TCG_TYPE_I64; + } } -#endif =20 return ldst; } @@ -3117,16 +3116,16 @@ static void tcg_target_qemu_prologue(TCGContext *s) tcg_set_frame(s, TCG_REG_SP, TCG_STATIC_CALL_ARGS_SIZE, CPU_TEMP_BUF_NLONGS * sizeof(long)); =20 -#if !defined(CONFIG_SOFTMMU) - /* - * Note that XZR cannot be encoded in the address base register slot, - * as that actually encodes SP. Depending on the guest, we may need - * to zero-extend the guest address via the address index register slo= t, - * therefore we need to load even a zero guest base into a register. - */ - tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_GUEST_BASE, guest_base); - tcg_regset_set_reg(s->reserved_regs, TCG_REG_GUEST_BASE); -#endif + if (!tcg_use_softmmu) { + /* + * Note that XZR cannot be encoded in the address base register sl= ot, + * as that actually encodes SP. Depending on the guest, we may ne= ed + * to zero-extend the guest address via the address index register= slot, + * therefore we need to load even a zero guest base into a registe= r. + */ + tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_GUEST_BASE, guest_base); + tcg_regset_set_reg(s->reserved_regs, TCG_REG_GUEST_BASE); + } =20 tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]); tcg_out_insn(s, 3207, BR, tcg_target_call_iarg_regs[1]); --=20 2.34.1 From nobody Wed Nov 27 17:32:24 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1697668360; cv=none; d=zohomail.com; s=zohoarc; b=nrc9g8XK7OCZWyXulSpwjbBbOdAnH6USX0+K/zL30tvnLfmUuLg5Mz6fWWywFkJcV9VFV2ebAJYtL3JADAmdey/c8i82b0uaGDmmj01Uou+utc69YdnMqYeFo+adq13oDOtwA7IYl+rwsHN36GGnU54sQhENsaSWmcoHkwFCHjs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1697668360; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=kkl77GmQxI4p68IyFC/SpNGEsbPXI+i6lxeUoQQHshE=; b=W4wq8k6XHu7GGnw5vr7z9fLB/bhnkAhevWCiPQ6CuZrMNQkh6vwsYiTFKIZ91N3TOMW2GFO3rS31/qgo7MgsT5xL0vSDRk1SSbuLhT7rvgikW7+CcjsmJL/91zIlTqXnhG3XmFCoHXMLZLx1R5mcoqUbJSwo0XCVC3icRUe4Aw4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1697668360740350.656626841752; Wed, 18 Oct 2023 15:32:40 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qtEzj-0008DG-Vh; Wed, 18 Oct 2023 18:26:28 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qtEza-00087o-PW for qemu-devel@nongnu.org; Wed, 18 Oct 2023 18:26:18 -0400 Received: from mail-pl1-x636.google.com ([2607:f8b0:4864:20::636]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qtEzY-0002VB-MV for qemu-devel@nongnu.org; Wed, 18 Oct 2023 18:26:18 -0400 Received: by mail-pl1-x636.google.com with SMTP id d9443c01a7336-1c9b7c234a7so63731215ad.3 for ; Wed, 18 Oct 2023 15:26:16 -0700 (PDT) Received: from stoup.. ([71.212.149.95]) by smtp.gmail.com with ESMTPSA id 13-20020a170902c24d00b001b9d95945afsm431058plg.155.2023.10.18.15.26.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Oct 2023 15:26:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1697667975; x=1698272775; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=kkl77GmQxI4p68IyFC/SpNGEsbPXI+i6lxeUoQQHshE=; b=KdPzu65KqaVCrt8h3DXyno4Wsojph6cCO5h8pKJjwTkGAdzX/eQTHIJCri92GtCs1u B1tkRKQ4EJ+5xA9Ean1K+8UjxVb/qNHgp2gcggfpMWy5L6Z/d/lDpdYCCu21uRmhNjm2 8lnhJScc1q087cdhNbz32wqI0tsLn8lh6+E+85HaZP5cZ3KvrTjxq/NInoj/oGpKiG6a vGzS5eiMGTiTamZ0CxM7I7cRlGLYS01xPC4D5xfAZxYpS9Mh8NNE8l3c0KdGBU51dYkZ xrOT1Wa3QA6E/8KjHezDqAODBKH0dRuVjuw7GsggQ3moeoS9e+L/EYogHrK2MhiOfvdb aKxg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697667975; x=1698272775; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=kkl77GmQxI4p68IyFC/SpNGEsbPXI+i6lxeUoQQHshE=; b=XjCPijXAIavNm08wVybagdNusqfyL7KD3Q27bYLpvNLbYqEs0trHRAsgBXrWMuRMTy Cxe7+YJHXSFkp8pmT4id74zDMF2XQ2X8atPzp1grC/2wWkwpOjH6YD4hVupbmGB1Kqk4 CpOTSdH8bSrgo96sWO2PjZnhbgzWey5y23ZblzowMHMhjCBpR1RNOM2KFXvtfdXBT1Ba KkkfRxssKFBK2K97J04H7yRjvMeHhEAsTP2t+kjM3mtOqdQKlH1YPWO8kNvTHifTT88o mpyjnfWUU+uWbBXa7bDjfG20YT8xJqJe6d+aFod7667GHoOYDhPftg/nJl7FLToQmzLf lC3A== X-Gm-Message-State: AOJu0YxLbvGsEV9jCqS/L1vEs4/cJLUPprPFeP2MTrwNFgumR96G/xRX L8KYTw2xG1DLjOW7rv5YPGgbly9YhLtfv19j9CE= X-Google-Smtp-Source: AGHT+IE4LUb8Mo9o9iK6GxM64FQDRphsEcmVLbPIJJZBNYyLSBZhSPpxfOPHsF8kkITFaCSEwJZjUA== X-Received: by 2002:a17:902:ea0e:b0:1ca:20a0:7b08 with SMTP id s14-20020a170902ea0e00b001ca20a07b08mr706139plg.50.1697667975397; Wed, 18 Oct 2023 15:26:15 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 18/29] tcg/i386: Use tcg_use_softmmu Date: Wed, 18 Oct 2023 15:25:46 -0700 Message-Id: <20231018222557.1562065-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231018222557.1562065-1-richard.henderson@linaro.org> References: <20231018222557.1562065-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697668361723100009 Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.c.inc | 184 ++++++++++++++++++-------------------- 1 file changed, 89 insertions(+), 95 deletions(-) diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index 788d608150..a3c0473395 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -153,11 +153,8 @@ static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKi= nd kind, int slot) # define ALL_VECTOR_REGS 0x00ff0000u # define ALL_BYTEL_REGS 0x0000000fu #endif -#ifdef CONFIG_SOFTMMU -# define SOFTMMU_RESERVE_REGS ((1 << TCG_REG_L0) | (1 << TCG_REG_L1)) -#else -# define SOFTMMU_RESERVE_REGS 0 -#endif +#define SOFTMMU_RESERVE_REGS \ + (tcg_use_softmmu ? (1 << TCG_REG_L0) | (1 << TCG_REG_L1) : 0) =20 /* For 64-bit, we always know that CMOV is available. */ #if TCG_TARGET_REG_BITS =3D=3D 64 @@ -1933,7 +1930,6 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, = TCGLabelQemuLdst *l) return true; } =20 -#ifndef CONFIG_SOFTMMU static HostAddress x86_guest_base =3D { .index =3D -1 }; @@ -1965,7 +1961,6 @@ static inline int setup_guest_base_seg(void) return 0; } #endif /* setup_guest_base_seg */ -#endif /* !SOFTMMU */ =20 #define MIN_TLB_MASK_TABLE_OFS INT_MIN =20 @@ -1984,94 +1979,94 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGConte= xt *s, HostAddress *h, MemOp s_bits =3D opc & MO_SIZE; unsigned a_mask; =20 -#ifdef CONFIG_SOFTMMU - h->index =3D TCG_REG_L0; - h->ofs =3D 0; - h->seg =3D 0; -#else - *h =3D x86_guest_base; -#endif + if (tcg_use_softmmu) { + h->index =3D TCG_REG_L0; + h->ofs =3D 0; + h->seg =3D 0; + } else { + *h =3D x86_guest_base; + } h->base =3D addrlo; h->aa =3D atom_and_align_for_opc(s, opc, MO_ATOM_IFALIGN, s_bits =3D= =3D MO_128); a_mask =3D (1 << h->aa.align) - 1; =20 -#ifdef CONFIG_SOFTMMU - int cmp_ofs =3D is_ld ? offsetof(CPUTLBEntry, addr_read) - : offsetof(CPUTLBEntry, addr_write); - TCGType ttype =3D TCG_TYPE_I32; - TCGType tlbtype =3D TCG_TYPE_I32; - int trexw =3D 0, hrexw =3D 0, tlbrexw =3D 0; - unsigned mem_index =3D get_mmuidx(oi); - unsigned s_mask =3D (1 << s_bits) - 1; - int fast_ofs =3D tlb_mask_table_ofs(s, mem_index); - int tlb_mask; + if (tcg_use_softmmu) { + int cmp_ofs =3D is_ld ? offsetof(CPUTLBEntry, addr_read) + : offsetof(CPUTLBEntry, addr_write); + TCGType ttype =3D TCG_TYPE_I32; + TCGType tlbtype =3D TCG_TYPE_I32; + int trexw =3D 0, hrexw =3D 0, tlbrexw =3D 0; + unsigned mem_index =3D get_mmuidx(oi); + unsigned s_mask =3D (1 << s_bits) - 1; + int fast_ofs =3D tlb_mask_table_ofs(s, mem_index); + int tlb_mask; =20 - ldst =3D new_ldst_label(s); - ldst->is_ld =3D is_ld; - ldst->oi =3D oi; - ldst->addrlo_reg =3D addrlo; - ldst->addrhi_reg =3D addrhi; + ldst =3D new_ldst_label(s); + ldst->is_ld =3D is_ld; + ldst->oi =3D oi; + ldst->addrlo_reg =3D addrlo; + ldst->addrhi_reg =3D addrhi; =20 - if (TCG_TARGET_REG_BITS =3D=3D 64) { - ttype =3D s->addr_type; - trexw =3D (ttype =3D=3D TCG_TYPE_I32 ? 0 : P_REXW); - if (TCG_TYPE_PTR =3D=3D TCG_TYPE_I64) { - hrexw =3D P_REXW; - if (s->page_bits + s->tlb_dyn_max_bits > 32) { - tlbtype =3D TCG_TYPE_I64; - tlbrexw =3D P_REXW; + if (TCG_TARGET_REG_BITS =3D=3D 64) { + ttype =3D s->addr_type; + trexw =3D (ttype =3D=3D TCG_TYPE_I32 ? 0 : P_REXW); + if (TCG_TYPE_PTR =3D=3D TCG_TYPE_I64) { + hrexw =3D P_REXW; + if (s->page_bits + s->tlb_dyn_max_bits > 32) { + tlbtype =3D TCG_TYPE_I64; + tlbrexw =3D P_REXW; + } } } - } =20 - tcg_out_mov(s, tlbtype, TCG_REG_L0, addrlo); - tcg_out_shifti(s, SHIFT_SHR + tlbrexw, TCG_REG_L0, - s->page_bits - CPU_TLB_ENTRY_BITS); + tcg_out_mov(s, tlbtype, TCG_REG_L0, addrlo); + tcg_out_shifti(s, SHIFT_SHR + tlbrexw, TCG_REG_L0, + s->page_bits - CPU_TLB_ENTRY_BITS); =20 - tcg_out_modrm_offset(s, OPC_AND_GvEv + trexw, TCG_REG_L0, TCG_AREG0, - fast_ofs + offsetof(CPUTLBDescFast, mask)); + tcg_out_modrm_offset(s, OPC_AND_GvEv + trexw, TCG_REG_L0, TCG_AREG= 0, + fast_ofs + offsetof(CPUTLBDescFast, mask)); =20 - tcg_out_modrm_offset(s, OPC_ADD_GvEv + hrexw, TCG_REG_L0, TCG_AREG0, - fast_ofs + offsetof(CPUTLBDescFast, table)); + tcg_out_modrm_offset(s, OPC_ADD_GvEv + hrexw, TCG_REG_L0, TCG_AREG= 0, + fast_ofs + offsetof(CPUTLBDescFast, table)); =20 - /* - * If the required alignment is at least as large as the access, simply - * copy the address and mask. For lesser alignments, check that we do= n't - * cross pages for the complete access. - */ - if (a_mask >=3D s_mask) { - tcg_out_mov(s, ttype, TCG_REG_L1, addrlo); - } else { - tcg_out_modrm_offset(s, OPC_LEA + trexw, TCG_REG_L1, - addrlo, s_mask - a_mask); - } - tlb_mask =3D s->page_mask | a_mask; - tgen_arithi(s, ARITH_AND + trexw, TCG_REG_L1, tlb_mask, 0); + /* + * If the required alignment is at least as large as the access, + * simply copy the address and mask. For lesser alignments, + * check that we don't cross pages for the complete access. + */ + if (a_mask >=3D s_mask) { + tcg_out_mov(s, ttype, TCG_REG_L1, addrlo); + } else { + tcg_out_modrm_offset(s, OPC_LEA + trexw, TCG_REG_L1, + addrlo, s_mask - a_mask); + } + tlb_mask =3D s->page_mask | a_mask; + tgen_arithi(s, ARITH_AND + trexw, TCG_REG_L1, tlb_mask, 0); =20 - /* cmp 0(TCG_REG_L0), TCG_REG_L1 */ - tcg_out_modrm_offset(s, OPC_CMP_GvEv + trexw, - TCG_REG_L1, TCG_REG_L0, cmp_ofs); - - /* jne slow_path */ - tcg_out_opc(s, OPC_JCC_long + JCC_JNE, 0, 0, 0); - ldst->label_ptr[0] =3D s->code_ptr; - s->code_ptr +=3D 4; - - if (TCG_TARGET_REG_BITS =3D=3D 32 && s->addr_type =3D=3D TCG_TYPE_I64)= { - /* cmp 4(TCG_REG_L0), addrhi */ - tcg_out_modrm_offset(s, OPC_CMP_GvEv, addrhi, TCG_REG_L0, cmp_ofs = + 4); + /* cmp 0(TCG_REG_L0), TCG_REG_L1 */ + tcg_out_modrm_offset(s, OPC_CMP_GvEv + trexw, + TCG_REG_L1, TCG_REG_L0, cmp_ofs); =20 /* jne slow_path */ tcg_out_opc(s, OPC_JCC_long + JCC_JNE, 0, 0, 0); - ldst->label_ptr[1] =3D s->code_ptr; + ldst->label_ptr[0] =3D s->code_ptr; s->code_ptr +=3D 4; - } =20 - /* TLB Hit. */ - tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_L0, TCG_REG_L0, - offsetof(CPUTLBEntry, addend)); -#else - if (a_mask) { + if (TCG_TARGET_REG_BITS =3D=3D 32 && s->addr_type =3D=3D TCG_TYPE_= I64) { + /* cmp 4(TCG_REG_L0), addrhi */ + tcg_out_modrm_offset(s, OPC_CMP_GvEv, addrhi, + TCG_REG_L0, cmp_ofs + 4); + + /* jne slow_path */ + tcg_out_opc(s, OPC_JCC_long + JCC_JNE, 0, 0, 0); + ldst->label_ptr[1] =3D s->code_ptr; + s->code_ptr +=3D 4; + } + + /* TLB Hit. */ + tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_L0, TCG_REG_L0, + offsetof(CPUTLBEntry, addend)); + } else if (a_mask) { ldst =3D new_ldst_label(s); =20 ldst->is_ld =3D is_ld; @@ -2085,7 +2080,6 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext= *s, HostAddress *h, ldst->label_ptr[0] =3D s->code_ptr; s->code_ptr +=3D 4; } -#endif =20 return ldst; } @@ -4140,35 +4134,35 @@ static void tcg_target_qemu_prologue(TCGContext *s) tcg_out_push(s, tcg_target_callee_save_regs[i]); } =20 -#if TCG_TARGET_REG_BITS =3D=3D 32 - tcg_out_ld(s, TCG_TYPE_PTR, TCG_AREG0, TCG_REG_ESP, - (ARRAY_SIZE(tcg_target_callee_save_regs) + 1) * 4); - tcg_out_addi(s, TCG_REG_ESP, -stack_addend); - /* jmp *tb. */ - tcg_out_modrm_offset(s, OPC_GRP5, EXT5_JMPN_Ev, TCG_REG_ESP, - (ARRAY_SIZE(tcg_target_callee_save_regs) + 2) * 4 - + stack_addend); -#else -# if !defined(CONFIG_SOFTMMU) - if (guest_base) { + if (!tcg_use_softmmu && guest_base) { int seg =3D setup_guest_base_seg(); if (seg !=3D 0) { x86_guest_base.seg =3D seg; } else if (guest_base =3D=3D (int32_t)guest_base) { x86_guest_base.ofs =3D guest_base; } else { + assert(TCG_TARGET_REG_BITS =3D=3D 64); /* Choose R12 because, as a base, it requires a SIB byte. */ x86_guest_base.index =3D TCG_REG_R12; tcg_out_movi(s, TCG_TYPE_PTR, x86_guest_base.index, guest_base= ); tcg_regset_set_reg(s->reserved_regs, x86_guest_base.index); } } -# endif - tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]); - tcg_out_addi(s, TCG_REG_ESP, -stack_addend); - /* jmp *tb. */ - tcg_out_modrm(s, OPC_GRP5, EXT5_JMPN_Ev, tcg_target_call_iarg_regs[1]); -#endif + + if (TCG_TARGET_REG_BITS =3D=3D 32) { + tcg_out_ld(s, TCG_TYPE_PTR, TCG_AREG0, TCG_REG_ESP, + (ARRAY_SIZE(tcg_target_callee_save_regs) + 1) * 4); + tcg_out_addi(s, TCG_REG_ESP, -stack_addend); + /* jmp *tb. */ + tcg_out_modrm_offset(s, OPC_GRP5, EXT5_JMPN_Ev, TCG_REG_ESP, + (ARRAY_SIZE(tcg_target_callee_save_regs) + 2)= * 4 + + stack_addend); + } else { + tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[= 0]); + tcg_out_addi(s, TCG_REG_ESP, -stack_addend); + /* jmp *tb. */ + tcg_out_modrm(s, OPC_GRP5, EXT5_JMPN_Ev, tcg_target_call_iarg_regs= [1]); + } =20 /* * Return path for goto_ptr. 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697668275455100001 Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- tcg/loongarch64/tcg-target.c.inc | 126 +++++++++++++++---------------- 1 file changed, 61 insertions(+), 65 deletions(-) diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.= c.inc index 801302d85d..ccf133db4b 100644 --- a/tcg/loongarch64/tcg-target.c.inc +++ b/tcg/loongarch64/tcg-target.c.inc @@ -165,10 +165,7 @@ static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKi= nd kind, int slot) return TCG_REG_A0 + slot; } =20 -#ifndef CONFIG_SOFTMMU -#define USE_GUEST_BASE (guest_base !=3D 0) #define TCG_GUEST_BASE_REG TCG_REG_S1 -#endif =20 #define TCG_CT_CONST_ZERO 0x100 #define TCG_CT_CONST_S12 0x200 @@ -908,76 +905,77 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext= *s, HostAddress *h, h->aa =3D atom_and_align_for_opc(s, opc, MO_ATOM_IFALIGN, false); a_bits =3D h->aa.align; =20 -#ifdef CONFIG_SOFTMMU - unsigned s_bits =3D opc & MO_SIZE; - int mem_index =3D get_mmuidx(oi); - int fast_ofs =3D tlb_mask_table_ofs(s, mem_index); - int mask_ofs =3D fast_ofs + offsetof(CPUTLBDescFast, mask); - int table_ofs =3D fast_ofs + offsetof(CPUTLBDescFast, table); + if (tcg_use_softmmu) { + unsigned s_bits =3D opc & MO_SIZE; + int mem_index =3D get_mmuidx(oi); + int fast_ofs =3D tlb_mask_table_ofs(s, mem_index); + int mask_ofs =3D fast_ofs + offsetof(CPUTLBDescFast, mask); + int table_ofs =3D fast_ofs + offsetof(CPUTLBDescFast, table); =20 - ldst =3D new_ldst_label(s); - ldst->is_ld =3D is_ld; - ldst->oi =3D oi; - ldst->addrlo_reg =3D addr_reg; - - tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP0, TCG_AREG0, mask_ofs); - tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, TCG_AREG0, table_ofs); - - tcg_out_opc_srli_d(s, TCG_REG_TMP2, addr_reg, - s->page_bits - CPU_TLB_ENTRY_BITS); - tcg_out_opc_and(s, TCG_REG_TMP2, TCG_REG_TMP2, TCG_REG_TMP0); - tcg_out_opc_add_d(s, TCG_REG_TMP2, TCG_REG_TMP2, TCG_REG_TMP1); - - /* Load the tlb comparator and the addend. */ - QEMU_BUILD_BUG_ON(HOST_BIG_ENDIAN); - tcg_out_ld(s, addr_type, TCG_REG_TMP0, TCG_REG_TMP2, - is_ld ? offsetof(CPUTLBEntry, addr_read) - : offsetof(CPUTLBEntry, addr_write)); - tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP2, TCG_REG_TMP2, - offsetof(CPUTLBEntry, addend)); - - /* - * For aligned accesses, we check the first byte and include the align= ment - * bits within the address. For unaligned access, we check that we do= n't - * cross pages using the address of the last byte of the access. - */ - if (a_bits < s_bits) { - unsigned a_mask =3D (1u << a_bits) - 1; - unsigned s_mask =3D (1u << s_bits) - 1; - tcg_out_addi(s, addr_type, TCG_REG_TMP1, addr_reg, s_mask - a_mask= ); - } else { - tcg_out_mov(s, addr_type, TCG_REG_TMP1, addr_reg); - } - tcg_out_opc_bstrins_d(s, TCG_REG_TMP1, TCG_REG_ZERO, - a_bits, s->page_bits - 1); - - /* Compare masked address with the TLB entry. */ - ldst->label_ptr[0] =3D s->code_ptr; - tcg_out_opc_bne(s, TCG_REG_TMP0, TCG_REG_TMP1, 0); - - h->index =3D TCG_REG_TMP2; -#else - if (a_bits) { ldst =3D new_ldst_label(s); - ldst->is_ld =3D is_ld; ldst->oi =3D oi; ldst->addrlo_reg =3D addr_reg; =20 + tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP0, TCG_AREG0, mask_ofs); + tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, TCG_AREG0, table_ofs); + + tcg_out_opc_srli_d(s, TCG_REG_TMP2, addr_reg, + s->page_bits - CPU_TLB_ENTRY_BITS); + tcg_out_opc_and(s, TCG_REG_TMP2, TCG_REG_TMP2, TCG_REG_TMP0); + tcg_out_opc_add_d(s, TCG_REG_TMP2, TCG_REG_TMP2, TCG_REG_TMP1); + + /* Load the tlb comparator and the addend. */ + QEMU_BUILD_BUG_ON(HOST_BIG_ENDIAN); + tcg_out_ld(s, addr_type, TCG_REG_TMP0, TCG_REG_TMP2, + is_ld ? offsetof(CPUTLBEntry, addr_read) + : offsetof(CPUTLBEntry, addr_write)); + tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP2, TCG_REG_TMP2, + offsetof(CPUTLBEntry, addend)); + /* - * Without micro-architecture details, we don't know which of - * bstrpick or andi is faster, so use bstrpick as it's not - * constrained by imm field width. Not to say alignments >=3D 2^12 - * are going to happen any time soon. + * For aligned accesses, we check the first byte and include the + * alignment bits within the address. For unaligned access, we + * check that we don't cross pages using the address of the last + * byte of the access. */ - tcg_out_opc_bstrpick_d(s, TCG_REG_TMP1, addr_reg, 0, a_bits - 1); + if (a_bits < s_bits) { + unsigned a_mask =3D (1u << a_bits) - 1; + unsigned s_mask =3D (1u << s_bits) - 1; + tcg_out_addi(s, addr_type, TCG_REG_TMP1, addr_reg, s_mask - a_= mask); + } else { + tcg_out_mov(s, addr_type, TCG_REG_TMP1, addr_reg); + } + tcg_out_opc_bstrins_d(s, TCG_REG_TMP1, TCG_REG_ZERO, + a_bits, s->page_bits - 1); =20 + /* Compare masked address with the TLB entry. */ ldst->label_ptr[0] =3D s->code_ptr; - tcg_out_opc_bne(s, TCG_REG_TMP1, TCG_REG_ZERO, 0); - } + tcg_out_opc_bne(s, TCG_REG_TMP0, TCG_REG_TMP1, 0); =20 - h->index =3D USE_GUEST_BASE ? TCG_GUEST_BASE_REG : TCG_REG_ZERO; -#endif + h->index =3D TCG_REG_TMP2; + } else { + if (a_bits) { + ldst =3D new_ldst_label(s); + + ldst->is_ld =3D is_ld; + ldst->oi =3D oi; + ldst->addrlo_reg =3D addr_reg; + + /* + * Without micro-architecture details, we don't know which of + * bstrpick or andi is faster, so use bstrpick as it's not + * constrained by imm field width. Not to say alignments >=3D = 2^12 + * are going to happen any time soon. + */ + tcg_out_opc_bstrpick_d(s, TCG_REG_TMP1, addr_reg, 0, a_bits - = 1); + + ldst->label_ptr[0] =3D s->code_ptr; + tcg_out_opc_bne(s, TCG_REG_TMP1, TCG_REG_ZERO, 0); + } + + h->index =3D guest_base ? TCG_GUEST_BASE_REG : TCG_REG_ZERO; + } =20 if (addr_type =3D=3D TCG_TYPE_I32) { h->base =3D TCG_REG_TMP0; @@ -2272,12 +2270,10 @@ static void tcg_target_qemu_prologue(TCGContext *s) TCG_REG_SP, SAVE_OFS + i * REG_SIZE); } =20 -#if !defined(CONFIG_SOFTMMU) - if (USE_GUEST_BASE) { + if (!tcg_use_softmmu && guest_base) { tcg_out_movi(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base); tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG); } -#endif =20 /* Call generated code */ tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]); --=20 2.34.1 From nobody Wed Nov 27 17:32:24 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1697668141; cv=none; d=zohomail.com; s=zohoarc; b=LJFHCSC8CnBiUUKL8nqOQk0C/smxAnhjxxWutm/z1+OHvxm49jsx/1ZXDuBEDPjaiN41glSOx4B2ZnGBDCkLBq2YVf4nOD/MXfCnbjozhrhzvkTFFV+PChAuwMBLi0usVAbN3I2bbYf1QhLSzjV184PwuISqoWgPwgqUT+wP6Lw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1697668141; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=6NA4v6NXBUoR4C0a50DqS4JX4mw0CRsfvfpO9da4xso=; b=VU8Gv+UF9RFKDXJa1uDyaosctBsoO0KFHB/1+aUvdPNG+AnIP5gMiWuCMBpcwah1dHO4cIBMaK3phwnRtui4C4U/IvN0GMVb/JGHuTnnr6CO3RKVYZbypoX78j/o4+/YzdCii3dYxht7jth4zVnH8p5vTnVcL4VvLmXRH96DPxQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1697668141239139.51806783529616; Wed, 18 Oct 2023 15:29:01 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qtEzg-0008AV-BW; Wed, 18 Oct 2023 18:26:24 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qtEzc-00088z-OV for qemu-devel@nongnu.org; Wed, 18 Oct 2023 18:26:20 -0400 Received: from mail-pl1-x62b.google.com ([2607:f8b0:4864:20::62b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qtEza-0002Ve-Hv for qemu-devel@nongnu.org; Wed, 18 Oct 2023 18:26:20 -0400 Received: by mail-pl1-x62b.google.com with SMTP id d9443c01a7336-1c9d3a21f7aso59739085ad.2 for ; Wed, 18 Oct 2023 15:26:18 -0700 (PDT) Received: from stoup.. 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697668142765100005 Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- tcg/mips/tcg-target.c.inc | 231 +++++++++++++++++++------------------- 1 file changed, 113 insertions(+), 118 deletions(-) diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index e2892edc6a..328984ccff 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -78,13 +78,11 @@ static const char * const tcg_target_reg_names[TCG_TARG= ET_NB_REGS] =3D { #define TCG_TMP2 TCG_REG_T8 #define TCG_TMP3 TCG_REG_T7 =20 -#ifndef CONFIG_SOFTMMU #define TCG_GUEST_BASE_REG TCG_REG_S7 -#endif #if TCG_TARGET_REG_BITS =3D=3D 64 #define TCG_REG_TB TCG_REG_S6 #else -#define TCG_REG_TB (qemu_build_not_reached(), TCG_REG_ZERO) +#define TCG_REG_TB ({ qemu_build_not_reached(); TCG_REG_ZERO; }) #endif =20 /* check if we really need so many registers :P */ @@ -1279,130 +1277,129 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGCon= text *s, HostAddress *h, a_bits =3D h->aa.align; a_mask =3D (1 << a_bits) - 1; =20 -#ifdef CONFIG_SOFTMMU - unsigned s_mask =3D (1 << s_bits) - 1; - int mem_index =3D get_mmuidx(oi); - int fast_off =3D tlb_mask_table_ofs(s, mem_index); - int mask_off =3D fast_off + offsetof(CPUTLBDescFast, mask); - int table_off =3D fast_off + offsetof(CPUTLBDescFast, table); - int add_off =3D offsetof(CPUTLBEntry, addend); - int cmp_off =3D is_ld ? offsetof(CPUTLBEntry, addr_read) - : offsetof(CPUTLBEntry, addr_write); + if (tcg_use_softmmu) { + unsigned s_mask =3D (1 << s_bits) - 1; + int mem_index =3D get_mmuidx(oi); + int fast_off =3D tlb_mask_table_ofs(s, mem_index); + int mask_off =3D fast_off + offsetof(CPUTLBDescFast, mask); + int table_off =3D fast_off + offsetof(CPUTLBDescFast, table); + int add_off =3D offsetof(CPUTLBEntry, addend); + int cmp_off =3D is_ld ? offsetof(CPUTLBEntry, addr_read) + : offsetof(CPUTLBEntry, addr_write); =20 - ldst =3D new_ldst_label(s); - ldst->is_ld =3D is_ld; - ldst->oi =3D oi; - ldst->addrlo_reg =3D addrlo; - ldst->addrhi_reg =3D addrhi; - - /* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */ - tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP0, TCG_AREG0, mask_off); - tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP1, TCG_AREG0, table_off); - - /* Extract the TLB index from the address into TMP3. */ - if (TCG_TARGET_REG_BITS =3D=3D 32 || addr_type =3D=3D TCG_TYPE_I32) { - tcg_out_opc_sa(s, OPC_SRL, TCG_TMP3, addrlo, - s->page_bits - CPU_TLB_ENTRY_BITS); - } else { - tcg_out_dsrl(s, TCG_TMP3, addrlo, - s->page_bits - CPU_TLB_ENTRY_BITS); - } - tcg_out_opc_reg(s, OPC_AND, TCG_TMP3, TCG_TMP3, TCG_TMP0); - - /* Add the tlb_table pointer, creating the CPUTLBEntry address in TMP3= . */ - tcg_out_opc_reg(s, ALIAS_PADD, TCG_TMP3, TCG_TMP3, TCG_TMP1); - - if (TCG_TARGET_REG_BITS =3D=3D 32 || addr_type =3D=3D TCG_TYPE_I32) { - /* Load the (low half) tlb comparator. */ - tcg_out_ld(s, TCG_TYPE_I32, TCG_TMP0, TCG_TMP3, - cmp_off + HOST_BIG_ENDIAN * 4); - } else { - tcg_out_ld(s, TCG_TYPE_I64, TCG_TMP0, TCG_TMP3, cmp_off); - } - - if (TCG_TARGET_REG_BITS =3D=3D 64 || addr_type =3D=3D TCG_TYPE_I32) { - /* Load the tlb addend for the fast path. */ - tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP3, TCG_TMP3, add_off); - } - - /* - * Mask the page bits, keeping the alignment bits to compare against. - * For unaligned accesses, compare against the end of the access to - * verify that it does not cross a page boundary. - */ - tcg_out_movi(s, addr_type, TCG_TMP1, s->page_mask | a_mask); - if (a_mask < s_mask) { - if (TCG_TARGET_REG_BITS =3D=3D 32 || addr_type =3D=3D TCG_TYPE_I32= ) { - tcg_out_opc_imm(s, OPC_ADDIU, TCG_TMP2, addrlo, s_mask - a_mas= k); - } else { - tcg_out_opc_imm(s, OPC_DADDIU, TCG_TMP2, addrlo, s_mask - a_ma= sk); - } - tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, TCG_TMP2); - } else { - tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, addrlo); - } - - /* Zero extend a 32-bit guest address for a 64-bit host. */ - if (TCG_TARGET_REG_BITS =3D=3D 64 && addr_type =3D=3D TCG_TYPE_I32) { - tcg_out_ext32u(s, TCG_TMP2, addrlo); - addrlo =3D TCG_TMP2; - } - - ldst->label_ptr[0] =3D s->code_ptr; - tcg_out_opc_br(s, OPC_BNE, TCG_TMP1, TCG_TMP0); - - /* Load and test the high half tlb comparator. */ - if (TCG_TARGET_REG_BITS =3D=3D 32 && addr_type !=3D TCG_TYPE_I32) { - /* delay slot */ - tcg_out_ldst(s, OPC_LW, TCG_TMP0, TCG_TMP3, cmp_off + HI_OFF); - - /* Load the tlb addend for the fast path. */ - tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP3, TCG_TMP3, add_off); - - ldst->label_ptr[1] =3D s->code_ptr; - tcg_out_opc_br(s, OPC_BNE, addrhi, TCG_TMP0); - } - - /* delay slot */ - base =3D TCG_TMP3; - tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_TMP3, addrlo); -#else - if (a_mask && (use_mips32r6_instructions || a_bits !=3D s_bits)) { ldst =3D new_ldst_label(s); - ldst->is_ld =3D is_ld; ldst->oi =3D oi; ldst->addrlo_reg =3D addrlo; ldst->addrhi_reg =3D addrhi; =20 - /* We are expecting a_bits to max out at 7, much lower than ANDI. = */ - tcg_debug_assert(a_bits < 16); - tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP0, addrlo, a_mask); + /* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */ + tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP0, TCG_AREG0, mask_off); + tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP1, TCG_AREG0, table_off); + + /* Extract the TLB index from the address into TMP3. */ + if (TCG_TARGET_REG_BITS =3D=3D 32 || addr_type =3D=3D TCG_TYPE_I32= ) { + tcg_out_opc_sa(s, OPC_SRL, TCG_TMP3, addrlo, + s->page_bits - CPU_TLB_ENTRY_BITS); + } else { + tcg_out_dsrl(s, TCG_TMP3, addrlo, + s->page_bits - CPU_TLB_ENTRY_BITS); + } + tcg_out_opc_reg(s, OPC_AND, TCG_TMP3, TCG_TMP3, TCG_TMP0); + + /* Add the tlb_table pointer, creating the CPUTLBEntry address. */ + tcg_out_opc_reg(s, ALIAS_PADD, TCG_TMP3, TCG_TMP3, TCG_TMP1); + + if (TCG_TARGET_REG_BITS =3D=3D 32 || addr_type =3D=3D TCG_TYPE_I32= ) { + /* Load the (low half) tlb comparator. */ + tcg_out_ld(s, TCG_TYPE_I32, TCG_TMP0, TCG_TMP3, + cmp_off + HOST_BIG_ENDIAN * 4); + } else { + tcg_out_ld(s, TCG_TYPE_I64, TCG_TMP0, TCG_TMP3, cmp_off); + } + + if (TCG_TARGET_REG_BITS =3D=3D 64 || addr_type =3D=3D TCG_TYPE_I32= ) { + /* Load the tlb addend for the fast path. */ + tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP3, TCG_TMP3, add_off); + } + + /* + * Mask the page bits, keeping the alignment bits to compare again= st. + * For unaligned accesses, compare against the end of the access to + * verify that it does not cross a page boundary. + */ + tcg_out_movi(s, addr_type, TCG_TMP1, s->page_mask | a_mask); + if (a_mask < s_mask) { + tcg_out_opc_imm(s, (TCG_TARGET_REG_BITS =3D=3D 32 + || addr_type =3D=3D TCG_TYPE_I32 + ? OPC_ADDIU : OPC_DADDIU), + TCG_TMP2, addrlo, s_mask - a_mask); + tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, TCG_TMP2); + } else { + tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, addrlo); + } + + /* Zero extend a 32-bit guest address for a 64-bit host. */ + if (TCG_TARGET_REG_BITS =3D=3D 64 && addr_type =3D=3D TCG_TYPE_I32= ) { + tcg_out_ext32u(s, TCG_TMP2, addrlo); + addrlo =3D TCG_TMP2; + } =20 ldst->label_ptr[0] =3D s->code_ptr; - if (use_mips32r6_instructions) { - tcg_out_opc_br(s, OPC_BNEZALC_R6, TCG_REG_ZERO, TCG_TMP0); - } else { - tcg_out_opc_br(s, OPC_BNEL, TCG_TMP0, TCG_REG_ZERO); - tcg_out_nop(s); - } - } + tcg_out_opc_br(s, OPC_BNE, TCG_TMP1, TCG_TMP0); =20 - base =3D addrlo; - if (TCG_TARGET_REG_BITS =3D=3D 64 && addr_type =3D=3D TCG_TYPE_I32) { - tcg_out_ext32u(s, TCG_REG_A0, base); - base =3D TCG_REG_A0; - } - if (guest_base) { - if (guest_base =3D=3D (int16_t)guest_base) { - tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_A0, base, guest_base); - } else { - tcg_out_opc_reg(s, ALIAS_PADD, TCG_REG_A0, base, - TCG_GUEST_BASE_REG); + /* Load and test the high half tlb comparator. */ + if (TCG_TARGET_REG_BITS =3D=3D 32 && addr_type !=3D TCG_TYPE_I32) { + /* delay slot */ + tcg_out_ldst(s, OPC_LW, TCG_TMP0, TCG_TMP3, cmp_off + HI_OFF); + + /* Load the tlb addend for the fast path. */ + tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP3, TCG_TMP3, add_off); + + ldst->label_ptr[1] =3D s->code_ptr; + tcg_out_opc_br(s, OPC_BNE, addrhi, TCG_TMP0); + } + + /* delay slot */ + base =3D TCG_TMP3; + tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_TMP3, addrlo); + } else { + if (a_mask && (use_mips32r6_instructions || a_bits !=3D s_bits)) { + ldst =3D new_ldst_label(s); + + ldst->is_ld =3D is_ld; + ldst->oi =3D oi; + ldst->addrlo_reg =3D addrlo; + ldst->addrhi_reg =3D addrhi; + + /* We are expecting a_bits to max out at 7, much lower than AN= DI. */ + tcg_debug_assert(a_bits < 16); + tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP0, addrlo, a_mask); + + ldst->label_ptr[0] =3D s->code_ptr; + if (use_mips32r6_instructions) { + tcg_out_opc_br(s, OPC_BNEZALC_R6, TCG_REG_ZERO, TCG_TMP0); + } else { + tcg_out_opc_br(s, OPC_BNEL, TCG_TMP0, TCG_REG_ZERO); + tcg_out_nop(s); + } + } + + base =3D addrlo; + if (TCG_TARGET_REG_BITS =3D=3D 64 && addr_type =3D=3D TCG_TYPE_I32= ) { + tcg_out_ext32u(s, TCG_REG_A0, base); + base =3D TCG_REG_A0; + } + if (guest_base) { + if (guest_base =3D=3D (int16_t)guest_base) { + tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_A0, base, guest_ba= se); + } else { + tcg_out_opc_reg(s, ALIAS_PADD, TCG_REG_A0, base, + TCG_GUEST_BASE_REG); + } + base =3D TCG_REG_A0; } - base =3D TCG_REG_A0; } -#endif =20 h->base =3D base; return ldst; @@ -2465,8 +2462,7 @@ static void tcg_target_qemu_prologue(TCGContext *s) TCG_REG_SP, SAVE_OFS + i * REG_SIZE); } =20 -#ifndef CONFIG_SOFTMMU - if (guest_base !=3D (int16_t)guest_base) { + if (!tcg_use_softmmu && guest_base !=3D (int16_t)guest_base) { /* * The function call abi for n32 and n64 will have loaded $25 (t9) * with the address of the prologue, so we can use that instead @@ -2479,7 +2475,6 @@ static void tcg_target_qemu_prologue(TCGContext *s) TCG_TARGET_REG_BITS =3D=3D 64 ? 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id 13-20020a170902c24d00b001b9d95945afsm431058plg.155.2023.10.18.15.26.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Oct 2023 15:26:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1697667978; x=1698272778; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=UPfL8PRDqxISdNKDDtEx7VkZ1IZG1ok5c8lkQqcFV18=; b=nv45LMkj3nvKFeD/KeVrxDVZ8scU0bT2WnsDSZm3x9AiBkmNHLNTCO1nyTsZr7ofF4 PCsMHV5In7WPTN7JrPtlpzybQYNtRU8Lsk0eeOOczzbAP3UMDTqJHcOinxCdZsZ/zP9w K5q+e8pq4j55HFR2avJjyPpeUUyADDNxaW4rVpduTWhwhg5w7B4zPOIowo69WLGWViOO FjYb7acIRpUR43gU4gGoQ2rZW0ZvTA2K39lv+44+w2u71mOaNkHSRv3yF7eYxhZZd1od blTpE7bhFChujb8xL3dINd9W5iHPiUKA7MCP70dyUEW+Xg8kHYIL2xX5dAHwwBMW0QgY NM9Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697667978; x=1698272778; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=UPfL8PRDqxISdNKDDtEx7VkZ1IZG1ok5c8lkQqcFV18=; b=ofKaj5MutOgs6Wei/TrknjwJEtP7l44fV0kzwT0/5n+YKPZCQq7Yb9rAN1Hqph6GYX ylUvsUrlCi5pBA9ZpTA9TmE17aYcONlG30DoJ0HqtcwbLqOPZP5QpYAVzOUnbvX8SQRv 5CrM0WQPT2fZmizfESK85jbU+akfniMKy/je4dkFRxHTNEc64ZVqnuzS2P6MAucusre7 f2cPwVNM9zo3UuGMxJQIrev0jZQR6OC5BWe4p6GlitSxRgdsP1NbIddeqWRNPTDPAXPD NTNzFnTk0nWnT8gCcDmuKrdikkkNpMaJt6bzlzzWeebrL3KG/yoMwGMVW8JRWhMjpfQ5 pb/g== X-Gm-Message-State: AOJu0YyJVERyKK3LK89316MhH1AppQW+C+FYmCHap0PW/Exz4RMnf/Rd SNWQme1TmKqeRy09xe/BlqZfHkzAnLgO9V3Ee7g= X-Google-Smtp-Source: AGHT+IHPV7SuLyfkXVDkpXji0HSihakDyhhnyzJjtIwHOcXxy+Sp7qxNhqG5xA7mDBHdLwSaZkcMMA== X-Received: by 2002:a17:902:e5c3:b0:1ca:3e40:beae with SMTP id u3-20020a170902e5c300b001ca3e40beaemr742366plf.38.1697667977950; Wed, 18 Oct 2023 15:26:17 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 21/29] tcg/ppc: Use tcg_use_softmmu Date: Wed, 18 Oct 2023 15:25:49 -0700 Message-Id: <20231018222557.1562065-22-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231018222557.1562065-1-richard.henderson@linaro.org> References: <20231018222557.1562065-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697668361725100010 Fix TCG_GUEST_BASE_REG to use 'TCG_REG_R30' instead of '30'. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target.c.inc | 284 ++++++++++++++++++++------------------- 1 file changed, 143 insertions(+), 141 deletions(-) diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index c31da4da9d..856c3b18f5 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -107,9 +107,7 @@ =20 #define have_isel (cpuinfo & CPUINFO_ISEL) =20 -#ifndef CONFIG_SOFTMMU -#define TCG_GUEST_BASE_REG 30 -#endif +#define TCG_GUEST_BASE_REG TCG_REG_R30 =20 #ifdef CONFIG_DEBUG_TCG static const char tcg_target_reg_names[TCG_TARGET_NB_REGS][4] =3D { @@ -2317,151 +2315,157 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGCon= text *s, HostAddress *h, s_bits =3D=3D MO_128); a_bits =3D h->aa.align; =20 -#ifdef CONFIG_SOFTMMU - int mem_index =3D get_mmuidx(oi); - int cmp_off =3D is_ld ? offsetof(CPUTLBEntry, addr_read) - : offsetof(CPUTLBEntry, addr_write); - int fast_off =3D tlb_mask_table_ofs(s, mem_index); - int mask_off =3D fast_off + offsetof(CPUTLBDescFast, mask); - int table_off =3D fast_off + offsetof(CPUTLBDescFast, table); + if (tcg_use_softmmu) { + int mem_index =3D get_mmuidx(oi); + int cmp_off =3D is_ld ? offsetof(CPUTLBEntry, addr_read) + : offsetof(CPUTLBEntry, addr_write); + int fast_off =3D tlb_mask_table_ofs(s, mem_index); + int mask_off =3D fast_off + offsetof(CPUTLBDescFast, mask); + int table_off =3D fast_off + offsetof(CPUTLBDescFast, table); =20 - ldst =3D new_ldst_label(s); - ldst->is_ld =3D is_ld; - ldst->oi =3D oi; - ldst->addrlo_reg =3D addrlo; - ldst->addrhi_reg =3D addrhi; - - /* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */ - tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, TCG_AREG0, mask_off); - tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP2, TCG_AREG0, table_off); - - /* Extract the page index, shifted into place for tlb index. */ - if (TCG_TARGET_REG_BITS =3D=3D 32) { - tcg_out_shri32(s, TCG_REG_R0, addrlo, - s->page_bits - CPU_TLB_ENTRY_BITS); - } else { - tcg_out_shri64(s, TCG_REG_R0, addrlo, - s->page_bits - CPU_TLB_ENTRY_BITS); - } - tcg_out32(s, AND | SAB(TCG_REG_TMP1, TCG_REG_TMP1, TCG_REG_R0)); - - /* - * Load the (low part) TLB comparator into TMP2. - * For 64-bit host, always load the entire 64-bit slot for simplicity. - * We will ignore the high bits with tcg_out_cmp(..., addr_type). - */ - if (TCG_TARGET_REG_BITS =3D=3D 64) { - if (cmp_off =3D=3D 0) { - tcg_out32(s, LDUX | TAB(TCG_REG_TMP2, TCG_REG_TMP1, TCG_REG_TM= P2)); - } else { - tcg_out32(s, ADD | TAB(TCG_REG_TMP1, TCG_REG_TMP1, TCG_REG_TMP= 2)); - tcg_out_ld(s, TCG_TYPE_I64, TCG_REG_TMP2, TCG_REG_TMP1, cmp_of= f); - } - } else if (cmp_off =3D=3D 0 && !HOST_BIG_ENDIAN) { - tcg_out32(s, LWZUX | TAB(TCG_REG_TMP2, TCG_REG_TMP1, TCG_REG_TMP2)= ); - } else { - tcg_out32(s, ADD | TAB(TCG_REG_TMP1, TCG_REG_TMP1, TCG_REG_TMP2)); - tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_TMP2, TCG_REG_TMP1, - cmp_off + 4 * HOST_BIG_ENDIAN); - } - - /* - * Load the TLB addend for use on the fast path. - * Do this asap to minimize any load use delay. - */ - if (TCG_TARGET_REG_BITS =3D=3D 64 || addr_type =3D=3D TCG_TYPE_I32) { - tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, TCG_REG_TMP1, - offsetof(CPUTLBEntry, addend)); - } - - /* Clear the non-page, non-alignment bits from the address in R0. */ - if (TCG_TARGET_REG_BITS =3D=3D 32) { - /* - * We don't support unaligned accesses on 32-bits. - * Preserve the bottom bits and thus trigger a comparison - * failure on unaligned accesses. - */ - if (a_bits < s_bits) { - a_bits =3D s_bits; - } - tcg_out_rlw(s, RLWINM, TCG_REG_R0, addrlo, 0, - (32 - a_bits) & 31, 31 - s->page_bits); - } else { - TCGReg t =3D addrlo; - - /* - * If the access is unaligned, we need to make sure we fail if we - * cross a page boundary. The trick is to add the access size-1 - * to the address before masking the low bits. That will make the - * address overflow to the next page if we cross a page boundary, - * which will then force a mismatch of the TLB compare. - */ - if (a_bits < s_bits) { - unsigned a_mask =3D (1 << a_bits) - 1; - unsigned s_mask =3D (1 << s_bits) - 1; - tcg_out32(s, ADDI | TAI(TCG_REG_R0, t, s_mask - a_mask)); - t =3D TCG_REG_R0; - } - - /* Mask the address for the requested alignment. */ - if (addr_type =3D=3D TCG_TYPE_I32) { - tcg_out_rlw(s, RLWINM, TCG_REG_R0, t, 0, - (32 - a_bits) & 31, 31 - s->page_bits); - } else if (a_bits =3D=3D 0) { - tcg_out_rld(s, RLDICR, TCG_REG_R0, t, 0, 63 - s->page_bits); - } else { - tcg_out_rld(s, RLDICL, TCG_REG_R0, t, - 64 - s->page_bits, s->page_bits - a_bits); - tcg_out_rld(s, RLDICL, TCG_REG_R0, TCG_REG_R0, s->page_bits, 0= ); - } - } - - if (TCG_TARGET_REG_BITS =3D=3D 32 && addr_type !=3D TCG_TYPE_I32) { - /* Low part comparison into cr7. */ - tcg_out_cmp(s, TCG_COND_EQ, TCG_REG_R0, TCG_REG_TMP2, - 0, 7, TCG_TYPE_I32); - - /* Load the high part TLB comparator into TMP2. */ - tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_TMP2, TCG_REG_TMP1, - cmp_off + 4 * !HOST_BIG_ENDIAN); - - /* Load addend, deferred for this case. */ - tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, TCG_REG_TMP1, - offsetof(CPUTLBEntry, addend)); - - /* High part comparison into cr6. */ - tcg_out_cmp(s, TCG_COND_EQ, addrhi, TCG_REG_TMP2, 0, 6, TCG_TYPE_I= 32); - - /* Combine comparisons into cr7. */ - tcg_out32(s, CRAND | BT(7, CR_EQ) | BA(6, CR_EQ) | BB(7, CR_EQ)); - } else { - /* Full comparison into cr7. */ - tcg_out_cmp(s, TCG_COND_EQ, TCG_REG_R0, TCG_REG_TMP2, 0, 7, addr_t= ype); - } - - /* Load a pointer into the current opcode w/conditional branch-link. */ - ldst->label_ptr[0] =3D s->code_ptr; - tcg_out32(s, BC | BI(7, CR_EQ) | BO_COND_FALSE | LK); - - h->base =3D TCG_REG_TMP1; -#else - if (a_bits) { ldst =3D new_ldst_label(s); ldst->is_ld =3D is_ld; ldst->oi =3D oi; ldst->addrlo_reg =3D addrlo; ldst->addrhi_reg =3D addrhi; =20 - /* We are expecting a_bits to max out at 7, much lower than ANDI. = */ - tcg_debug_assert(a_bits < 16); - tcg_out32(s, ANDI | SAI(addrlo, TCG_REG_R0, (1 << a_bits) - 1)); + /* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */ + tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, TCG_AREG0, mask_off); + tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP2, TCG_AREG0, table_off); =20 + /* Extract the page index, shifted into place for tlb index. */ + if (TCG_TARGET_REG_BITS =3D=3D 32) { + tcg_out_shri32(s, TCG_REG_R0, addrlo, + s->page_bits - CPU_TLB_ENTRY_BITS); + } else { + tcg_out_shri64(s, TCG_REG_R0, addrlo, + s->page_bits - CPU_TLB_ENTRY_BITS); + } + tcg_out32(s, AND | SAB(TCG_REG_TMP1, TCG_REG_TMP1, TCG_REG_R0)); + + /* + * Load the (low part) TLB comparator into TMP2. + * For 64-bit host, always load the entire 64-bit slot for simplic= ity. + * We will ignore the high bits with tcg_out_cmp(..., addr_type). + */ + if (TCG_TARGET_REG_BITS =3D=3D 64) { + if (cmp_off =3D=3D 0) { + tcg_out32(s, LDUX | TAB(TCG_REG_TMP2, + TCG_REG_TMP1, TCG_REG_TMP2)); + } else { + tcg_out32(s, ADD | TAB(TCG_REG_TMP1, + TCG_REG_TMP1, TCG_REG_TMP2)); + tcg_out_ld(s, TCG_TYPE_I64, TCG_REG_TMP2, + TCG_REG_TMP1, cmp_off); + } + } else if (cmp_off =3D=3D 0 && !HOST_BIG_ENDIAN) { + tcg_out32(s, LWZUX | TAB(TCG_REG_TMP2, + TCG_REG_TMP1, TCG_REG_TMP2)); + } else { + tcg_out32(s, ADD | TAB(TCG_REG_TMP1, TCG_REG_TMP1, TCG_REG_TMP= 2)); + tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_TMP2, TCG_REG_TMP1, + cmp_off + 4 * HOST_BIG_ENDIAN); + } + + /* + * Load the TLB addend for use on the fast path. + * Do this asap to minimize any load use delay. + */ + if (TCG_TARGET_REG_BITS =3D=3D 64 || addr_type =3D=3D TCG_TYPE_I32= ) { + tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, TCG_REG_TMP1, + offsetof(CPUTLBEntry, addend)); + } + + /* Clear the non-page, non-alignment bits from the address in R0. = */ + if (TCG_TARGET_REG_BITS =3D=3D 32) { + /* + * We don't support unaligned accesses on 32-bits. + * Preserve the bottom bits and thus trigger a comparison + * failure on unaligned accesses. + */ + if (a_bits < s_bits) { + a_bits =3D s_bits; + } + tcg_out_rlw(s, RLWINM, TCG_REG_R0, addrlo, 0, + (32 - a_bits) & 31, 31 - s->page_bits); + } else { + TCGReg t =3D addrlo; + + /* + * If the access is unaligned, we need to make sure we fail if= we + * cross a page boundary. The trick is to add the access size= -1 + * to the address before masking the low bits. That will make= the + * address overflow to the next page if we cross a page bounda= ry, + * which will then force a mismatch of the TLB compare. + */ + if (a_bits < s_bits) { + unsigned a_mask =3D (1 << a_bits) - 1; + unsigned s_mask =3D (1 << s_bits) - 1; + tcg_out32(s, ADDI | TAI(TCG_REG_R0, t, s_mask - a_mask)); + t =3D TCG_REG_R0; + } + + /* Mask the address for the requested alignment. */ + if (addr_type =3D=3D TCG_TYPE_I32) { + tcg_out_rlw(s, RLWINM, TCG_REG_R0, t, 0, + (32 - a_bits) & 31, 31 - s->page_bits); + } else if (a_bits =3D=3D 0) { + tcg_out_rld(s, RLDICR, TCG_REG_R0, t, 0, 63 - s->page_bits= ); + } else { + tcg_out_rld(s, RLDICL, TCG_REG_R0, t, + 64 - s->page_bits, s->page_bits - a_bits); + tcg_out_rld(s, RLDICL, TCG_REG_R0, TCG_REG_R0, s->page_bit= s, 0); + } + } + + if (TCG_TARGET_REG_BITS =3D=3D 32 && addr_type !=3D TCG_TYPE_I32) { + /* Low part comparison into cr7. */ + tcg_out_cmp(s, TCG_COND_EQ, TCG_REG_R0, TCG_REG_TMP2, + 0, 7, TCG_TYPE_I32); + + /* Load the high part TLB comparator into TMP2. */ + tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_TMP2, TCG_REG_TMP1, + cmp_off + 4 * !HOST_BIG_ENDIAN); + + /* Load addend, deferred for this case. */ + tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, TCG_REG_TMP1, + offsetof(CPUTLBEntry, addend)); + + /* High part comparison into cr6. */ + tcg_out_cmp(s, TCG_COND_EQ, addrhi, TCG_REG_TMP2, + 0, 6, TCG_TYPE_I32); + + /* Combine comparisons into cr7. */ + tcg_out32(s, CRAND | BT(7, CR_EQ) | BA(6, CR_EQ) | BB(7, CR_EQ= )); + } else { + /* Full comparison into cr7. */ + tcg_out_cmp(s, TCG_COND_EQ, TCG_REG_R0, TCG_REG_TMP2, + 0, 7, addr_type); + } + + /* Load a pointer into the current opcode w/conditional branch-lin= k. */ ldst->label_ptr[0] =3D s->code_ptr; - tcg_out32(s, BC | BI(0, CR_EQ) | BO_COND_FALSE | LK); - } + tcg_out32(s, BC | BI(7, CR_EQ) | BO_COND_FALSE | LK); =20 - h->base =3D guest_base ? TCG_GUEST_BASE_REG : 0; -#endif + h->base =3D TCG_REG_TMP1; + } else { + if (a_bits) { + ldst =3D new_ldst_label(s); + ldst->is_ld =3D is_ld; + ldst->oi =3D oi; + ldst->addrlo_reg =3D addrlo; + ldst->addrhi_reg =3D addrhi; + + /* We are expecting a_bits to max out at 7, much lower than AN= DI. */ + tcg_debug_assert(a_bits < 16); + tcg_out32(s, ANDI | SAI(addrlo, TCG_REG_R0, (1 << a_bits) - 1)= ); + + ldst->label_ptr[0] =3D s->code_ptr; + tcg_out32(s, BC | BI(0, CR_EQ) | BO_COND_FALSE | LK); + } + + h->base =3D guest_base ? TCG_GUEST_BASE_REG : 0; + } =20 if (TCG_TARGET_REG_BITS =3D=3D 64 && addr_type =3D=3D TCG_TYPE_I32) { /* Zero-extend the guest address for use in the host address. */ @@ -2695,12 +2699,10 @@ static void tcg_target_qemu_prologue(TCGContext *s) } tcg_out_st(s, TCG_TYPE_PTR, TCG_REG_R0, TCG_REG_R1, FRAME_SIZE+LR_OFFS= ET); =20 -#ifndef CONFIG_SOFTMMU - if (guest_base) { + if (!tcg_use_softmmu && guest_base) { tcg_out_movi_int(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base, = true); tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG); } -#endif =20 tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]); tcg_out32(s, MTSPR | RS(tcg_target_call_iarg_regs[1]) | CTR); --=20 2.34.1 From nobody Wed Nov 27 17:32:24 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1697668175; cv=none; d=zohomail.com; s=zohoarc; b=ANmU1hA3qTy0+hFP+LrzEnvw2MkEZvB3bC4wcPG+MKMU6rTf6bUeBmLAczeehDjaOSaZEP+aS9G48a5QTFHW6TaTMrjjPrC0p1BP53f/Vfg+Z4/EIT9zAMpIhO95PEIkrzk8cnd45MPbpdUcQePxZNPhrq5lh+iDmO8IFo6HbJY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1697668175; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=Gscgf9TaNURfjEVsbC8XIQGIbXkPOrKC3iA1FwA6PsE=; b=QZ87sRMAZuvuym89wF1L9supvRc8BKlyFONiAdZmG6oCLJQdOpcfglfegAoScaptNpF/Cu23gHXxTGrCWy6RNR5oLT1/5RpdbHADG+8f6WsjrhKdoMotrZmu7uOR9hEAoghqNtObEe2B8uo+SgLv4Iz5B38qrvwPwNel8i4x4oA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1697668175749271.35644284953344; Wed, 18 Oct 2023 15:29:35 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qtEzh-0008By-Pb; Wed, 18 Oct 2023 18:26:25 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qtEze-00089U-Om for qemu-devel@nongnu.org; Wed, 18 Oct 2023 18:26:22 -0400 Received: from mail-pl1-x62f.google.com ([2607:f8b0:4864:20::62f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qtEzb-0002W0-V1 for qemu-devel@nongnu.org; Wed, 18 Oct 2023 18:26:21 -0400 Received: by mail-pl1-x62f.google.com with SMTP id d9443c01a7336-1ca6809fb8aso27745355ad.1 for ; Wed, 18 Oct 2023 15:26:19 -0700 (PDT) Received: from stoup.. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697668176830100001 Content-Type: text/plain; charset="utf-8" Fixes: 92c041c59b ("tcg/riscv: Add the prologue generation and register the= JIT") Signed-off-by: Richard Henderson --- tcg/riscv/tcg-target.c.inc | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index d6dbcaf3cb..dc71f829d1 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -2076,8 +2076,10 @@ static void tcg_target_qemu_prologue(TCGContext *s) } =20 #if !defined(CONFIG_SOFTMMU) - tcg_out_movi(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base); - tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG); + if (guest_base) { + tcg_out_movi(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base); + tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG); + } #endif =20 /* Call generated code */ --=20 2.34.1 From nobody Wed Nov 27 17:32:24 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1697668364; cv=none; d=zohomail.com; s=zohoarc; b=WFSA7ereqgOtUlnsYADf+Alav/sWV7qfyT2NaWhWhOUKhiQWYTiXHKsZ1FtCT5D/EqrTjAwBLnmxyFhgusI0aY93RXXomttU/U2a3l/+XF7pEn6W9/FX8umDxdt/YpAcq1xsEpl6MPNvCdGq+D/tdkdHWQ1TTojp70fCjJMsd8A= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1697668364; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id 13-20020a170902c24d00b001b9d95945afsm431058plg.155.2023.10.18.15.26.18 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Oct 2023 15:26:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1697667979; x=1698272779; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=JvjLY5SZ74SJJZ4Z/bCpNskQetGcwIwHRaw0bsKKJdY=; b=pAnPQLJDqUNvHB+i5d86GjO8/IL2YL95hgDtq2iTSxvPH4TNAjW+kg9iY5QFN0KbJ6 VBk61h88RpIiPLhEQ2leEr32t0zc36sZnsZ3kySQ6QgMUAmoQcmnnLhH+Cb3YbSHQ0JD IzLoOh58ThmRl+SH5JGBOIQBPU4nPi/dRjGsJ94ubCNDnB7+f/pRAlrUR1sLIQ8ctdmm XJr6s2E0UskU3zIWta49wWP0ARTqPrU1/E/vXzpVWedyNuX4wviSf7TzRTDSzIDMoX7z P0oG34nrBEAc+IWt/SsdjxzXC/V5VVtnqUJNNlv7FAbqM6wo7jmsWhwuVFjCh7njNI2L IHgw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697667979; x=1698272779; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697668365696100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/riscv/tcg-target.c.inc | 185 +++++++++++++++++++------------------ 1 file changed, 94 insertions(+), 91 deletions(-) diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index dc71f829d1..34e10e77d9 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -1245,105 +1245,110 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGCon= text *s, TCGReg *pbase, aa =3D atom_and_align_for_opc(s, opc, MO_ATOM_IFALIGN, false); a_mask =3D (1u << aa.align) - 1; =20 -#ifdef CONFIG_SOFTMMU - unsigned s_bits =3D opc & MO_SIZE; - unsigned s_mask =3D (1u << s_bits) - 1; - int mem_index =3D get_mmuidx(oi); - int fast_ofs =3D tlb_mask_table_ofs(s, mem_index); - int mask_ofs =3D fast_ofs + offsetof(CPUTLBDescFast, mask); - int table_ofs =3D fast_ofs + offsetof(CPUTLBDescFast, table); - int compare_mask; - TCGReg addr_adj; + if (tcg_use_softmmu) { + unsigned s_bits =3D opc & MO_SIZE; + unsigned s_mask =3D (1u << s_bits) - 1; + int mem_index =3D get_mmuidx(oi); + int fast_ofs =3D tlb_mask_table_ofs(s, mem_index); + int mask_ofs =3D fast_ofs + offsetof(CPUTLBDescFast, mask); + int table_ofs =3D fast_ofs + offsetof(CPUTLBDescFast, table); + int compare_mask; + TCGReg addr_adj; =20 - ldst =3D new_ldst_label(s); - ldst->is_ld =3D is_ld; - ldst->oi =3D oi; - ldst->addrlo_reg =3D addr_reg; - - tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP0, TCG_AREG0, mask_ofs); - tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, TCG_AREG0, table_ofs); - - tcg_out_opc_imm(s, OPC_SRLI, TCG_REG_TMP2, addr_reg, - s->page_bits - CPU_TLB_ENTRY_BITS); - tcg_out_opc_reg(s, OPC_AND, TCG_REG_TMP2, TCG_REG_TMP2, TCG_REG_TMP0); - tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP2, TCG_REG_TMP2, TCG_REG_TMP1); - - /* - * For aligned accesses, we check the first byte and include the align= ment - * bits within the address. For unaligned access, we check that we do= n't - * cross pages using the address of the last byte of the access. - */ - addr_adj =3D addr_reg; - if (a_mask < s_mask) { - addr_adj =3D TCG_REG_TMP0; - tcg_out_opc_imm(s, addr_type =3D=3D TCG_TYPE_I32 ? OPC_ADDIW : OPC= _ADDI, - addr_adj, addr_reg, s_mask - a_mask); - } - compare_mask =3D s->page_mask | a_mask; - if (compare_mask =3D=3D sextreg(compare_mask, 0, 12)) { - tcg_out_opc_imm(s, OPC_ANDI, TCG_REG_TMP1, addr_adj, compare_mask); - } else { - tcg_out_movi(s, addr_type, TCG_REG_TMP1, compare_mask); - tcg_out_opc_reg(s, OPC_AND, TCG_REG_TMP1, TCG_REG_TMP1, addr_adj); - } - - /* Load the tlb comparator and the addend. */ - QEMU_BUILD_BUG_ON(HOST_BIG_ENDIAN); - tcg_out_ld(s, addr_type, TCG_REG_TMP0, TCG_REG_TMP2, - is_ld ? offsetof(CPUTLBEntry, addr_read) - : offsetof(CPUTLBEntry, addr_write)); - tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP2, TCG_REG_TMP2, - offsetof(CPUTLBEntry, addend)); - - /* Compare masked address with the TLB entry. */ - ldst->label_ptr[0] =3D s->code_ptr; - tcg_out_opc_branch(s, OPC_BNE, TCG_REG_TMP0, TCG_REG_TMP1, 0); - - /* TLB Hit - translate address using addend. */ - if (addr_type !=3D TCG_TYPE_I32) { - tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP0, addr_reg, TCG_REG_TMP2); - } else if (have_zba) { - tcg_out_opc_reg(s, OPC_ADD_UW, TCG_REG_TMP0, addr_reg, TCG_REG_TMP= 2); - } else { - tcg_out_ext32u(s, TCG_REG_TMP0, addr_reg); - tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP0, TCG_REG_TMP0, TCG_REG_TM= P2); - } - *pbase =3D TCG_REG_TMP0; -#else - TCGReg base; - - if (a_mask) { ldst =3D new_ldst_label(s); ldst->is_ld =3D is_ld; ldst->oi =3D oi; ldst->addrlo_reg =3D addr_reg; =20 - /* We are expecting alignment max 7, so we can always use andi. */ - tcg_debug_assert(a_mask =3D=3D sextreg(a_mask, 0, 12)); - tcg_out_opc_imm(s, OPC_ANDI, TCG_REG_TMP1, addr_reg, a_mask); + tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP0, TCG_AREG0, mask_ofs); + tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, TCG_AREG0, table_ofs); =20 - ldst->label_ptr[0] =3D s->code_ptr; - tcg_out_opc_branch(s, OPC_BNE, TCG_REG_TMP1, TCG_REG_ZERO, 0); - } + tcg_out_opc_imm(s, OPC_SRLI, TCG_REG_TMP2, addr_reg, + s->page_bits - CPU_TLB_ENTRY_BITS); + tcg_out_opc_reg(s, OPC_AND, TCG_REG_TMP2, TCG_REG_TMP2, TCG_REG_TM= P0); + tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP2, TCG_REG_TMP2, TCG_REG_TM= P1); =20 - if (guest_base !=3D 0) { - base =3D TCG_REG_TMP0; - if (addr_type !=3D TCG_TYPE_I32) { - tcg_out_opc_reg(s, OPC_ADD, base, addr_reg, TCG_GUEST_BASE_REG= ); - } else if (have_zba) { - tcg_out_opc_reg(s, OPC_ADD_UW, base, addr_reg, TCG_GUEST_BASE_= REG); - } else { - tcg_out_ext32u(s, base, addr_reg); - tcg_out_opc_reg(s, OPC_ADD, base, base, TCG_GUEST_BASE_REG); + /* + * For aligned accesses, we check the first byte and include the + * alignment bits within the address. For unaligned access, we + * check that we don't cross pages using the address of the last + * byte of the access. + */ + addr_adj =3D addr_reg; + if (a_mask < s_mask) { + addr_adj =3D TCG_REG_TMP0; + tcg_out_opc_imm(s, addr_type =3D=3D TCG_TYPE_I32 ? OPC_ADDIW := OPC_ADDI, + addr_adj, addr_reg, s_mask - a_mask); } - } else if (addr_type !=3D TCG_TYPE_I32) { - base =3D addr_reg; + compare_mask =3D s->page_mask | a_mask; + if (compare_mask =3D=3D sextreg(compare_mask, 0, 12)) { + tcg_out_opc_imm(s, OPC_ANDI, TCG_REG_TMP1, addr_adj, compare_m= ask); + } else { + tcg_out_movi(s, addr_type, TCG_REG_TMP1, compare_mask); + tcg_out_opc_reg(s, OPC_AND, TCG_REG_TMP1, TCG_REG_TMP1, addr_a= dj); + } + + /* Load the tlb comparator and the addend. */ + QEMU_BUILD_BUG_ON(HOST_BIG_ENDIAN); + tcg_out_ld(s, addr_type, TCG_REG_TMP0, TCG_REG_TMP2, + is_ld ? offsetof(CPUTLBEntry, addr_read) + : offsetof(CPUTLBEntry, addr_write)); + tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP2, TCG_REG_TMP2, + offsetof(CPUTLBEntry, addend)); + + /* Compare masked address with the TLB entry. */ + ldst->label_ptr[0] =3D s->code_ptr; + tcg_out_opc_branch(s, OPC_BNE, TCG_REG_TMP0, TCG_REG_TMP1, 0); + + /* TLB Hit - translate address using addend. */ + if (addr_type !=3D TCG_TYPE_I32) { + tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP0, addr_reg, TCG_REG_TM= P2); + } else if (have_zba) { + tcg_out_opc_reg(s, OPC_ADD_UW, TCG_REG_TMP0, + addr_reg, TCG_REG_TMP2); + } else { + tcg_out_ext32u(s, TCG_REG_TMP0, addr_reg); + tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP0, + TCG_REG_TMP0, TCG_REG_TMP2); + } + *pbase =3D TCG_REG_TMP0; } else { - base =3D TCG_REG_TMP0; - tcg_out_ext32u(s, base, addr_reg); + TCGReg base; + + if (a_mask) { + ldst =3D new_ldst_label(s); + ldst->is_ld =3D is_ld; + ldst->oi =3D oi; + ldst->addrlo_reg =3D addr_reg; + + /* We are expecting alignment max 7, so we can always use andi= . */ + tcg_debug_assert(a_mask =3D=3D sextreg(a_mask, 0, 12)); + tcg_out_opc_imm(s, OPC_ANDI, TCG_REG_TMP1, addr_reg, a_mask); + + ldst->label_ptr[0] =3D s->code_ptr; + tcg_out_opc_branch(s, OPC_BNE, TCG_REG_TMP1, TCG_REG_ZERO, 0); + } + + if (guest_base !=3D 0) { + base =3D TCG_REG_TMP0; + if (addr_type !=3D TCG_TYPE_I32) { + tcg_out_opc_reg(s, OPC_ADD, base, addr_reg, + TCG_GUEST_BASE_REG); + } else if (have_zba) { + tcg_out_opc_reg(s, OPC_ADD_UW, base, addr_reg, + TCG_GUEST_BASE_REG); + } else { + tcg_out_ext32u(s, base, addr_reg); + tcg_out_opc_reg(s, OPC_ADD, base, base, TCG_GUEST_BASE_REG= ); + } + } else if (addr_type !=3D TCG_TYPE_I32) { + base =3D addr_reg; + } else { + base =3D TCG_REG_TMP0; + tcg_out_ext32u(s, base, addr_reg); + } + *pbase =3D base; } - *pbase =3D base; -#endif =20 return ldst; } @@ -2075,12 +2080,10 @@ static void tcg_target_qemu_prologue(TCGContext *s) TCG_REG_SP, SAVE_OFS + i * REG_SIZE); } =20 -#if !defined(CONFIG_SOFTMMU) - if (guest_base) { + if (!tcg_use_softmmu && guest_base) { tcg_out_movi(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base); tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG); } -#endif =20 /* Call generated code */ tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]); --=20 2.34.1 From nobody Wed Nov 27 17:32:24 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697668046296100002 Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target.c.inc | 161 ++++++++++++++++++------------------- 1 file changed, 79 insertions(+), 82 deletions(-) diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index 4ef9ac3d5b..fbee43d3b0 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -46,9 +46,7 @@ /* A scratch register that may be be used throughout the backend. */ #define TCG_TMP0 TCG_REG_R1 =20 -#ifndef CONFIG_SOFTMMU #define TCG_GUEST_BASE_REG TCG_REG_R13 -#endif =20 /* All of the following instructions are prefixed with their instruction format, and are defined as 8- or 16-bit quantities, even when the two @@ -1768,94 +1766,95 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGConte= xt *s, HostAddress *h, h->aa =3D atom_and_align_for_opc(s, opc, MO_ATOM_IFALIGN, s_bits =3D= =3D MO_128); a_mask =3D (1 << h->aa.align) - 1; =20 -#ifdef CONFIG_SOFTMMU - unsigned s_mask =3D (1 << s_bits) - 1; - int mem_index =3D get_mmuidx(oi); - int fast_off =3D tlb_mask_table_ofs(s, mem_index); - int mask_off =3D fast_off + offsetof(CPUTLBDescFast, mask); - int table_off =3D fast_off + offsetof(CPUTLBDescFast, table); - int ofs, a_off; - uint64_t tlb_mask; + if (tcg_use_softmmu) { + unsigned s_mask =3D (1 << s_bits) - 1; + int mem_index =3D get_mmuidx(oi); + int fast_off =3D tlb_mask_table_ofs(s, mem_index); + int mask_off =3D fast_off + offsetof(CPUTLBDescFast, mask); + int table_off =3D fast_off + offsetof(CPUTLBDescFast, table); + int ofs, a_off; + uint64_t tlb_mask; =20 - ldst =3D new_ldst_label(s); - ldst->is_ld =3D is_ld; - ldst->oi =3D oi; - ldst->addrlo_reg =3D addr_reg; - - tcg_out_sh64(s, RSY_SRLG, TCG_TMP0, addr_reg, TCG_REG_NONE, - s->page_bits - CPU_TLB_ENTRY_BITS); - - tcg_out_insn(s, RXY, NG, TCG_TMP0, TCG_AREG0, TCG_REG_NONE, mask_off); - tcg_out_insn(s, RXY, AG, TCG_TMP0, TCG_AREG0, TCG_REG_NONE, table_off); - - /* - * For aligned accesses, we check the first byte and include the align= ment - * bits within the address. For unaligned access, we check that we do= n't - * cross pages using the address of the last byte of the access. - */ - a_off =3D (a_mask >=3D s_mask ? 0 : s_mask - a_mask); - tlb_mask =3D (uint64_t)s->page_mask | a_mask; - if (a_off =3D=3D 0) { - tgen_andi_risbg(s, TCG_REG_R0, addr_reg, tlb_mask); - } else { - tcg_out_insn(s, RX, LA, TCG_REG_R0, addr_reg, TCG_REG_NONE, a_off); - tgen_andi(s, addr_type, TCG_REG_R0, tlb_mask); - } - - if (is_ld) { - ofs =3D offsetof(CPUTLBEntry, addr_read); - } else { - ofs =3D offsetof(CPUTLBEntry, addr_write); - } - if (addr_type =3D=3D TCG_TYPE_I32) { - ofs +=3D HOST_BIG_ENDIAN * 4; - tcg_out_insn(s, RX, C, TCG_REG_R0, TCG_TMP0, TCG_REG_NONE, ofs); - } else { - tcg_out_insn(s, RXY, CG, TCG_REG_R0, TCG_TMP0, TCG_REG_NONE, ofs); - } - - tcg_out16(s, RI_BRC | (S390_CC_NE << 4)); - ldst->label_ptr[0] =3D s->code_ptr++; - - h->index =3D TCG_TMP0; - tcg_out_insn(s, RXY, LG, h->index, TCG_TMP0, TCG_REG_NONE, - offsetof(CPUTLBEntry, addend)); - - if (addr_type =3D=3D TCG_TYPE_I32) { - tcg_out_insn(s, RRE, ALGFR, h->index, addr_reg); - h->base =3D TCG_REG_NONE; - } else { - h->base =3D addr_reg; - } - h->disp =3D 0; -#else - if (a_mask) { ldst =3D new_ldst_label(s); ldst->is_ld =3D is_ld; ldst->oi =3D oi; ldst->addrlo_reg =3D addr_reg; =20 - /* We are expecting a_bits to max out at 7, much lower than TMLL. = */ - tcg_debug_assert(a_mask <=3D 0xffff); - tcg_out_insn(s, RI, TMLL, addr_reg, a_mask); + tcg_out_sh64(s, RSY_SRLG, TCG_TMP0, addr_reg, TCG_REG_NONE, + s->page_bits - CPU_TLB_ENTRY_BITS); =20 - tcg_out16(s, RI_BRC | (7 << 4)); /* CC in {1,2,3} */ + tcg_out_insn(s, RXY, NG, TCG_TMP0, TCG_AREG0, TCG_REG_NONE, mask_o= ff); + tcg_out_insn(s, RXY, AG, TCG_TMP0, TCG_AREG0, TCG_REG_NONE, table_= off); + + /* + * For aligned accesses, we check the first byte and include the + * alignment bits within the address. For unaligned access, we + * check that we don't cross pages using the address of the last + * byte of the access. + */ + a_off =3D (a_mask >=3D s_mask ? 0 : s_mask - a_mask); + tlb_mask =3D (uint64_t)s->page_mask | a_mask; + if (a_off =3D=3D 0) { + tgen_andi_risbg(s, TCG_REG_R0, addr_reg, tlb_mask); + } else { + tcg_out_insn(s, RX, LA, TCG_REG_R0, addr_reg, TCG_REG_NONE, a_= off); + tgen_andi(s, addr_type, TCG_REG_R0, tlb_mask); + } + + if (is_ld) { + ofs =3D offsetof(CPUTLBEntry, addr_read); + } else { + ofs =3D offsetof(CPUTLBEntry, addr_write); + } + if (addr_type =3D=3D TCG_TYPE_I32) { + ofs +=3D HOST_BIG_ENDIAN * 4; + tcg_out_insn(s, RX, C, TCG_REG_R0, TCG_TMP0, TCG_REG_NONE, ofs= ); + } else { + tcg_out_insn(s, RXY, CG, TCG_REG_R0, TCG_TMP0, TCG_REG_NONE, o= fs); + } + + tcg_out16(s, RI_BRC | (S390_CC_NE << 4)); ldst->label_ptr[0] =3D s->code_ptr++; - } =20 - h->base =3D addr_reg; - if (addr_type =3D=3D TCG_TYPE_I32) { - tcg_out_ext32u(s, TCG_TMP0, addr_reg); - h->base =3D TCG_TMP0; - } - if (guest_base < 0x80000) { - h->index =3D TCG_REG_NONE; - h->disp =3D guest_base; - } else { - h->index =3D TCG_GUEST_BASE_REG; + h->index =3D TCG_TMP0; + tcg_out_insn(s, RXY, LG, h->index, TCG_TMP0, TCG_REG_NONE, + offsetof(CPUTLBEntry, addend)); + + if (addr_type =3D=3D TCG_TYPE_I32) { + tcg_out_insn(s, RRE, ALGFR, h->index, addr_reg); + h->base =3D TCG_REG_NONE; + } else { + h->base =3D addr_reg; + } h->disp =3D 0; + } else { + if (a_mask) { + ldst =3D new_ldst_label(s); + ldst->is_ld =3D is_ld; + ldst->oi =3D oi; + ldst->addrlo_reg =3D addr_reg; + + /* We are expecting a_bits to max out at 7, much lower than TM= LL. */ + tcg_debug_assert(a_mask <=3D 0xffff); + tcg_out_insn(s, RI, TMLL, addr_reg, a_mask); + + tcg_out16(s, RI_BRC | (7 << 4)); /* CC in {1,2,3} */ + ldst->label_ptr[0] =3D s->code_ptr++; + } + + h->base =3D addr_reg; + if (addr_type =3D=3D TCG_TYPE_I32) { + tcg_out_ext32u(s, TCG_TMP0, addr_reg); + h->base =3D TCG_TMP0; + } + if (guest_base < 0x80000) { + h->index =3D TCG_REG_NONE; + h->disp =3D guest_base; + } else { + h->index =3D TCG_GUEST_BASE_REG; + h->disp =3D 0; + } } -#endif =20 return ldst; } @@ -3453,12 +3452,10 @@ static void tcg_target_qemu_prologue(TCGContext *s) TCG_STATIC_CALL_ARGS_SIZE + TCG_TARGET_CALL_STACK_OFFSET, CPU_TEMP_BUF_NLONGS * sizeof(long)); =20 -#ifndef CONFIG_SOFTMMU - if (guest_base >=3D 0x80000) { + if (!tcg_use_softmmu && guest_base >=3D 0x80000) { tcg_out_movi(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base); tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG); } -#endif =20 tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]); =20 --=20 2.34.1 From nobody Wed Nov 27 17:32:24 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1697668400; 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id 13-20020a170902c24d00b001b9d95945afsm431058plg.155.2023.10.18.15.26.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Oct 2023 15:26:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1697667981; x=1698272781; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=qq+/ocKlHxuwOLYzAnqcUyLG835LUOMki3n0K/cpOvs=; b=XjfzpNBS+3c2+hjem6mOqS4IFEiTXolG/SEECoOCTFI4Tw2oICEmqKo7eQ8j5wuLWL 8WYCZs5QLB60Yunb+Z+ZOjMapJQ0Fvdgp+nwUGTnxmeyRtqVjd44hktw9LmulRcKhTXU 9KaO6mkprzEyh6c+kng1VzTZjDFDgR2RktQm6uftylK+gKw4CPt8j+D3JW1JlFj8/vBQ Md/J6d/jhn6e80nr0o6wCCwal1SzvigP0LynashOFQ3cQba+J7twFSwzG0aX707rjM75 7O1H4+XT87lLZIHm5xd2k7iHZOGb0tLO/w3pYyDr2gHj3SzHVc6o7tGoTzDKBmCMbqva GjuQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697667981; x=1698272781; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=qq+/ocKlHxuwOLYzAnqcUyLG835LUOMki3n0K/cpOvs=; b=YsiHGfVtlvMJN77RO6DA7cdjUcvBjRfPLJOvXFANQ42ZHmsE8U0miyuuwVHdOIc04w l1Qe358ewDOP+7lLOMdS90UZM6ML/TONFWJgO4HorQOpv5d4YRKi8gkTg0ZG1b9ETymp /JPgiPzA2Eo9BfesbC91QwGZr2Nw7FYBDm1A6zugfsvr0xfNJYwcIBZUIY6/a1EECSYQ clp3PXEpMFMaJ4Mpgel4wt3o8nikgLfqbFfRr6ZjtRdKBuz+7xegCTbXjRYqQTGqsidJ pJybc6rnRCanBc73HQ3YxOFogQUxxQ6/F26TKstDp7gPdK7gTkWXLG21+aYVLboODpkC uZfQ== X-Gm-Message-State: AOJu0YxU5r33GuX3JUniBocBbyx4PFjvTiPrm7sbDUAAog/i7hSeYmzr XB8MfA09KG4BH/LadHB4GuRUIrimRYT+00R3cSA= X-Google-Smtp-Source: AGHT+IG5v7ZRWCoZHAPxcFNIinbmMnYxJOVT64EdD5c3iHyKUxg2xEBZ3ZmYBoNCPeV7/nlDQSTAvQ== X-Received: by 2002:a17:902:da8d:b0:1c5:de4c:f079 with SMTP id j13-20020a170902da8d00b001c5de4cf079mr828068plx.33.1697667981229; Wed, 18 Oct 2023 15:26:21 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Mike Frysinger , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 25/29] tcg: drop unused tcg_temp_free define Date: Wed, 18 Oct 2023 15:25:53 -0700 Message-Id: <20231018222557.1562065-26-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231018222557.1562065-1-richard.henderson@linaro.org> References: <20231018222557.1562065-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697668401817100006 From: Mike Frysinger Use of the API was removed a while back, but the define wasn't. Signed-off-by: Mike Frysinger Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20231015010046.16020-1-vapier@gentoo.org> Signed-off-by: Richard Henderson --- include/tcg/tcg-op.h | 2 -- 1 file changed, 2 deletions(-) diff --git a/include/tcg/tcg-op.h b/include/tcg/tcg-op.h index 80cfcf8104..3ead59e459 100644 --- a/include/tcg/tcg-op.h +++ b/include/tcg/tcg-op.h @@ -52,7 +52,6 @@ static inline void tcg_gen_insn_start(target_ulong pc, ta= rget_ulong a1, typedef TCGv_i32 TCGv; #define tcg_temp_new() tcg_temp_new_i32() #define tcg_global_mem_new tcg_global_mem_new_i32 -#define tcg_temp_free tcg_temp_free_i32 #define tcgv_tl_temp tcgv_i32_temp #define tcg_gen_qemu_ld_tl tcg_gen_qemu_ld_i32 #define tcg_gen_qemu_st_tl tcg_gen_qemu_st_i32 @@ -60,7 +59,6 @@ typedef TCGv_i32 TCGv; typedef TCGv_i64 TCGv; #define tcg_temp_new() tcg_temp_new_i64() #define tcg_global_mem_new tcg_global_mem_new_i64 -#define tcg_temp_free tcg_temp_free_i64 #define tcgv_tl_temp tcgv_i64_temp #define tcg_gen_qemu_ld_tl tcg_gen_qemu_ld_i64 #define tcg_gen_qemu_st_tl tcg_gen_qemu_st_i64 --=20 2.34.1 From nobody Wed Nov 27 17:32:24 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1697668400; cv=none; d=zohomail.com; s=zohoarc; b=kaXl+X/nK9JbM8jEZ9xk4nSVN1UALNyoq2kvtC7OP49gr3HMMen5WBhEXILdKzJwNAE2XkCDxFIUMB+dK7siE9Dn8jMbo2/nSNX4TiBa6HtiQDxh+i48Vypf/PKcTB/DnKjZOWNzb5PSkN1rtkk4MTuBkIsAc4v0NaNXPuvVDGI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1697668400; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=F3d0+LIJRpydd1LcLJpx5zgMPpG2uno1kweVdtXY0oQ=; b=EDZVHWYPrFNkXRJFYH7j+ESe295NLvjV/QkbVQoX1ycxzn7uADWc3eZoge6xmpIVKrRJLD5yVrdi7q4K418nbW8rtb57GvfAlWb9TSTFMwQKd7ns0tllwVjpeDDlovxjo95uww9Kw16zkNlXTUuHtzO0fVaDS2kTxvCAYg2Roak= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1697668400586712.8623080331276; Wed, 18 Oct 2023 15:33:20 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qtEzj-0008D0-Kf; Wed, 18 Oct 2023 18:26:27 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qtEzh-0008BU-DZ for qemu-devel@nongnu.org; Wed, 18 Oct 2023 18:26:25 -0400 Received: from mail-pl1-x636.google.com ([2607:f8b0:4864:20::636]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qtEzf-0002WV-Aj for qemu-devel@nongnu.org; Wed, 18 Oct 2023 18:26:25 -0400 Received: by mail-pl1-x636.google.com with SMTP id d9443c01a7336-1c9e06f058bso1358215ad.0 for ; Wed, 18 Oct 2023 15:26:22 -0700 (PDT) Received: from stoup.. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697668401798100005 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- tcg/tcg-op.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 393dbcd01c..c29355b67b 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -342,8 +342,8 @@ void tcg_gen_divu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv= _i32 arg2) tcg_gen_op3_i32(INDEX_op_divu_i32, ret, arg1, arg2); } else if (TCG_TARGET_HAS_div2_i32) { TCGv_i32 t0 =3D tcg_temp_ebb_new_i32(); - tcg_gen_movi_i32(t0, 0); - tcg_gen_op5_i32(INDEX_op_divu2_i32, ret, t0, arg1, t0, arg2); + TCGv_i32 zero =3D tcg_constant_i32(0); + tcg_gen_op5_i32(INDEX_op_divu2_i32, ret, t0, arg1, zero, arg2); tcg_temp_free_i32(t0); } else { gen_helper_divu_i32(ret, arg1, arg2); @@ -362,8 +362,8 @@ void tcg_gen_remu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv= _i32 arg2) tcg_temp_free_i32(t0); } else if (TCG_TARGET_HAS_div2_i32) { TCGv_i32 t0 =3D tcg_temp_ebb_new_i32(); - tcg_gen_movi_i32(t0, 0); - tcg_gen_op5_i32(INDEX_op_divu2_i32, t0, ret, arg1, t0, arg2); + TCGv_i32 zero =3D tcg_constant_i32(0); + tcg_gen_op5_i32(INDEX_op_divu2_i32, t0, ret, arg1, zero, arg2); tcg_temp_free_i32(t0); } else { gen_helper_remu_i32(ret, arg1, arg2); @@ -1674,8 +1674,8 @@ void tcg_gen_divu_i64(TCGv_i64 ret, TCGv_i64 arg1, TC= Gv_i64 arg2) tcg_gen_op3_i64(INDEX_op_divu_i64, ret, arg1, arg2); } else if (TCG_TARGET_HAS_div2_i64) { TCGv_i64 t0 =3D tcg_temp_ebb_new_i64(); - tcg_gen_movi_i64(t0, 0); - tcg_gen_op5_i64(INDEX_op_divu2_i64, ret, t0, arg1, t0, arg2); + TCGv_i64 zero =3D tcg_constant_i64(0); + tcg_gen_op5_i64(INDEX_op_divu2_i64, ret, t0, arg1, zero, arg2); tcg_temp_free_i64(t0); } else { gen_helper_divu_i64(ret, arg1, arg2); @@ -1694,8 +1694,8 @@ void tcg_gen_remu_i64(TCGv_i64 ret, TCGv_i64 arg1, TC= Gv_i64 arg2) tcg_temp_free_i64(t0); } else if (TCG_TARGET_HAS_div2_i64) { TCGv_i64 t0 =3D tcg_temp_ebb_new_i64(); - tcg_gen_movi_i64(t0, 0); - tcg_gen_op5_i64(INDEX_op_divu2_i64, t0, ret, arg1, t0, arg2); + TCGv_i64 zero =3D tcg_constant_i64(0); + tcg_gen_op5_i64(INDEX_op_divu2_i64, t0, ret, arg1, zero, arg2); tcg_temp_free_i64(t0); } else { gen_helper_remu_i64(ret, arg1, arg2); --=20 2.34.1 From nobody Wed Nov 27 17:32:24 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id 13-20020a170902c24d00b001b9d95945afsm431058plg.155.2023.10.18.15.26.22 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Oct 2023 15:26:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1697667983; x=1698272783; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=QOgygXHDxUHtfSFg6wMi8J9He8Jq0o2OiYkY7oLrEpM=; b=TrBpgvRJH7NywtdKrlwyN3vLPadSu/sRKc0LCCoZpQmPfEGpMla1fVP5P+jB86+Lpo 90Iqj4f10yNrMDf9Bln00p6opZ4sca96/IReDh51ZgoDdPQYJmyGykTnZC4ZgGYcH+78 3tj4n8tYs6yAbTcH2YdvdzzHYEoSW3nUcujQfWaldtokrEx73H/W1yODrTTwdMWd9W29 r2NHw4B1ZO85173Ocmk2/+8HfE36sv2zql1lH2RR5+iROQXcQidzjLljwuvEFfXKIuW6 DZCNCVjsEjumv4VmsoKHJXyufvs7pxBMlh9+cGom8rRrjcfQdP36io2H25gSQlbktJfP XYWA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697667983; x=1698272783; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=QOgygXHDxUHtfSFg6wMi8J9He8Jq0o2OiYkY7oLrEpM=; b=BX/cO+c/8IlA1X6GB6VzRY1E2rPzI8jUZEiFbKduq+3v5fG0WrvBRs/1KYOmrUg2wl VDkgFrYFlkqd6MEBEiX0D3OSH+OCoiSm5kIOTXlb07p1o4xjh3iTzCDniiHq/pwRYko9 I8QuEeo92Zy2vHDXm0J9+9Kdr0nJ+JN4/hBhP3XUa3KtTQXaU8zU/mHmvCNaZyDijrHu xrRX764BzT2pHh6/9GjqtDdd3nfAO4wlwd4jl0Kio2YIjKA50erHT2480FlUQgISMaZR Qqw6IsPYbSiNCdW+Gjl+BDXvxLGkhRQi2IKMfvCxGH1+Mluyb0IQ/hfDVaBwnaISnFHB PcuQ== X-Gm-Message-State: AOJu0Yywdm8opzHrV3isAS95l0e3v4VPSW4xk33IuABMwrVJJQ/aSoF+ OTZKckIdq7h7qJOO5ETdnVmBf3PJcAAXdQNAH5Y= X-Google-Smtp-Source: AGHT+IEOXKKTnp+LyfWr7jK5iamAehfggSAaU2ZpsyD8ZDob1RfuEW65XtWIatXhtAnrpBGbZKeYow== X-Received: by 2002:a17:902:f38b:b0:1c9:d667:4e85 with SMTP id f11-20020a170902f38b00b001c9d6674e85mr643466ple.40.1697667982778; Wed, 18 Oct 2023 15:26:22 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 27/29] tcg: Optimize past conditional branches Date: Wed, 18 Oct 2023 15:25:55 -0700 Message-Id: <20231018222557.1562065-28-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231018222557.1562065-1-richard.henderson@linaro.org> References: <20231018222557.1562065-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697668024208100001 Content-Type: text/plain; charset="utf-8" We already register allocate through extended basic blocks, optimize through extended basic blocks as well. Signed-off-by: Richard Henderson --- tcg/optimize.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/tcg/optimize.c b/tcg/optimize.c index 3013eb04e6..2db5177c32 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -688,12 +688,14 @@ static void finish_folding(OptContext *ctx, TCGOp *op) int i, nb_oargs; =20 /* - * For an opcode that ends a BB, reset all temp data. - * We do no cross-BB optimization. + * We only optimize extended basic blocks. If the opcode ends a BB + * and is not a conditional branch, reset all temp data. */ if (def->flags & TCG_OPF_BB_END) { - memset(&ctx->temps_used, 0, sizeof(ctx->temps_used)); ctx->prev_mb =3D NULL; + if (!(def->flags & TCG_OPF_COND_BRANCH)) { + memset(&ctx->temps_used, 0, sizeof(ctx->temps_used)); + } return; } =20 --=20 2.34.1 From nobody Wed Nov 27 17:32:24 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1697668187; cv=none; d=zohomail.com; s=zohoarc; b=SxHpRAMgn0OChX5NXrP5T94BmfdzrpWvyGoPEv7UR734taviyypjeIurQJqeNaQc7cdoJB5RGqor2V9rxVPkM+85k3WmnzNHZxjh8azl9Enzg2DzO3YEf6lgunidq9xPJA3A0jOgnZjcxCVFKnSHmYX0JApxDeUTFD2q1sqjprk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1697668187; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=i+3c/q3YHMTCq7WXcy5yo10z7tmQCbWln7ShYoiyjhk=; b=h6h7MoaxF6ZRzgknXMMWQy3I2iJMGHe7qPuvRbFa3Y+0XTlwSLfkGRaaCMCs/idkVPm+CBaJH7dOJOtD1rWTjZecKJNIQkzfWeX2zocFt3/R0IhJsPuLOdx/8WIuduMbSRDu91CpGVqZGSigVkWp+qO1bsQHWTaf5b6lIKm771E= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1697668187090626.4288088121649; Wed, 18 Oct 2023 15:29:47 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qtEzm-0008E6-Dj; Wed, 18 Oct 2023 18:26:30 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qtEzi-0008Cd-Si for qemu-devel@nongnu.org; Wed, 18 Oct 2023 18:26:26 -0400 Received: from mail-pl1-x629.google.com ([2607:f8b0:4864:20::629]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qtEzg-0002Wu-Ry for qemu-devel@nongnu.org; Wed, 18 Oct 2023 18:26:26 -0400 Received: by mail-pl1-x629.google.com with SMTP id d9443c01a7336-1c0ecb9a075so51284725ad.2 for ; Wed, 18 Oct 2023 15:26:24 -0700 (PDT) Received: from stoup.. ([71.212.149.95]) by smtp.gmail.com with ESMTPSA id 13-20020a170902c24d00b001b9d95945afsm431058plg.155.2023.10.18.15.26.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Oct 2023 15:26:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1697667983; x=1698272783; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=i+3c/q3YHMTCq7WXcy5yo10z7tmQCbWln7ShYoiyjhk=; b=lL2j41WC81p7BdVmwpZb9bTmWMsxHzIovu9uQ3Wc68cnFVYdoCEjj2xb6FM4zM5CJ6 PcNGCMAM2Piaox1q1nw3IseALeuHGXVMHizQU+f1USlCWLWFxhLrJ7FrpUNr4/zy2f8J tQ8Ts0tXANQdz2X5x77mWCEIimsz8/DTr9VEh1YO9VHAObcKmWLMKvbpYS7BQAOSwWRG OFhzTbqE/t3nriSAaSWv7yiwG+SAfYIIeVtaVrtLgJY1Myjj4RKKgbuHb9SDVWW6xGHo /h5KD5jabX8pHkc7Ak0v40jEdXdZsYMkCNjIYNEu2gGWjlnIOh+M3BKHD0cqnct+l6Hr ctBw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697667983; x=1698272783; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=i+3c/q3YHMTCq7WXcy5yo10z7tmQCbWln7ShYoiyjhk=; b=gnrc5lFZSY5K+cv72Y6l5N3ujGVY66rgSS2Xr5XufUkYH6YcXBV0vv24OnJj4jSK/j rTQ9Q+Eft3gV2SjzQL82svhQULv5kepCMSFpagoX7QbJVilHS56gIyGWsRBQ9xVlDOP3 kkakaHkjTJx24UFsN2bppDh5FZklksTID6XWcCIoQIgOOYW5Rg13+QdVrgnV2XdLKJNd Y90epTnlUpw5/9KK9ZonYxEojUulWb338NxRhVL/L9Ujc+nN8nCkQpXzV9vOyzYIAHNT OEtAS30M7aGNOUG+F5w4M5LpCXqcnxHkwSoX22lWSPQvj5AMLKrJl2jOq+sgv1xHfMhr jFMA== X-Gm-Message-State: AOJu0Yy6jevPwjmDQ5NAmsU8hJd+EIqCXra7SP4Oc4jyhoj7ugc3/t87 WHB8VsjRS3ASes9G3sL2ZuwEBHKi171DcLKzAe0= X-Google-Smtp-Source: AGHT+IG6/aHbuZlW4w+aTI5xLmj2t6mqr6LPD6JM/SFFoQ3L/NYWauhz5JsP2CS1BYeWWH4+77CoCA== X-Received: by 2002:a17:902:ce8a:b0:1c7:7b27:f9a9 with SMTP id f10-20020a170902ce8a00b001c77b27f9a9mr784385plg.59.1697667983472; Wed, 18 Oct 2023 15:26:23 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Song Gao , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 28/29] tcg: Add tcg_gen_{ld,st}_i128 Date: Wed, 18 Oct 2023 15:25:56 -0700 Message-Id: <20231018222557.1562065-29-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231018222557.1562065-1-richard.henderson@linaro.org> References: <20231018222557.1562065-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697668188947100001 Do not require the translators to jump through concat and extract of i64 in order to move values to and from env. Tested-by: Song Gao Reviewed-by: Song Gao Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- include/tcg/tcg-op-common.h | 3 +++ tcg/tcg-op.c | 22 ++++++++++++++++++++++ 2 files changed, 25 insertions(+) diff --git a/include/tcg/tcg-op-common.h b/include/tcg/tcg-op-common.h index 2048f92b5e..56d4e9cb9f 100644 --- a/include/tcg/tcg-op-common.h +++ b/include/tcg/tcg-op-common.h @@ -747,6 +747,9 @@ void tcg_gen_mov_i128(TCGv_i128 dst, TCGv_i128 src); void tcg_gen_extr_i128_i64(TCGv_i64 lo, TCGv_i64 hi, TCGv_i128 arg); void tcg_gen_concat_i64_i128(TCGv_i128 ret, TCGv_i64 lo, TCGv_i64 hi); =20 +void tcg_gen_ld_i128(TCGv_i128 ret, TCGv_ptr base, tcg_target_long offset); +void tcg_gen_st_i128(TCGv_i128 val, TCGv_ptr base, tcg_target_long offset); + static inline void tcg_gen_concat32_i64(TCGv_i64 ret, TCGv_i64 lo, TCGv_i6= 4 hi) { tcg_gen_deposit_i64(ret, lo, hi, 32, 32); diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index c29355b67b..b4dbb2f2ba 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -2880,6 +2880,28 @@ void tcg_gen_mov_i128(TCGv_i128 dst, TCGv_i128 src) } } =20 +void tcg_gen_ld_i128(TCGv_i128 ret, TCGv_ptr base, tcg_target_long offset) +{ + if (HOST_BIG_ENDIAN) { + tcg_gen_ld_i64(TCGV128_HIGH(ret), base, offset); + tcg_gen_ld_i64(TCGV128_LOW(ret), base, offset + 8); + } else { + tcg_gen_ld_i64(TCGV128_LOW(ret), base, offset); + tcg_gen_ld_i64(TCGV128_HIGH(ret), base, offset + 8); + } +} + +void tcg_gen_st_i128(TCGv_i128 val, TCGv_ptr base, tcg_target_long offset) +{ + if (HOST_BIG_ENDIAN) { + tcg_gen_st_i64(TCGV128_HIGH(val), base, offset); + tcg_gen_st_i64(TCGV128_LOW(val), base, offset + 8); + } else { + tcg_gen_st_i64(TCGV128_LOW(val), base, offset); + tcg_gen_st_i64(TCGV128_HIGH(val), base, offset + 8); + } +} + /* QEMU specific operations. */ =20 void tcg_gen_exit_tb(const TranslationBlock *tb, unsigned idx) --=20 2.34.1 From nobody Wed Nov 27 17:32:24 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1697668111; cv=none; d=zohomail.com; s=zohoarc; b=bLCA2RTYXefrPX4UvmVHcYiwVZ6g9s7IT+n4nx4j8yK6SOU8wIUzkiKzsy6op15cay1oVi5G5+Gj6o3QiT4QRBK2rrxJFSPYaPzQ7hzvQK+lLX2kTK6M6T+4CZDc7jtgJ6q/d1kFWTXefM/HOTM2ZrI+cwoW0H1uX2xivyRSHhs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1697668111; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; bh=VWfRq90wjGAr0oweacpv5OPKCpxjoxKXHInDtElvTJQ=; b=KH3RZe1/EYrVmw5EIlt8LzFRMlJDhm9jpiy8Zhb9OBKoPnat33/oFgNPxm44RH8Q/7TAL9OrsjHRNS8bItMVRkgXCXmMm/E2lqGjvt8R47uO/HbyM+SdTpMt6/E+lkg9twZIMSvIrXM3Vfse6Uzm1BP8LyuIf6LCqTg+8LG95J8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1697668111002330.00315248803713; Wed, 18 Oct 2023 15:28:31 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qtEzn-0008Em-MI; Wed, 18 Oct 2023 18:26:31 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qtEzk-0008DO-2w for qemu-devel@nongnu.org; Wed, 18 Oct 2023 18:26:28 -0400 Received: from mail-pl1-x62d.google.com ([2607:f8b0:4864:20::62d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qtEzi-0002XE-82 for qemu-devel@nongnu.org; Wed, 18 Oct 2023 18:26:27 -0400 Received: by mail-pl1-x62d.google.com with SMTP id d9443c01a7336-1cab2c24ecdso2579805ad.0 for ; Wed, 18 Oct 2023 15:26:25 -0700 (PDT) Received: from stoup.. ([71.212.149.95]) by smtp.gmail.com with ESMTPSA id 13-20020a170902c24d00b001b9d95945afsm431058plg.155.2023.10.18.15.26.23 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Oct 2023 15:26:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1697667984; x=1698272784; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=VWfRq90wjGAr0oweacpv5OPKCpxjoxKXHInDtElvTJQ=; b=Tem9QmnoidsKj8YSLhQTsZr4LvyoGN+FE3T6vlSIJwTk3yhVB3PzUOT0mF/I1pXPmW Jw/1kIHChfR78WXZ40HEyUkMGWsb7W0Bw1W2+iCF4p4PK/vox83HVYxXThtUFRPVedpf z0ZfAsnjMOzJH/I5pBjqGwvRQ7TkLZ/V5xE2l9w3uEEBvwgCdoBGyVpTZr/VHv7zFiwt FvTwBeBkbodhyAhsDTCLrZPIXvPqnTBG78s9VTK2hyOpIPhudXGPczwvuko6QYMHihB6 JI3x5ysDWZq4oCFEkBuvi0aU8wunpQDnxTAdl6m6FX5qlecEyGkcsa02OoGkMf23lRTI 24sA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697667984; x=1698272784; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=VWfRq90wjGAr0oweacpv5OPKCpxjoxKXHInDtElvTJQ=; b=nQBbbS8hx6XBdF7IHFv7k9gPz1wVLenaeG4Gya0ALQ4dq0VgxNifT6mlcPuuhq6NSs sC6mYo1w91SjhRwu2YtGMS/nwsyA6XAUig7u93Gld2LExiTHfYVgSFT6qA3hfEqighyv 0FfGFF+sdpxRdeKNuFVRTJnyIvrTtseZnZVUFDe6tpbt36uz9n0nRdCwOYWiFEKHrVCu 3QM/29Nse47AbTE86RZKLv9EcbQy2ySQrw3nJZYElyX7fFEU6K0bdahd+xaKT8n+mzi4 GTqMCSNdCXsDtKw5L7pxGwcYzOluSg9ZdvW9TVLblotiH1znj48O20ZH2DrmVPKjKd1f Sltg== X-Gm-Message-State: AOJu0YwNJBWq9xKQxJranPGtfoBq/609KOKPYt1RmDqN2XsW8xX6cuOI MOgFnMciPj1CCixTOQp+Llr0dCyxFHMvXzL6GEg= X-Google-Smtp-Source: AGHT+IFiZPrODE08bPiVJo7MjtgYgyVFK/h5lSVdHOfLEmKC8+AjOMw9pGH7WTUwKho6dcmVMghx4Q== X-Received: by 2002:a17:903:258a:b0:1ca:8a38:38c4 with SMTP id jb10-20020a170903258a00b001ca8a3838c4mr597135plb.27.1697667984279; Wed, 18 Oct 2023 15:26:24 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 29/29] target/i386: Use i128 for 128 and 256-bit loads and stores Date: Wed, 18 Oct 2023 15:25:57 -0700 Message-Id: <20231018222557.1562065-30-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231018222557.1562065-1-richard.henderson@linaro.org> References: <20231018222557.1562065-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697668112526100007 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/i386/tcg/translate.c | 63 +++++++++++++++++-------------------- 1 file changed, 29 insertions(+), 34 deletions(-) diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index d2061ec44a..0c81e066de 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -2918,59 +2918,54 @@ static inline void gen_stq_env_A0(DisasContext *s, = int offset) =20 static inline void gen_ldo_env_A0(DisasContext *s, int offset, bool align) { + MemOp atom =3D (s->cpuid_ext_features & CPUID_EXT_AVX + ? MO_ATOM_IFALIGN : MO_ATOM_IFALIGN_PAIR); + MemOp mop =3D MO_128 | MO_LE | atom | (align ? MO_ALIGN_16 : 0); int mem_index =3D s->mem_index; - tcg_gen_qemu_ld_i64(s->tmp1_i64, s->A0, mem_index, - MO_LEUQ | (align ? MO_ALIGN_16 : 0)); - tcg_gen_st_i64(s->tmp1_i64, tcg_env, offset + offsetof(XMMReg, XMM_Q(0= ))); - tcg_gen_addi_tl(s->tmp0, s->A0, 8); - tcg_gen_qemu_ld_i64(s->tmp1_i64, s->tmp0, mem_index, MO_LEUQ); - tcg_gen_st_i64(s->tmp1_i64, tcg_env, offset + offsetof(XMMReg, XMM_Q(1= ))); + TCGv_i128 t =3D tcg_temp_new_i128(); + + tcg_gen_qemu_ld_i128(t, s->A0, mem_index, mop); + tcg_gen_st_i128(t, tcg_env, offset); } =20 static inline void gen_sto_env_A0(DisasContext *s, int offset, bool align) { + MemOp atom =3D (s->cpuid_ext_features & CPUID_EXT_AVX + ? MO_ATOM_IFALIGN : MO_ATOM_IFALIGN_PAIR); + MemOp mop =3D MO_128 | MO_LE | atom | (align ? MO_ALIGN_16 : 0); int mem_index =3D s->mem_index; - tcg_gen_ld_i64(s->tmp1_i64, tcg_env, offset + offsetof(XMMReg, XMM_Q(0= ))); - tcg_gen_qemu_st_i64(s->tmp1_i64, s->A0, mem_index, - MO_LEUQ | (align ? MO_ALIGN_16 : 0)); - tcg_gen_addi_tl(s->tmp0, s->A0, 8); - tcg_gen_ld_i64(s->tmp1_i64, tcg_env, offset + offsetof(XMMReg, XMM_Q(1= ))); - tcg_gen_qemu_st_i64(s->tmp1_i64, s->tmp0, mem_index, MO_LEUQ); + TCGv_i128 t =3D tcg_temp_new_i128(); + + tcg_gen_ld_i128(t, tcg_env, offset); + tcg_gen_qemu_st_i128(t, s->A0, mem_index, mop); } =20 static void gen_ldy_env_A0(DisasContext *s, int offset, bool align) { + MemOp mop =3D MO_128 | MO_LE | MO_ATOM_IFALIGN_PAIR; int mem_index =3D s->mem_index; - tcg_gen_qemu_ld_i64(s->tmp1_i64, s->A0, mem_index, - MO_LEUQ | (align ? MO_ALIGN_32 : 0)); - tcg_gen_st_i64(s->tmp1_i64, tcg_env, offset + offsetof(YMMReg, YMM_Q(0= ))); - tcg_gen_addi_tl(s->tmp0, s->A0, 8); - tcg_gen_qemu_ld_i64(s->tmp1_i64, s->tmp0, mem_index, MO_LEUQ); - tcg_gen_st_i64(s->tmp1_i64, tcg_env, offset + offsetof(YMMReg, YMM_Q(1= ))); + TCGv_i128 t0 =3D tcg_temp_new_i128(); + TCGv_i128 t1 =3D tcg_temp_new_i128(); =20 + tcg_gen_qemu_ld_i128(t0, s->A0, mem_index, mop | (align ? MO_ALIGN_32 = : 0)); tcg_gen_addi_tl(s->tmp0, s->A0, 16); - tcg_gen_qemu_ld_i64(s->tmp1_i64, s->tmp0, mem_index, MO_LEUQ); - tcg_gen_st_i64(s->tmp1_i64, tcg_env, offset + offsetof(YMMReg, YMM_Q(2= ))); - tcg_gen_addi_tl(s->tmp0, s->A0, 24); - tcg_gen_qemu_ld_i64(s->tmp1_i64, s->tmp0, mem_index, MO_LEUQ); - tcg_gen_st_i64(s->tmp1_i64, tcg_env, offset + offsetof(YMMReg, YMM_Q(3= ))); + tcg_gen_qemu_ld_i128(t1, s->tmp0, mem_index, mop); + + tcg_gen_st_i128(t0, tcg_env, offset + offsetof(YMMReg, YMM_X(0))); + tcg_gen_st_i128(t1, tcg_env, offset + offsetof(YMMReg, YMM_X(1))); } =20 static void gen_sty_env_A0(DisasContext *s, int offset, bool align) { + MemOp mop =3D MO_128 | MO_LE | MO_ATOM_IFALIGN_PAIR; int mem_index =3D s->mem_index; - tcg_gen_ld_i64(s->tmp1_i64, tcg_env, offset + offsetof(YMMReg, YMM_Q(0= ))); - tcg_gen_qemu_st_i64(s->tmp1_i64, s->A0, mem_index, - MO_LEUQ | (align ? MO_ALIGN_32 : 0)); - tcg_gen_addi_tl(s->tmp0, s->A0, 8); - tcg_gen_ld_i64(s->tmp1_i64, tcg_env, offset + offsetof(YMMReg, YMM_Q(1= ))); - tcg_gen_qemu_st_i64(s->tmp1_i64, s->tmp0, mem_index, MO_LEUQ); + TCGv_i128 t =3D tcg_temp_new_i128(); + + tcg_gen_ld_i128(t, tcg_env, offset + offsetof(YMMReg, YMM_X(0))); + tcg_gen_qemu_st_i128(t, s->A0, mem_index, mop | (align ? MO_ALIGN_32 := 0)); tcg_gen_addi_tl(s->tmp0, s->A0, 16); - tcg_gen_ld_i64(s->tmp1_i64, tcg_env, offset + offsetof(YMMReg, YMM_Q(2= ))); - tcg_gen_qemu_st_i64(s->tmp1_i64, s->tmp0, mem_index, MO_LEUQ); - tcg_gen_addi_tl(s->tmp0, s->A0, 24); - tcg_gen_ld_i64(s->tmp1_i64, tcg_env, offset + offsetof(YMMReg, YMM_Q(3= ))); - tcg_gen_qemu_st_i64(s->tmp1_i64, s->tmp0, mem_index, MO_LEUQ); + tcg_gen_ld_i128(t, tcg_env, offset + offsetof(YMMReg, YMM_X(1))); + tcg_gen_qemu_st_i128(t, s->tmp0, mem_index, mop); } =20 #include "decode-new.h" --=20 2.34.1