From nobody Wed Nov 27 21:32:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1697666569; cv=none; d=zohomail.com; s=zohoarc; b=m6Ll5r+wZovkvK/4VuYx4F1yuYENH61AeQ7kk7CNCM+rUcJdrHxaqR1x0E92ckL5+s3tvNF/vCCvGWRCGs0CXIi2m4JTwLuttmEMTpiUJ1Xb2/lIb42dHHiBXMlkrUptlOd0AcrD+t+uY2+bJkFHQ5QG8PckTqHzX8uGCIbuxR0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1697666569; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=IfXXjPSCAekTKnfIpCckOL6yHpkL7tvWXEcAjeu6hPU=; b=YoZArKpJXSf7JWrwc+8UJ8fa2mEtL837yd7SFFSfTgzT/SPj3GuoBbyWPEeb1lkhyDrdXqCbByVOAYNhh6jfXrBq6h+8zkvhXo2zPE/9YCiTGDIpxgjh0FoD3kuf+YPqJd9OJGtHgTl5Z9DEx1942IV8KyWTz8UzjWJNZUCgrf8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1697666569394116.4162376729314; Wed, 18 Oct 2023 15:02:49 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qtEVn-0002Kf-8V; Wed, 18 Oct 2023 17:55:31 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qtEVl-0002Gh-MN for qemu-devel@nongnu.org; Wed, 18 Oct 2023 17:55:29 -0400 Received: from mail-pf1-x430.google.com ([2607:f8b0:4864:20::430]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qtEVk-00058J-3w for qemu-devel@nongnu.org; Wed, 18 Oct 2023 17:55:29 -0400 Received: by mail-pf1-x430.google.com with SMTP id d2e1a72fcca58-6bd73395bceso124875b3a.0 for ; Wed, 18 Oct 2023 14:55:27 -0700 (PDT) Received: from stoup.. ([71.212.149.95]) by smtp.gmail.com with ESMTPSA id r15-20020aa7962f000000b006889348ba6esm3796263pfg.127.2023.10.18.14.55.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Oct 2023 14:55:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1697666127; x=1698270927; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=IfXXjPSCAekTKnfIpCckOL6yHpkL7tvWXEcAjeu6hPU=; b=Jv1wp4dy/uMbbKRKlcXmBIXFn8ZmG7/7xM7twHvg5FN9fQCH3D0U5SESPRUd02aBI1 z5+mymZr/YCX/E/dGiGdcX8ObZ8x7pUEqhm2i2kSz0D6KdAOrooRBPSD8zAc2LReRrb9 zGUVEFpQRDKDangngRz9tY4YruZYzsYQAfPus3NIhwSKhYGEbhOHDNZqsVwnQJovdgIw 7bZwCIbPAJXFG93SEI75lb6/NNfXGa0P5uwLEvGyLlm8BSgdwmKW9hbkJuAsN11vXGe6 UsvdeU/F/Sues5eotk+A2G9TAZEAFmIRZdYmBOze3WIWI+Uc0mThyLaYt4g0cu2q3P3D BLFw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697666127; x=1698270927; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=IfXXjPSCAekTKnfIpCckOL6yHpkL7tvWXEcAjeu6hPU=; b=JH1/ZNq1vw2pYbZiM0ftEFFAffcNMwnRBwqWwc0msKKv1XmEcfGa7gy6VShks6Bclh Wmv4UE4AfH2xa2oYMZEVlQn3NJFbevs/QPpDVNtbnYU9BHYY9p35ewxL0xAqpkpeX4Y2 pk9ghIr7k7Tn3tjAUb3jUapOP8EUG63PXIq2GRMFG5RykDp+plCp9M4i8ACCvwZAZH+x vkAASC2k0p4JisrswXV7rcbj483yHoTT0l8/jiKhvSAOKLb+3mcD3ymcxr6nwEixzU0p A7eSN3JSTVIMKqzYbAB8hvodxAlBcRfJ39u/NSBlW+hpCxOUHONpTWuSFEHfuEKghwyJ e1sw== X-Gm-Message-State: AOJu0YwoHQs1E7qPQDESl+DTEkEErCoa/o2Q9G0aJgl/RsN3K1+Txgb/ LKjVAWTPukD0x7x3U4Vy2v8EJU7ujuyluFp0/2k= X-Google-Smtp-Source: AGHT+IEf0qS3Knw3NMn/ddcwS75SfDemZxsP5NTyw4vXtCcN0EKDeyY9y5too4+bMvCxMEPW/o5fYA== X-Received: by 2002:a05:6a00:2789:b0:68a:5cf8:dae4 with SMTP id bd9-20020a056a00278900b0068a5cf8dae4mr168682pfb.3.1697666126834; Wed, 18 Oct 2023 14:55:26 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH 58/61] target/hppa: Fix interruption based on default PSW Date: Wed, 18 Oct 2023 14:51:32 -0700 Message-Id: <20231018215135.1561375-59-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231018215135.1561375-1-richard.henderson@linaro.org> References: <20231018215135.1561375-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::430; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697666571102100003 Content-Type: text/plain; charset="utf-8" From: Helge Deller The default PSW is set by the operating system with the PDC_PSW firmware call. Use that setting to decide if wide mode is to be enabled for interruptions and EIRR usage. Signed-off-by: Helge Deller Reviewed-by: Richard Henderson Signed-off-by: Richard Henderson --- target/hppa/cpu.h | 2 ++ target/hppa/int_helper.c | 17 +++++++++++++---- 2 files changed, 15 insertions(+), 4 deletions(-) diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 5ce05046c0..5c7fddbc2b 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -124,6 +124,8 @@ #define PSW_SM_W 0x200 /* PA2.0 only : Enable Wide Mode */ =20 #define CR_RC 0 +#define CR_PSW_DEFAULT 6 /* see SeaBIOS PDC_PSW firmware call */ +#define PDC_PSW_WIDE_BIT 2 #define CR_PID1 8 #define CR_PID2 9 #define CR_PID3 12 diff --git a/target/hppa/int_helper.c b/target/hppa/int_helper.c index f355c4c76b..021f410bef 100644 --- a/target/hppa/int_helper.c +++ b/target/hppa/int_helper.c @@ -52,9 +52,16 @@ static void io_eir_write(void *opaque, hwaddr addr, uint64_t data, unsigned size) { HPPACPU *cpu =3D opaque; - int le_bit =3D ~data & 31; + int widthm1 =3D 31; + int le_bit; =20 - cpu->env.cr[CR_EIRR] |=3D (target_ulong)1 << le_bit; + /* The default PSW.W controls the width of EIRR. */ + if (cpu->is_pa20 && cpu->env.cr[CR_PSW_DEFAULT] & PDC_PSW_WIDE_BIT) { + widthm1 =3D 63; + } + le_bit =3D ~data & widthm1; + + cpu->env.cr[CR_EIRR] |=3D 1ull << le_bit; eval_interrupt(cpu); } =20 @@ -104,8 +111,10 @@ void hppa_cpu_do_interrupt(CPUState *cs) /* step 1 */ env->cr[CR_IPSW] =3D old_psw =3D cpu_hppa_get_psw(env); =20 - /* step 2 -- note PSW_W =3D=3D 0 for !HPPA64. */ - cpu_hppa_put_psw(env, PSW_W | (i =3D=3D EXCP_HPMC ? PSW_M : 0)); + /* step 2 -- Note PSW_W is masked out again for pa1.x */ + cpu_hppa_put_psw(env, + (env->cr[CR_PSW_DEFAULT] & PDC_PSW_WIDE_BIT ? PSW_W := 0) | + (i =3D=3D EXCP_HPMC ? PSW_M : 0)); =20 /* step 3 */ env->cr[CR_IIASQ] =3D iasq_f >> 32; --=20 2.34.1