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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::430; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697666775782100003 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/hppa/insns.decode | 6 ++- target/hppa/translate.c | 79 ++++++++++++++++++++++++++++------------ 2 files changed, 60 insertions(+), 25 deletions(-) diff --git a/target/hppa/insns.decode b/target/hppa/insns.decode index 7b51f39b9e..6f0c3f6ea5 100644 --- a/target/hppa/insns.decode +++ b/target/hppa/insns.decode @@ -332,8 +332,10 @@ addbi 101011 ..... ..... ... ........... . .= @rib_cf f=3D1 # Shift, Extract, Deposit #### =20 -shrpw_sar 110100 r2:5 r1:5 c:3 00 0 00000 t:5 -shrpw_imm 110100 r2:5 r1:5 c:3 01 0 cpos:5 t:5 +shrp_sar 110100 r2:5 r1:5 c:3 00 0 d:1 0000 t:5 +shrp_imm 110100 r2:5 r1:5 c:3 01 0 cpos:5 t:5 d=3D0 +shrp_imm 110100 r2:5 r1:5 c:3 0. 1 ..... t:5 \ + d=3D1 cpos=3D%cpos6_11 =20 extr_sar 110100 r:5 t:5 c:3 10 se:1 00 000 ..... d=3D0 len=3D= %len5 extr_sar 110100 r:5 t:5 c:3 10 se:1 1. 000 ..... d=3D1 len=3D= %len6_8 diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 974ed558d7..a23c44e3d6 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -3258,32 +3258,56 @@ static bool trans_movbi(DisasContext *ctx, arg_movb= i *a) return do_cbranch(ctx, a->disp, a->n, &cond); } =20 -static bool trans_shrpw_sar(DisasContext *ctx, arg_shrpw_sar *a) +static bool trans_shrp_sar(DisasContext *ctx, arg_shrp_sar *a) { - TCGv_reg dest; + TCGv_reg dest, tmp; =20 + if (!ctx->is_pa20 && a->d) { + return false; + } if (a->c) { nullify_over(ctx); } =20 dest =3D dest_gpr(ctx, a->t); if (a->r1 =3D=3D 0) { - tcg_gen_ext32u_reg(dest, load_gpr(ctx, a->r2)); - tcg_gen_shr_reg(dest, dest, cpu_sar); + if (a->d) { + tcg_gen_shr_reg(dest, dest, cpu_sar); + } else { + tcg_gen_ext32u_reg(dest, load_gpr(ctx, a->r2)); + tmp =3D tcg_temp_new(); + tcg_gen_andi_reg(tmp, cpu_sar, 31); + tcg_gen_shr_reg(dest, dest, tmp); + } } else if (a->r1 =3D=3D a->r2) { - TCGv_i32 t32 =3D tcg_temp_new_i32(); - TCGv_i32 s32 =3D tcg_temp_new_i32(); + if (a->d) { + tcg_gen_rotr_reg(dest, load_gpr(ctx, a->r2), cpu_sar); + } else { + TCGv_i32 t32 =3D tcg_temp_new_i32(); + TCGv_i32 s32 =3D tcg_temp_new_i32(); =20 - tcg_gen_trunc_reg_i32(t32, load_gpr(ctx, a->r2)); - tcg_gen_trunc_reg_i32(s32, cpu_sar); - tcg_gen_rotr_i32(t32, t32, s32); - tcg_gen_extu_i32_reg(dest, t32); + tcg_gen_trunc_reg_i32(t32, load_gpr(ctx, a->r2)); + tcg_gen_trunc_reg_i32(s32, cpu_sar); + tcg_gen_andi_i32(s32, s32, 31); + tcg_gen_rotr_i32(t32, t32, s32); + tcg_gen_extu_i32_reg(dest, t32); + } + } else if (a->d) { + TCGv_reg t =3D tcg_temp_new(); + TCGv_reg n =3D tcg_temp_new(); + + tcg_gen_xori_reg(n, cpu_sar, 63); + tcg_gen_shl_reg(t, load_gpr(ctx, a->r2), n); + tcg_gen_shli_reg(t, t, 1); + tcg_gen_shr_reg(dest, load_gpr(ctx, a->r1), cpu_sar); + tcg_gen_or_reg(dest, dest, t); } else { TCGv_i64 t =3D tcg_temp_new_i64(); TCGv_i64 s =3D tcg_temp_new_i64(); =20 tcg_gen_concat_reg_i64(t, load_gpr(ctx, a->r2), load_gpr(ctx, a->r= 1)); tcg_gen_extu_reg_i64(s, cpu_sar); + tcg_gen_andi_i64(s, s, 31); tcg_gen_shr_i64(t, t, s); tcg_gen_trunc_i64_reg(dest, t); } @@ -3297,31 +3321,40 @@ static bool trans_shrpw_sar(DisasContext *ctx, arg_= shrpw_sar *a) return nullify_end(ctx); } =20 -static bool trans_shrpw_imm(DisasContext *ctx, arg_shrpw_imm *a) +static bool trans_shrp_imm(DisasContext *ctx, arg_shrp_imm *a) { - unsigned sa =3D 31 - a->cpos; + unsigned width, sa; TCGv_reg dest, t2; =20 + if (!ctx->is_pa20 && a->d) { + return false; + } if (a->c) { nullify_over(ctx); } =20 + width =3D a->d ? 64 : 32; + sa =3D width - 1 - a->cpos; + dest =3D dest_gpr(ctx, a->t); t2 =3D load_gpr(ctx, a->r2); if (a->r1 =3D=3D 0) { - tcg_gen_extract_reg(dest, t2, sa, 32 - sa); - } else if (TARGET_REGISTER_BITS =3D=3D 32) { + tcg_gen_extract_reg(dest, t2, sa, width - sa); + } else if (width =3D=3D TARGET_REGISTER_BITS) { tcg_gen_extract2_reg(dest, t2, cpu_gr[a->r1], sa); - } else if (a->r1 =3D=3D a->r2) { - TCGv_i32 t32 =3D tcg_temp_new_i32(); - tcg_gen_trunc_reg_i32(t32, t2); - tcg_gen_rotri_i32(t32, t32, sa); - tcg_gen_extu_i32_reg(dest, t32); } else { - TCGv_i64 t64 =3D tcg_temp_new_i64(); - tcg_gen_concat_reg_i64(t64, t2, cpu_gr[a->r1]); - tcg_gen_shri_i64(t64, t64, sa); - tcg_gen_trunc_i64_reg(dest, t64); + assert(!a->d); + if (a->r1 =3D=3D a->r2) { + TCGv_i32 t32 =3D tcg_temp_new_i32(); + tcg_gen_trunc_reg_i32(t32, t2); + tcg_gen_rotri_i32(t32, t32, sa); + tcg_gen_extu_i32_reg(dest, t32); + } else { + TCGv_i64 t64 =3D tcg_temp_new_i64(); + tcg_gen_concat_reg_i64(t64, t2, cpu_gr[a->r1]); + tcg_gen_shri_i64(t64, t64, sa); + tcg_gen_trunc_i64_reg(dest, t64); + } } save_gpr(ctx, a->t, dest); =20 --=20 2.34.1