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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id w17-20020a63f511000000b005b61a024ec7sm2176380pgh.74.2023.10.18.14.51.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Oct 2023 14:51:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1697665915; x=1698270715; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=io7/0k/pOO+TKp7Ec9Fj4OHEiClXaVK9yG3Lda49zh8=; b=Zr2PzKBNK44CINttQlE5jN5RD74XF9JTJpe55i1/Af8yuM90jY570FLWFN2VOiH/wi CR/L0LyGcB7vposOfVTWh+c9lC3CIEha8ggO0t0ED20kBznrbk6RER4bWH4YqT73x4zS JAtoEu9zUGDZStxUDuaLi4MQA4bXrjLi6rSf38/XJ/Sfuo1MnK2w5PsbQeXbfk95MErR K+TfKnTqEVTjKd6cpGjHaA7xrgiKvfofoGZ3kIzFcafu0AD6srknCu5zjiYcPkkmsjNe e5lS1Jdl1/+vgppJSy4y9dj06JjUlV7ATONOjnCcdewHbLZaCqRU4n8BbrfwWvCnh2u5 2YTA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697665915; x=1698270715; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=io7/0k/pOO+TKp7Ec9Fj4OHEiClXaVK9yG3Lda49zh8=; b=uYo4up3ApLrtJwE6u9WqHqEp/XCGnUjPBdtmZWtCUIR8n3/oj1YISpMw/IO+HbHr6d 7lsTHJTYZig+m/gRzRC8oPNJJx/W7oGrzP74CeFzWcgBpUVJrODHAA2OtVh8Gk6pt16D jl2ombI3uDi5wa1wnuUyLJI1zhMBZc7ouCBSkX7/JDdMSu/6S3y0T+HhltAWLK6qFFDg xFygFuVtzdK6TMl+HXBvGX1XW6JV20gLFAMcDgOKF599D7ZLsnBXRPc+/r5KlYgukoo2 MI75AMn6A6NSzNbS2kZIl3CGKjn4bDTdcSwTXIPxUvBa7IBhws5rs3iiAdoXYeZZIAGA LogA== X-Gm-Message-State: AOJu0YwnCYhDX+F/2oN2HoY2PHmtgZWhVDxMaWljmITy1lye1CUz5hlz 05bK/5DNA17KXO3AM7jy8X6LBgrZvKmone+bbQM= X-Google-Smtp-Source: AGHT+IEZ41v1fhC8JMM4JZ7zHR4YWf/tJNwSFXgmFDf+PNEJYCUcuwEG8VotdyY5VKvzP4xwyYe1iA== X-Received: by 2002:a05:6871:6183:b0:1e9:a8ff:67e8 with SMTP id rb3-20020a056871618300b001e9a8ff67e8mr608688oab.50.1697665914999; Wed, 18 Oct 2023 14:51:54 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH 22/61] target/hppa: Pass d to do_cond Date: Wed, 18 Oct 2023 14:50:56 -0700 Message-Id: <20231018215135.1561375-23-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231018215135.1561375-1-richard.henderson@linaro.org> References: <20231018215135.1561375-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:4860:4864:20::2a; envelope-from=richard.henderson@linaro.org; helo=mail-oa1-x2a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697666088633100001 Content-Type: text/plain; charset="utf-8" Hoist the resolution of d up one level above do_cond. Signed-off-by: Richard Henderson --- target/hppa/translate.c | 82 +++++++++++++++++++++++++++-------------- 1 file changed, 54 insertions(+), 28 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index e2b692a6c5..d6edad9adb 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -814,7 +814,7 @@ static bool cond_need_cb(int c) /* Need extensions from TCGv_i32 to TCGv_reg. */ static bool cond_need_ext(DisasContext *ctx, bool d) { - return TARGET_REGISTER_BITS =3D=3D 64 && !d; + return TARGET_REGISTER_BITS =3D=3D 64 && !(ctx->is_pa20 && d); } =20 /* @@ -822,8 +822,8 @@ static bool cond_need_ext(DisasContext *ctx, bool d) * the Parisc 1.1 Architecture Reference Manual for details. */ =20 -static DisasCond do_cond(unsigned cf, TCGv_reg res, - TCGv_reg cb_msb, TCGv_reg sv) +static DisasCond do_cond(DisasContext *ctx, unsigned cf, bool d, + TCGv_reg res, TCGv_reg cb_msb, TCGv_reg sv) { DisasCond cond; TCGv_reg tmp; @@ -833,11 +833,19 @@ static DisasCond do_cond(unsigned cf, TCGv_reg res, cond =3D cond_make_f(); break; case 1: /* =3D / <> (Z / !Z) */ + if (cond_need_ext(ctx, d)) { + tmp =3D tcg_temp_new(); + tcg_gen_ext32u_reg(tmp, res); + res =3D tmp; + } cond =3D cond_make_0(TCG_COND_EQ, res); break; case 2: /* < / >=3D (N ^ V / !(N ^ V) */ tmp =3D tcg_temp_new(); tcg_gen_xor_reg(tmp, res, sv); + if (cond_need_ext(ctx, d)) { + tcg_gen_ext32s_reg(tmp, tmp); + } cond =3D cond_make_0_tmp(TCG_COND_LT, tmp); break; case 3: /* <=3D / > (N ^ V) | Z / !((N ^ V) | Z) */ @@ -852,20 +860,35 @@ static DisasCond do_cond(unsigned cf, TCGv_reg res, */ tmp =3D tcg_temp_new(); tcg_gen_eqv_reg(tmp, res, sv); - tcg_gen_sari_reg(tmp, tmp, TARGET_REGISTER_BITS - 1); - tcg_gen_and_reg(tmp, tmp, res); + if (cond_need_ext(ctx, d)) { + tcg_gen_sextract_reg(tmp, tmp, 31, 1); + tcg_gen_and_reg(tmp, tmp, res); + tcg_gen_ext32u_reg(tmp, tmp); + } else { + tcg_gen_sari_reg(tmp, tmp, TARGET_REGISTER_BITS - 1); + tcg_gen_and_reg(tmp, tmp, res); + } cond =3D cond_make_0_tmp(TCG_COND_EQ, tmp); break; case 4: /* NUV / UV (!C / C) */ + /* Only bit 0 of cb_msb is ever set. */ cond =3D cond_make_0(TCG_COND_EQ, cb_msb); break; case 5: /* ZNV / VNZ (!C | Z / C & !Z) */ tmp =3D tcg_temp_new(); tcg_gen_neg_reg(tmp, cb_msb); tcg_gen_and_reg(tmp, tmp, res); + if (cond_need_ext(ctx, d)) { + tcg_gen_ext32u_reg(tmp, tmp); + } cond =3D cond_make_0_tmp(TCG_COND_EQ, tmp); break; case 6: /* SV / NSV (V / !V) */ + if (cond_need_ext(ctx, d)) { + tmp =3D tcg_temp_new(); + tcg_gen_ext32s_reg(tmp, sv); + sv =3D tmp; + } cond =3D cond_make_0(TCG_COND_LT, sv); break; case 7: /* OD / EV */ @@ -887,10 +910,11 @@ static DisasCond do_cond(unsigned cf, TCGv_reg res, can use the inputs directly. This can allow other computation to be deleted as unused. */ =20 -static DisasCond do_sub_cond(unsigned cf, TCGv_reg res, +static DisasCond do_sub_cond(DisasContext *ctx, unsigned cf, TCGv_reg res, TCGv_reg in1, TCGv_reg in2, TCGv_reg sv) { DisasCond cond; + bool d =3D false; =20 switch (cf >> 1) { case 1: /* =3D / <> */ @@ -909,7 +933,7 @@ static DisasCond do_sub_cond(unsigned cf, TCGv_reg res, cond =3D cond_make(TCG_COND_LEU, in1, in2); break; default: - return do_cond(cf, res, NULL, sv); + return do_cond(ctx, cf, d, res, NULL, sv); } if (cf & 1) { cond.c =3D tcg_invert_cond(cond.c); @@ -927,8 +951,10 @@ static DisasCond do_sub_cond(unsigned cf, TCGv_reg res, * how cases c=3D{2,3} are treated. */ =20 -static DisasCond do_log_cond(unsigned cf, TCGv_reg res) +static DisasCond do_log_cond(DisasContext *ctx, unsigned cf, TCGv_reg res) { + bool d =3D false; + switch (cf) { case 0: /* never */ case 9: /* undef, C */ @@ -957,7 +983,7 @@ static DisasCond do_log_cond(unsigned cf, TCGv_reg res) =20 case 14: /* OD */ case 15: /* EV */ - return do_cond(cf, res, NULL, NULL); + return do_cond(ctx, cf, d, res, NULL, NULL); =20 default: g_assert_not_reached(); @@ -966,7 +992,7 @@ static DisasCond do_log_cond(unsigned cf, TCGv_reg res) =20 /* Similar, but for shift/extract/deposit conditions. */ =20 -static DisasCond do_sed_cond(unsigned orig, TCGv_reg res) +static DisasCond do_sed_cond(DisasContext *ctx, unsigned orig, TCGv_reg re= s) { unsigned c, f; =20 @@ -979,7 +1005,7 @@ static DisasCond do_sed_cond(unsigned orig, TCGv_reg r= es) } f =3D (orig & 4) / 4; =20 - return do_log_cond(c * 2 + f, res); + return do_log_cond(ctx, c * 2 + f, res); } =20 /* Similar, but for unit conditions. */ @@ -1151,7 +1177,7 @@ static void do_add(DisasContext *ctx, unsigned rt, TC= Gv_reg in1, } =20 /* Emit any conditional trap before any writeback. */ - cond =3D do_cond(cf, dest, cb_cond, sv); + cond =3D do_cond(ctx, cf, d, dest, cb_cond, sv); if (is_tc) { tmp =3D tcg_temp_new(); tcg_gen_setcond_reg(cond.c, tmp, cond.a0, cond.a1); @@ -1241,9 +1267,9 @@ static void do_sub(DisasContext *ctx, unsigned rt, TC= Gv_reg in1, =20 /* Compute the condition. We cannot use the special case for borrow. = */ if (!is_b) { - cond =3D do_sub_cond(cf, dest, in1, in2, sv); + cond =3D do_sub_cond(ctx, cf, dest, in1, in2, sv); } else { - cond =3D do_cond(cf, dest, get_carry(ctx, d, cb, cb_msb), sv); + cond =3D do_cond(ctx, cf, d, dest, get_carry(ctx, d, cb, cb_msb), = sv); } =20 /* Emit any conditional trap before any writeback. */ @@ -1306,7 +1332,7 @@ static void do_cmpclr(DisasContext *ctx, unsigned rt,= TCGv_reg in1, } =20 /* Form the condition for the compare. */ - cond =3D do_sub_cond(cf, dest, in1, in2, sv); + cond =3D do_sub_cond(ctx, cf, dest, in1, in2, sv); =20 /* Clear. */ tcg_gen_movi_reg(dest, 0); @@ -1330,7 +1356,7 @@ static void do_log(DisasContext *ctx, unsigned rt, TC= Gv_reg in1, /* Install the new nullification. */ cond_free(&ctx->null_cond); if (cf) { - ctx->null_cond =3D do_log_cond(cf, dest); + ctx->null_cond =3D do_log_cond(ctx, cf, dest); } } =20 @@ -2796,7 +2822,7 @@ static bool trans_ds(DisasContext *ctx, arg_rrr_cf *a) /* ??? The lshift is supposed to contribute to overflow. */ sv =3D do_add_sv(ctx, dest, add1, add2); } - ctx->null_cond =3D do_cond(a->cf, dest, cout, sv); + ctx->null_cond =3D do_cond(ctx, a->cf, false, dest, cout, sv); } =20 return nullify_end(ctx); @@ -3013,7 +3039,7 @@ static bool do_cmpb(DisasContext *ctx, unsigned r, TC= Gv_reg in1, sv =3D do_sub_sv(ctx, dest, in1, in2); } =20 - cond =3D do_sub_cond(c * 2 + f, dest, in1, in2, sv); + cond =3D do_sub_cond(ctx, c * 2 + f, dest, in1, in2, sv); return do_cbranch(ctx, disp, n, &cond); } =20 @@ -3057,7 +3083,7 @@ static bool do_addb(DisasContext *ctx, unsigned r, TC= Gv_reg in1, sv =3D do_add_sv(ctx, dest, in1, in2); } =20 - cond =3D do_cond(c * 2 + f, dest, cb_cond, sv); + cond =3D do_cond(ctx, c * 2 + f, d, dest, cb_cond, sv); save_gpr(ctx, r, dest); return do_cbranch(ctx, disp, n, &cond); } @@ -3128,7 +3154,7 @@ static bool trans_movb(DisasContext *ctx, arg_movb *a) tcg_gen_mov_reg(dest, cpu_gr[a->r1]); } =20 - cond =3D do_sed_cond(a->c, dest); + cond =3D do_sed_cond(ctx, a->c, dest); return do_cbranch(ctx, a->disp, a->n, &cond); } =20 @@ -3142,7 +3168,7 @@ static bool trans_movbi(DisasContext *ctx, arg_movbi = *a) dest =3D dest_gpr(ctx, a->r); tcg_gen_movi_reg(dest, a->i); =20 - cond =3D do_sed_cond(a->c, dest); + cond =3D do_sed_cond(ctx, a->c, dest); return do_cbranch(ctx, a->disp, a->n, &cond); } =20 @@ -3180,7 +3206,7 @@ static bool trans_shrpw_sar(DisasContext *ctx, arg_sh= rpw_sar *a) /* Install the new nullification. */ cond_free(&ctx->null_cond); if (a->c) { - ctx->null_cond =3D do_sed_cond(a->c, dest); + ctx->null_cond =3D do_sed_cond(ctx, a->c, dest); } return nullify_end(ctx); } @@ -3216,7 +3242,7 @@ static bool trans_shrpw_imm(DisasContext *ctx, arg_sh= rpw_imm *a) /* Install the new nullification. */ cond_free(&ctx->null_cond); if (a->c) { - ctx->null_cond =3D do_sed_cond(a->c, dest); + ctx->null_cond =3D do_sed_cond(ctx, a->c, dest); } return nullify_end(ctx); } @@ -3250,7 +3276,7 @@ static bool trans_extrw_sar(DisasContext *ctx, arg_ex= trw_sar *a) /* Install the new nullification. */ cond_free(&ctx->null_cond); if (a->c) { - ctx->null_cond =3D do_sed_cond(a->c, dest); + ctx->null_cond =3D do_sed_cond(ctx, a->c, dest); } return nullify_end(ctx); } @@ -3277,7 +3303,7 @@ static bool trans_extrw_imm(DisasContext *ctx, arg_ex= trw_imm *a) /* Install the new nullification. */ cond_free(&ctx->null_cond); if (a->c) { - ctx->null_cond =3D do_sed_cond(a->c, dest); + ctx->null_cond =3D do_sed_cond(ctx, a->c, dest); } return nullify_end(ctx); } @@ -3314,7 +3340,7 @@ static bool trans_depwi_imm(DisasContext *ctx, arg_de= pwi_imm *a) /* Install the new nullification. */ cond_free(&ctx->null_cond); if (a->c) { - ctx->null_cond =3D do_sed_cond(a->c, dest); + ctx->null_cond =3D do_sed_cond(ctx, a->c, dest); } return nullify_end(ctx); } @@ -3344,7 +3370,7 @@ static bool trans_depw_imm(DisasContext *ctx, arg_dep= w_imm *a) /* Install the new nullification. */ cond_free(&ctx->null_cond); if (a->c) { - ctx->null_cond =3D do_sed_cond(a->c, dest); + ctx->null_cond =3D do_sed_cond(ctx, a->c, dest); } return nullify_end(ctx); } @@ -3381,7 +3407,7 @@ static bool do_depw_sar(DisasContext *ctx, unsigned r= t, unsigned c, /* Install the new nullification. */ cond_free(&ctx->null_cond); if (c) { - ctx->null_cond =3D do_sed_cond(c, dest); + ctx->null_cond =3D do_sed_cond(ctx, c, dest); } return nullify_end(ctx); } --=20 2.34.1