From nobody Wed Nov 27 18:51:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1697666400; cv=none; d=zohomail.com; s=zohoarc; b=Pv1BJnrWUZ9e1nwHc7i67783qNBgUSgCoIH7+3bbtnTnFK0M60WeXxA723ejMEcza55832h0i7MRWWQsZw/SztAOkJMc/YUxY/S4NVuhgolo+4ZiyyzSAdqh6PEsli0m/aTEU0QabTRaja6/d+0xfQBRKK5qGaVMFmGqM/xMaAo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1697666400; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=hkIbB3zmI08zQqo8JvI15EoPXprMPyQ2OgXzm/sTzaE=; b=nYpuxjJnrA0QWFOrog75K91qVWFhYa0K6WxW0+2mbS5FE3W6A3TUrru3osFUkWQX4qX+uTCRJWE2uhAdqf5UkzOd9nG7lI0SqdRoFj7BXlhUy0sDAstPSASmkAfkcJjQXcVqRN5wKCkriiWKrD80jJhTqu3EwzSjam5WTAI5k5I= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1697666400718647.0442359967258; Wed, 18 Oct 2023 15:00:00 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qtESA-0000rL-9e; Wed, 18 Oct 2023 17:51:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qtES5-0000it-Tb for qemu-devel@nongnu.org; Wed, 18 Oct 2023 17:51:42 -0400 Received: from mail-oo1-xc2f.google.com ([2607:f8b0:4864:20::c2f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qtES3-0004Mi-Lq for qemu-devel@nongnu.org; Wed, 18 Oct 2023 17:51:41 -0400 Received: by mail-oo1-xc2f.google.com with SMTP id 006d021491bc7-57b5f0d658dso4275582eaf.0 for ; Wed, 18 Oct 2023 14:51:38 -0700 (PDT) Received: from stoup.. ([71.212.149.95]) by smtp.gmail.com with ESMTPSA id w17-20020a63f511000000b005b61a024ec7sm2176380pgh.74.2023.10.18.14.51.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Oct 2023 14:51:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1697665897; x=1698270697; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=hkIbB3zmI08zQqo8JvI15EoPXprMPyQ2OgXzm/sTzaE=; b=C0pxWsAMx0xMZpriRBPtpt6F2xoLOTokrT6GVDvIDnBJcoURHZ7yAUnTBBX79trORM Bk1g/ipdxpGsHABeH7Dof5Mmh9kBKngf+kTNrm9rQoMVL8yHOuUpyNpGsxdO2qaNHrdv 96l1bE8MFoRfoh888c+I5xp36hQ/heASfihyWapdsaW/z6oBkqoaMfdcFLGjHgbqOrlA D3PHGszWTYnBtaBO/axCBpD5xjhr8lAZJKQO3kNXoFo9PtNwlq5Zqgelj6Y9uyIMGbzM r8WAVC3+aYtQj3SnoXr4FqOc5w0BkSQLg/wdoo289cnZJ/uTXQ6C2Sj5zWG49xqOo/0B A4EA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697665897; x=1698270697; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=hkIbB3zmI08zQqo8JvI15EoPXprMPyQ2OgXzm/sTzaE=; b=FPsJE6SDDObhVToiaCRA6erm4A0zl13Rf+yhtACRt4lvMW+FVcg8+MezFHDxxGPhiU ggdGc1zsay1eD2o0PA6cBkZf5dZ4oxbqq0SqVJ16kypqzwMtICyKZVVc2e2tzzazZhSn lIr8e18LBMjOx1Ycsgf23jVc/vJP7noPzEBLOx2kRbpGU16h8PavrjhfvOh09O8EZTuK x49Hdd0I5UeIPYqVFYgm8xnfR9sUi8kx4hFX22u+97I8U+FWNPAyIEoF4UaxjEeW9t+Z JBrB9EQw5WQF9kBZvqJ3W6CCoeKHTaA6Oz6C0gLO2kuxaJxBFUkKK4OVi4TsiSJ9fLYk 6Bhg== X-Gm-Message-State: AOJu0YwVLQFn1BPvPjKsxTfOMKkbAOIsGvuHHgf3knfnEWUcyLMuY5JI 8kF9fuCJQcBMOMZScRvR+zxZMEc5fIb+itSOiio= X-Google-Smtp-Source: AGHT+IEM4bpcAkiUdoZgnOSLxLBYZkIDTw8zSjc3U1qbDkNHfHuf5QP4yazFqw2hCByosjlk4beojQ== X-Received: by 2002:a05:6359:d14:b0:14a:ddb8:9a12 with SMTP id gp20-20020a0563590d1400b0014addb89a12mr276183rwb.6.1697665897576; Wed, 18 Oct 2023 14:51:37 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH 01/61] include/hw/elf: Remove truncating signed casts Date: Wed, 18 Oct 2023 14:50:35 -0700 Message-Id: <20231018215135.1561375-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231018215135.1561375-1-richard.henderson@linaro.org> References: <20231018215135.1561375-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::c2f; envelope-from=richard.henderson@linaro.org; helo=mail-oo1-xc2f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697666402287100009 Content-Type: text/plain; charset="utf-8" There's nothing about elf that specifically requires signed vs unsigned. This is very much a target-specific preference. In the meantime, casting low and high from uint64_t back to Elf_SWord to uint64_t discards high bits that might have been set by translate_fn. Signed-off-by: Richard Henderson --- include/hw/elf_ops.h | 17 ++++++++++------- 1 file changed, 10 insertions(+), 7 deletions(-) diff --git a/include/hw/elf_ops.h b/include/hw/elf_ops.h index dffb0e73d2..0a5c258fe6 100644 --- a/include/hw/elf_ops.h +++ b/include/hw/elf_ops.h @@ -385,10 +385,11 @@ static ssize_t glue(load_elf, SZ)(const char *name, i= nt fd, } =20 if (pflags) { - *pflags =3D (elf_word)ehdr.e_flags; + *pflags =3D ehdr.e_flags; + } + if (pentry) { + *pentry =3D ehdr.e_entry; } - if (pentry) - *pentry =3D (uint64_t)(elf_sword)ehdr.e_entry; =20 glue(load_symbols, SZ)(&ehdr, fd, must_swab, clear_lsb, sym_cb); =20 @@ -610,10 +611,12 @@ static ssize_t glue(load_elf, SZ)(const char *name, i= nt fd, } } =20 - if (lowaddr) - *lowaddr =3D (uint64_t)(elf_sword)low; - if (highaddr) - *highaddr =3D (uint64_t)(elf_sword)high; + if (lowaddr) { + *lowaddr =3D low; + } + if (highaddr) { + *highaddr =3D high; + } ret =3D total_size; fail: if (mapped_file) { --=20 2.34.1 From nobody Wed Nov 27 18:51:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1697665994; cv=none; d=zohomail.com; s=zohoarc; b=c3cU2Nwk5K0rMyYoAaE0Ay173aKeu/4ntCjssEAk0U5uciw/M+kj7z5qlxZltVnSAhuRjUVKjWihYwNQVvQrK/AVaquZXb0Ukvdm6ywJluIixFXM6mdT24YB85IjjtO5IN/6tdrlTfXQmF2qma/bYQSZJwJBmCRKeF3/mwkmSoQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1697665994; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=23RI/mW6AMfApntB6AZBjNSIoZLAv2J5xj2sb88apLg=; b=Me4CwkMCYtAIl0bt4gsAKmJd5x/pm1KjaUfCs+i4xmPgLDIR38xqRGCiQqe2r8Qkw+MTOYrdduBThNdQavpkifw+oqwZvi/T1lH7SoMcojQZNl0zLaTwXt02BQieSZv/cnZx8nQFJQRdKRxZj8LC6v81IbmRRxmkAiGVBHso3/I= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1697665994043814.3980131344991; Wed, 18 Oct 2023 14:53:14 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qtESB-0000sR-2W; Wed, 18 Oct 2023 17:51:47 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qtES7-0000jD-8c for qemu-devel@nongnu.org; Wed, 18 Oct 2023 17:51:43 -0400 Received: from mail-pf1-x42e.google.com ([2607:f8b0:4864:20::42e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qtES4-0004Mu-GO for qemu-devel@nongnu.org; Wed, 18 Oct 2023 17:51:43 -0400 Received: by mail-pf1-x42e.google.com with SMTP id d2e1a72fcca58-6b87c1edfd5so4161605b3a.1 for ; Wed, 18 Oct 2023 14:51:39 -0700 (PDT) Received: from stoup.. ([71.212.149.95]) by smtp.gmail.com with ESMTPSA id w17-20020a63f511000000b005b61a024ec7sm2176380pgh.74.2023.10.18.14.51.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Oct 2023 14:51:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1697665898; x=1698270698; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=23RI/mW6AMfApntB6AZBjNSIoZLAv2J5xj2sb88apLg=; b=WXYP2C5IlICDiz/j4nUrYJO4uyAYtK4VcJ/RzmXYxxxAyiaTOnZD34aNdQ0rdmFUaU TMB3g+D4XvTuQ+hyS2tUVzxuaJFbyb8T81QKdH+FTsejLhBGqL17i4gpKtWMkw7ESDLi weDHptqQgpXnYtMfhub8fbiiRZ4n+AUh1FZ7B+QLrvX0ApWVpm4//c1lxN+vz7zj74dp OJZ/diez8oknA4a7DIp3tIHXSr4PcBRXhFzaanSsExewBfKv1gANkRW+UsqUfDWw4utU 95dAJNs8x196fsITI6OwPkkfKXdcCwZUbQqF6MDecTmizXdBO947kskN1Txi3uvnR37z R4jg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697665898; x=1698270698; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=23RI/mW6AMfApntB6AZBjNSIoZLAv2J5xj2sb88apLg=; b=wgOotSeSuo2W+SPpeqgmtihhnNeFX6dnhwls/lx0AhhIAkQE2bmVaJKJYcVaC8pw+g i83nZRfKFH5i5HmHdMnd3hKuI1RjA/y/ajKzJyoQN/ZzczAuTMVyg+A4sAgLdKBsJiMx V7KLichYmefgosp4xQcX6k/0vQmxLrexO5oJRx/+UZY9j/AmlOyLgs7SgWkl3uTmst6v IdJpWl71GH3zHKI+iagu8AQqqhnTpOcstFA013yWXKI2p+kCMvDcqwXr9YSAjhQL9h/E PXVD9CBbvT+7bSTIXGHpiilP73OvRCN1RoELjXVqivutzY2S0O/BmJpVcriJNKYQbtnB 8kuQ== X-Gm-Message-State: AOJu0YxM7pLJmgYI5wG5n+6Fnneq/w2jDcosX5fEuX5Jr1qIf1WsDbhN 4u7h/6BJaN1QhucElRNaZCrkyJxNWQ9GDbSN9yU= X-Google-Smtp-Source: AGHT+IEzf2Oo43gFUyxtxLCb2HpsO+LeWcOeTUwZXKC5Vbo4n5ZftfwMmq22BkUme81MEN/XCC7i3A== X-Received: by 2002:a05:6a00:1827:b0:690:d620:7804 with SMTP id y39-20020a056a00182700b00690d6207804mr407896pfa.13.1697665898520; Wed, 18 Oct 2023 14:51:38 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH 02/61] target/hppa: Remove get_temp Date: Wed, 18 Oct 2023 14:50:36 -0700 Message-Id: <20231018215135.1561375-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231018215135.1561375-1-richard.henderson@linaro.org> References: <20231018215135.1561375-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42e; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697665994322100001 Content-Type: text/plain; charset="utf-8" Replace with tcg_temp_new without recording into ctx. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/hppa/translate.c | 76 +++++++++++++++++------------------------ 1 file changed, 31 insertions(+), 45 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 9f3ba9f42f..3065fbf625 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -254,8 +254,7 @@ typedef struct DisasContext { target_ureg iaoq_n; TCGv_reg iaoq_n_var; =20 - int ntempr, ntempl; - TCGv_reg tempr[8]; + int ntempl; TCGv_tl templ[4]; =20 DisasCond null_cond; @@ -492,13 +491,6 @@ static void cond_free(DisasCond *cond) } } =20 -static TCGv_reg get_temp(DisasContext *ctx) -{ - unsigned i =3D ctx->ntempr++; - g_assert(i < ARRAY_SIZE(ctx->tempr)); - return ctx->tempr[i] =3D tcg_temp_new(); -} - #ifndef CONFIG_USER_ONLY static TCGv_tl get_temp_tl(DisasContext *ctx) { @@ -510,7 +502,7 @@ static TCGv_tl get_temp_tl(DisasContext *ctx) =20 static TCGv_reg load_const(DisasContext *ctx, target_sreg v) { - TCGv_reg t =3D get_temp(ctx); + TCGv_reg t =3D tcg_temp_new(); tcg_gen_movi_reg(t, v); return t; } @@ -518,7 +510,7 @@ static TCGv_reg load_const(DisasContext *ctx, target_sr= eg v) static TCGv_reg load_gpr(DisasContext *ctx, unsigned reg) { if (reg =3D=3D 0) { - TCGv_reg t =3D get_temp(ctx); + TCGv_reg t =3D tcg_temp_new(); tcg_gen_movi_reg(t, 0); return t; } else { @@ -529,7 +521,7 @@ static TCGv_reg load_gpr(DisasContext *ctx, unsigned re= g) static TCGv_reg dest_gpr(DisasContext *ctx, unsigned reg) { if (reg =3D=3D 0 || ctx->null_cond.c !=3D TCG_COND_NEVER) { - return get_temp(ctx); + return tcg_temp_new(); } else { return cpu_gr[reg]; } @@ -1071,7 +1063,7 @@ static DisasCond do_unit_cond(unsigned cf, TCGv_reg r= es, static TCGv_reg do_add_sv(DisasContext *ctx, TCGv_reg res, TCGv_reg in1, TCGv_reg in2) { - TCGv_reg sv =3D get_temp(ctx); + TCGv_reg sv =3D tcg_temp_new(); TCGv_reg tmp =3D tcg_temp_new(); =20 tcg_gen_xor_reg(sv, res, in1); @@ -1085,7 +1077,7 @@ static TCGv_reg do_add_sv(DisasContext *ctx, TCGv_reg= res, static TCGv_reg do_sub_sv(DisasContext *ctx, TCGv_reg res, TCGv_reg in1, TCGv_reg in2) { - TCGv_reg sv =3D get_temp(ctx); + TCGv_reg sv =3D tcg_temp_new(); TCGv_reg tmp =3D tcg_temp_new(); =20 tcg_gen_xor_reg(sv, res, in1); @@ -1108,20 +1100,20 @@ static void do_add(DisasContext *ctx, unsigned rt, = TCGv_reg in1, cb_msb =3D NULL; =20 if (shift) { - tmp =3D get_temp(ctx); + tmp =3D tcg_temp_new(); tcg_gen_shli_reg(tmp, in1, shift); in1 =3D tmp; } =20 if (!is_l || cond_need_cb(c)) { TCGv_reg zero =3D tcg_constant_reg(0); - cb_msb =3D get_temp(ctx); + cb_msb =3D tcg_temp_new(); tcg_gen_add2_reg(dest, cb_msb, in1, zero, in2, zero); if (is_c) { tcg_gen_add2_reg(dest, cb_msb, dest, cb_msb, cpu_psw_cb_msb, z= ero); } if (!is_l) { - cb =3D get_temp(ctx); + cb =3D tcg_temp_new(); tcg_gen_xor_reg(cb, in1, in2); tcg_gen_xor_reg(cb, cb, dest); } @@ -1414,11 +1406,11 @@ static void form_gva(DisasContext *ctx, TCGv_tl *pg= va, TCGv_reg *pofs, =20 /* Note that RX is mutually exclusive with DISP. */ if (rx) { - ofs =3D get_temp(ctx); + ofs =3D tcg_temp_new(); tcg_gen_shli_reg(ofs, cpu_gr[rx], scale); tcg_gen_add_reg(ofs, ofs, base); } else if (disp || modify) { - ofs =3D get_temp(ctx); + ofs =3D tcg_temp_new(); tcg_gen_addi_reg(ofs, base, disp); } else { ofs =3D base; @@ -1538,7 +1530,7 @@ static bool do_load(DisasContext *ctx, unsigned rt, u= nsigned rb, dest =3D dest_gpr(ctx, rt); } else { /* Make sure if RT =3D=3D RB, we see the result of the load. */ - dest =3D get_temp(ctx); + dest =3D tcg_temp_new(); } do_load_reg(ctx, dest, rb, rx, scale, disp, sp, modify, mop); save_gpr(ctx, rt, dest); @@ -1854,7 +1846,7 @@ static bool do_ibranch(DisasContext *ctx, TCGv_reg de= st, if (link !=3D 0) { copy_iaoq_entry(cpu_gr[link], ctx->iaoq_n, ctx->iaoq_n_var); } - next =3D get_temp(ctx); + next =3D tcg_temp_new(); tcg_gen_mov_reg(next, dest); if (is_n) { if (use_nullify_skip(ctx)) { @@ -1896,7 +1888,7 @@ static bool do_ibranch(DisasContext *ctx, TCGv_reg de= st, a1 =3D ctx->null_cond.a1; =20 tmp =3D tcg_temp_new(); - next =3D get_temp(ctx); + next =3D tcg_temp_new(); =20 copy_iaoq_entry(tmp, ctx->iaoq_n, ctx->iaoq_n_var); tcg_gen_movcond_reg(c, next, a0, a1, tmp, dest); @@ -1938,11 +1930,11 @@ static TCGv_reg do_ibranch_priv(DisasContext *ctx, = TCGv_reg offset) return offset; case 3: /* Privilege 3 is minimum and is never allowed to increase. */ - dest =3D get_temp(ctx); + dest =3D tcg_temp_new(); tcg_gen_ori_reg(dest, offset, 3); break; default: - dest =3D get_temp(ctx); + dest =3D tcg_temp_new(); tcg_gen_andi_reg(dest, offset, -4); tcg_gen_ori_reg(dest, dest, ctx->privilege); tcg_gen_movcond_reg(TCG_COND_GTU, dest, dest, offset, dest, offset= ); @@ -2104,7 +2096,7 @@ static bool trans_mfctl(DisasContext *ctx, arg_mfctl = *a) break; } =20 - tmp =3D get_temp(ctx); + tmp =3D tcg_temp_new(); tcg_gen_ld_reg(tmp, tcg_env, offsetof(CPUHPPAState, cr[ctl])); save_gpr(ctx, rt, tmp); =20 @@ -2177,7 +2169,7 @@ static bool trans_mtctl(DisasContext *ctx, arg_mtctl = *a) case CR_IIAOQ: /* FIXME: Respect PSW_Q bit */ /* The write advances the queue and stores to the back element. */ - tmp =3D get_temp(ctx); + tmp =3D tcg_temp_new(); tcg_gen_ld_reg(tmp, tcg_env, offsetof(CPUHPPAState, cr_back[ctl - CR_IIASQ])); tcg_gen_st_reg(tmp, tcg_env, offsetof(CPUHPPAState, cr[ctl])); @@ -2243,7 +2235,7 @@ static bool trans_rsm(DisasContext *ctx, arg_rsm *a) =20 nullify_over(ctx); =20 - tmp =3D get_temp(ctx); + tmp =3D tcg_temp_new(); tcg_gen_ld_reg(tmp, tcg_env, offsetof(CPUHPPAState, psw)); tcg_gen_andi_reg(tmp, tmp, ~a->i); gen_helper_swap_system_mask(tmp, tcg_env, tmp); @@ -2263,7 +2255,7 @@ static bool trans_ssm(DisasContext *ctx, arg_ssm *a) =20 nullify_over(ctx); =20 - tmp =3D get_temp(ctx); + tmp =3D tcg_temp_new(); tcg_gen_ld_reg(tmp, tcg_env, offsetof(CPUHPPAState, psw)); tcg_gen_ori_reg(tmp, tmp, a->i); gen_helper_swap_system_mask(tmp, tcg_env, tmp); @@ -2283,7 +2275,7 @@ static bool trans_mtsm(DisasContext *ctx, arg_mtsm *a) nullify_over(ctx); =20 reg =3D load_gpr(ctx, a->r); - tmp =3D get_temp(ctx); + tmp =3D tcg_temp_new(); gen_helper_swap_system_mask(tmp, tcg_env, reg); =20 /* Exit the TB to recognize new interrupts. */ @@ -2692,7 +2684,7 @@ static bool do_uaddcm(DisasContext *ctx, arg_rrr_cf *= a, bool is_tc) } tcg_r1 =3D load_gpr(ctx, a->r1); tcg_r2 =3D load_gpr(ctx, a->r2); - tmp =3D get_temp(ctx); + tmp =3D tcg_temp_new(); tcg_gen_not_reg(tmp, tcg_r2); do_unit(ctx, a->t, tcg_r1, tmp, a->cf, is_tc, tcg_gen_add_reg); return nullify_end(ctx); @@ -2714,7 +2706,7 @@ static bool do_dcor(DisasContext *ctx, arg_rr_cf *a, = bool is_i) =20 nullify_over(ctx); =20 - tmp =3D get_temp(ctx); + tmp =3D tcg_temp_new(); tcg_gen_shri_reg(tmp, cpu_psw_cb, 3); if (!is_i) { tcg_gen_not_reg(tmp, tmp); @@ -2866,7 +2858,7 @@ static bool trans_ldc(DisasContext *ctx, arg_ldst *a) if (a->m) { /* Base register modification. Make sure if RT =3D=3D RB, we see the result of the load. */ - dest =3D get_temp(ctx); + dest =3D tcg_temp_new(); } else { dest =3D dest_gpr(ctx, a->t); } @@ -2992,7 +2984,7 @@ static bool do_cmpb(DisasContext *ctx, unsigned r, TC= Gv_reg in1, DisasCond cond; =20 in2 =3D load_gpr(ctx, r); - dest =3D get_temp(ctx); + dest =3D tcg_temp_new(); =20 tcg_gen_sub_reg(dest, in1, in2); =20 @@ -3029,7 +3021,7 @@ static bool do_addb(DisasContext *ctx, unsigned r, TC= Gv_reg in1, cb_msb =3D NULL; =20 if (cond_need_cb(c)) { - cb_msb =3D get_temp(ctx); + cb_msb =3D tcg_temp_new(); tcg_gen_movi_reg(cb_msb, 0); tcg_gen_add2_reg(dest, cb_msb, in1, cb_msb, in2, cb_msb); } else { @@ -3388,7 +3380,7 @@ static bool trans_be(DisasContext *ctx, arg_be *a) nullify_over(ctx); #endif =20 - tmp =3D get_temp(ctx); + tmp =3D tcg_temp_new(); tcg_gen_addi_reg(tmp, load_gpr(ctx, a->b), a->disp); tmp =3D do_ibranch_priv(ctx, tmp); =20 @@ -3485,7 +3477,7 @@ static bool trans_b_gate(DisasContext *ctx, arg_b_gat= e *a) static bool trans_blr(DisasContext *ctx, arg_blr *a) { if (a->x) { - TCGv_reg tmp =3D get_temp(ctx); + TCGv_reg tmp =3D tcg_temp_new(); tcg_gen_shli_reg(tmp, load_gpr(ctx, a->x), 3); tcg_gen_addi_reg(tmp, tmp, ctx->iaoq_f + 8); /* The computation here never changes privilege level. */ @@ -3503,7 +3495,7 @@ static bool trans_bv(DisasContext *ctx, arg_bv *a) if (a->x =3D=3D 0) { dest =3D load_gpr(ctx, a->b); } else { - dest =3D get_temp(ctx); + dest =3D tcg_temp_new(); tcg_gen_shli_reg(dest, load_gpr(ctx, a->x), 3); tcg_gen_add_reg(dest, dest, load_gpr(ctx, a->b)); } @@ -3834,7 +3826,7 @@ static bool trans_ftest(DisasContext *ctx, arg_ftest = *a) =20 nullify_over(ctx); =20 - t =3D get_temp(ctx); + t =3D tcg_temp_new(); tcg_gen_ld32u_reg(t, tcg_env, offsetof(CPUHPPAState, fr0_shadow)); =20 if (a->y =3D=3D 1) { @@ -4089,9 +4081,7 @@ static void hppa_tr_init_disas_context(DisasContextBa= se *dcbase, CPUState *cs) bound =3D -(ctx->base.pc_first | TARGET_PAGE_MASK) / 4; ctx->base.max_insns =3D MIN(ctx->base.max_insns, bound); =20 - ctx->ntempr =3D 0; ctx->ntempl =3D 0; - memset(ctx->tempr, 0, sizeof(ctx->tempr)); memset(ctx->templ, 0, sizeof(ctx->templ)); } =20 @@ -4140,7 +4130,7 @@ static void hppa_tr_translate_insn(DisasContextBase *= dcbase, CPUState *cs) This will be overwritten by a branch. */ if (ctx->iaoq_b =3D=3D -1) { ctx->iaoq_n =3D -1; - ctx->iaoq_n_var =3D get_temp(ctx); + ctx->iaoq_n_var =3D tcg_temp_new(); tcg_gen_addi_reg(ctx->iaoq_n_var, cpu_iaoq_b, 4); } else { ctx->iaoq_n =3D ctx->iaoq_b + 4; @@ -4161,13 +4151,9 @@ static void hppa_tr_translate_insn(DisasContextBase = *dcbase, CPUState *cs) } =20 /* Forget any temporaries allocated. */ - for (i =3D 0, n =3D ctx->ntempr; i < n; ++i) { - ctx->tempr[i] =3D NULL; - } for (i =3D 0, n =3D ctx->ntempl; i < n; ++i) { ctx->templ[i] =3D NULL; } - ctx->ntempr =3D 0; ctx->ntempl =3D 0; =20 /* Advance the insn queue. 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id w17-20020a63f511000000b005b61a024ec7sm2176380pgh.74.2023.10.18.14.51.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Oct 2023 14:51:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1697665899; x=1698270699; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=3tf30naxwG8ULfBR8Z80R+ehNXjBaz2adScdYG1B0wU=; b=NCSlLadgE/GDmykhjXg+w4Y37UXtENolz0RqrRYfRDENiraCzJVMlXRXkpvRWQ/0Xt 60LuXd03KPrCyBT7UEy0rPft5YcjVFEbiytVD0tiCP+7eNStLnZMyDl6QP5gurhALeZV CAihLL4LLTuhee+uhq41iqBrS5x9JWg6r8ffYxM6IWyTfVk3YNPfsOflyPAlrA27I37c sPMwZKnc9kjkvrWZ3mRIXGZS3dcNRAWJQnCibrhtwAZ46YzgMVjHoKfWzNiNWPg3/esB UQhEEOWJvNcVAOyv8e+XkVhUt7ffjZSD53ubG94wSdI8kTbCt9T3Ou/SD3oLW4Q9ZyJQ Lzmg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697665899; x=1698270699; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=3tf30naxwG8ULfBR8Z80R+ehNXjBaz2adScdYG1B0wU=; b=xTmeXCJOjqNtU/9gBe0osm3aamzRBPcHO+7RSTU/WjJqloRmnplOqKdneicRfLJX2J DFoSm6IcuIAp08WAnCPOKJsV8FiGblmXFlnaIr5bqPDvQmtJWa0xolT4uKhUiH3qvKkH v3IlRUSqwYy4LoZHg8rQTMfCXMmgLRFJplizBJxx7vlIyU3qoJ7DrL5uG+BS97nS/ab0 izRLJaOyUDoCwxofuAwhB8n4W22jKOHPAMvuKwBqpnPApZqB+I0/lxrD4yN2/l+ovrF3 tSvBds2Iz5+DcAjwv3O2M/mXTGg11qwK+Qv4vnqtUEbYAQvRgS+NzLNYY1KKsk4NZjhv 0yog== X-Gm-Message-State: AOJu0YzQr7Lau8b7XJjFFu/XqL7dbKQCImcEi1QHvsD0LNThQTdEBWo/ bE3IcmCb2BQUnlHdapbh9bt1+zV6b8ZcW1vtb6k= X-Google-Smtp-Source: AGHT+IGYJGDuOrbfnUrWbhpI0nFKFd/mvXgWybVVtdRXT3C+j1M7eM+EwGnUnYrGBiY9sqC/mQWPag== X-Received: by 2002:a05:6a00:b53:b0:6b5:ec98:4289 with SMTP id p19-20020a056a000b5300b006b5ec984289mr357415pfo.14.1697665899423; Wed, 18 Oct 2023 14:51:39 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH 03/61] target/hppa: Remove get_temp_tl Date: Wed, 18 Oct 2023 14:50:37 -0700 Message-Id: <20231018215135.1561375-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231018215135.1561375-1-richard.henderson@linaro.org> References: <20231018215135.1561375-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::429; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697666004389100001 Content-Type: text/plain; charset="utf-8" Replace with tcg_temp_new_tl without recording into ctx. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/hppa/translate.c | 28 +++------------------------- 1 file changed, 3 insertions(+), 25 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 3065fbf625..5302381a56 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -254,9 +254,6 @@ typedef struct DisasContext { target_ureg iaoq_n; TCGv_reg iaoq_n_var; =20 - int ntempl; - TCGv_tl templ[4]; - DisasCond null_cond; TCGLabel *null_lab; =20 @@ -491,15 +488,6 @@ static void cond_free(DisasCond *cond) } } =20 -#ifndef CONFIG_USER_ONLY -static TCGv_tl get_temp_tl(DisasContext *ctx) -{ - unsigned i =3D ctx->ntempl++; - g_assert(i < ARRAY_SIZE(ctx->templ)); - return ctx->templ[i] =3D tcg_temp_new_tl(); -} -#endif - static TCGv_reg load_const(DisasContext *ctx, target_sreg v) { TCGv_reg t =3D tcg_temp_new(); @@ -1374,7 +1362,7 @@ static TCGv_i64 space_select(DisasContext *ctx, int s= p, TCGv_reg base) if (sp < 0) { sp =3D ~sp; } - spc =3D get_temp_tl(ctx); + spc =3D tcg_temp_new_tl(); load_spr(ctx, spc, sp); return spc; } @@ -1384,7 +1372,7 @@ static TCGv_i64 space_select(DisasContext *ctx, int s= p, TCGv_reg base) =20 ptr =3D tcg_temp_new_ptr(); tmp =3D tcg_temp_new(); - spc =3D get_temp_tl(ctx); + spc =3D tcg_temp_new_tl(); =20 tcg_gen_shri_reg(tmp, base, TARGET_REGISTER_BITS - 5); tcg_gen_andi_reg(tmp, tmp, 030); @@ -1420,7 +1408,7 @@ static void form_gva(DisasContext *ctx, TCGv_tl *pgva= , TCGv_reg *pofs, #ifdef CONFIG_USER_ONLY *pgva =3D (modify <=3D 0 ? ofs : base); #else - TCGv_tl addr =3D get_temp_tl(ctx); + TCGv_tl addr =3D tcg_temp_new_tl(); tcg_gen_extu_reg_tl(addr, modify <=3D 0 ? ofs : base); if (ctx->tb_flags & PSW_W) { tcg_gen_andi_tl(addr, addr, 0x3fffffffffffffffull); @@ -4080,9 +4068,6 @@ static void hppa_tr_init_disas_context(DisasContextBa= se *dcbase, CPUState *cs) /* Bound the number of instructions by those left on the page. */ bound =3D -(ctx->base.pc_first | TARGET_PAGE_MASK) / 4; ctx->base.max_insns =3D MIN(ctx->base.max_insns, bound); - - ctx->ntempl =3D 0; - memset(ctx->templ, 0, sizeof(ctx->templ)); } =20 static void hppa_tr_tb_start(DisasContextBase *dcbase, CPUState *cs) @@ -4111,7 +4096,6 @@ static void hppa_tr_translate_insn(DisasContextBase *= dcbase, CPUState *cs) DisasContext *ctx =3D container_of(dcbase, DisasContext, base); CPUHPPAState *env =3D cpu_env(cs); DisasJumpType ret; - int i, n; =20 /* Execute one insn. */ #ifdef CONFIG_USER_ONLY @@ -4150,12 +4134,6 @@ static void hppa_tr_translate_insn(DisasContextBase = *dcbase, CPUState *cs) } } =20 - /* Forget any temporaries allocated. */ - for (i =3D 0, n =3D ctx->ntempl; i < n; ++i) { - ctx->templ[i] =3D NULL; - } - ctx->ntempl =3D 0; - /* Advance the insn queue. Note that this check also detects a priority change within the instruction queue. */ if (ret =3D=3D DISAS_NEXT && ctx->iaoq_b !=3D ctx->iaoq_f + 4) { --=20 2.34.1 From nobody Wed Nov 27 18:51:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1697666332; cv=none; d=zohomail.com; s=zohoarc; b=k47wJqiUrULy4iijVl8fpQm0IumLJ8wB5yvwlC3+4NvREwprdgG9EdZDx3q1Ka7urFlS4Opd4OMEFF1mjA04BDgSUUrvE+xtEFJ925gaCZYkqQoP3tS3RxOgnMQlrYvb/EjnIerRaFoxCv0BNw4XpN2iQ/LUGZidafE5QUFg0zE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1697666332; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=mNZMizemvrujc4XnqyNiXy5WpOSPf3XvMMBFfWR0das=; b=i74aXHkkWq6hjaLb1wBxHaz3GDZQB0CVmd0cgw7aCCHlwDU2CK6ke4OKlYiEZZeJ7MCPtMhXzSFXDdcJ8OMwL1D9tBI71uJqiiSlurr5a6xaw0hHGSS3nI1Uso0dBxLfUxWq8zVuyQ9JVuiKVDrU3O6tY9Hft44EBZ62/taM7Ws= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1697666332237754.6647254870998; Wed, 18 Oct 2023 14:58:52 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qtESh-0001mt-Bb; Wed, 18 Oct 2023 17:52:19 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qtES7-0000jI-Rj for qemu-devel@nongnu.org; Wed, 18 Oct 2023 17:51:44 -0400 Received: from mail-pf1-x433.google.com ([2607:f8b0:4864:20::433]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qtES5-0004N9-Pz for qemu-devel@nongnu.org; Wed, 18 Oct 2023 17:51:43 -0400 Received: by mail-pf1-x433.google.com with SMTP id d2e1a72fcca58-6b20577ef7bso4648803b3a.3 for ; Wed, 18 Oct 2023 14:51:41 -0700 (PDT) Received: from stoup.. ([71.212.149.95]) by smtp.gmail.com with ESMTPSA id w17-20020a63f511000000b005b61a024ec7sm2176380pgh.74.2023.10.18.14.51.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Oct 2023 14:51:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1697665900; x=1698270700; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=mNZMizemvrujc4XnqyNiXy5WpOSPf3XvMMBFfWR0das=; b=ayD/AAtZT34aCcjfvcAfIBSySIo5sKo7Ud8EWRzKvQUDmEspuENEqvZkMuykwdzsIk LRshcKvTqUAi0bd6jdINf9o8lgA4HBUqxxjB4v382KpO4SNhfaD8hxD4AkFB/EQe534H SdmRkraKkvPrCHAzP1Z0Ah5flfv/Nf9GwG+5sgcOIbzxOK8dPT4eOvSsOTQU9W/rLD42 dSf43fO6P/cyHyM8sXgwT++mJGii5blzrap5Gqgk/2ke/HMGy9cm4IGTHEVMKneuIKSH j6FfOjvkgbtxopoEkoROZiG5Bb/aQp926mjiLEMJIVunEXGeic/lH7QDil9PUFTgwKjn YlqA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697665900; x=1698270700; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=mNZMizemvrujc4XnqyNiXy5WpOSPf3XvMMBFfWR0das=; b=kclm7fy9gPV4PHLc+1nhVEL2DAKtGSg1sJByEpI/JHvQppEIJje2XSPRgJazdu259c t/BP6dQ3paJp65QAIAZ+bp5wc+9ZZLHp/emyegfPlVjvol7JZ9At0Bmu5tqfMfRoyRpJ jbEA9ic4OJEORR9KfKXYQdD031OTzRfIlAzrSAR9F7uCb5mSEs73LBQdKH0Nh9RyGb94 qCBFJAGgspYmF6TpRTaB/T5p2sUfiL2DWbgum3N8//KruHPb7+zENOO7+x2W69m7Vqz2 4OrcLjz+KyWIycEaaUGSYvYPOi/M2eJV8vwC0PAIYGZaV3wBXReDCn092aTz56nEaPRo KbxA== X-Gm-Message-State: AOJu0YyI4s70w1xHu0AbwgOehq6XUV0PfPeAELyrFLOhF3DFkJnadEYz iDavSww90F33/r8lVNeItc6WZFZcLko4OqBLlkY= X-Google-Smtp-Source: AGHT+IHahDbi6lQUK9pwmuToqzheubshgSDWDjq+UHLUFqHkr9+JhiWiZ1TWJnu94iCg8WKiMuCgVA== X-Received: by 2002:a62:5e05:0:b0:690:2e46:aca3 with SMTP id s5-20020a625e05000000b006902e46aca3mr327818pfb.25.1697665900218; Wed, 18 Oct 2023 14:51:40 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH 04/61] target/hppa: Remove load_const Date: Wed, 18 Oct 2023 14:50:38 -0700 Message-Id: <20231018215135.1561375-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231018215135.1561375-1-richard.henderson@linaro.org> References: <20231018215135.1561375-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::433; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697666333976100013 Content-Type: text/plain; charset="utf-8" Replace with tcg_constant_reg. Signed-off-by: Richard Henderson --- target/hppa/translate.c | 21 +++++++-------------- 1 file changed, 7 insertions(+), 14 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 5302381a56..21f97f63a9 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -488,13 +488,6 @@ static void cond_free(DisasCond *cond) } } =20 -static TCGv_reg load_const(DisasContext *ctx, target_sreg v) -{ - TCGv_reg t =3D tcg_temp_new(); - tcg_gen_movi_reg(t, v); - return t; -} - static TCGv_reg load_gpr(DisasContext *ctx, unsigned reg) { if (reg =3D=3D 0) { @@ -1164,7 +1157,7 @@ static bool do_add_imm(DisasContext *ctx, arg_rri_cf = *a, if (a->cf) { nullify_over(ctx); } - tcg_im =3D load_const(ctx, a->i); + tcg_im =3D tcg_constant_reg(a->i); tcg_r2 =3D load_gpr(ctx, a->r); do_add(ctx, a->t, tcg_im, tcg_r2, 0, 0, is_tsv, is_tc, 0, a->cf); return nullify_end(ctx); @@ -1253,7 +1246,7 @@ static bool do_sub_imm(DisasContext *ctx, arg_rri_cf = *a, bool is_tsv) if (a->cf) { nullify_over(ctx); } - tcg_im =3D load_const(ctx, a->i); + tcg_im =3D tcg_constant_reg(a->i); tcg_r2 =3D load_gpr(ctx, a->r); do_sub(ctx, a->t, tcg_im, tcg_r2, is_tsv, 0, 0, a->cf); return nullify_end(ctx); @@ -2808,7 +2801,7 @@ static bool trans_cmpiclr(DisasContext *ctx, arg_rri_= cf *a) nullify_over(ctx); } =20 - tcg_im =3D load_const(ctx, a->i); + tcg_im =3D tcg_constant_reg(a->i); tcg_r2 =3D load_gpr(ctx, a->r); do_cmpclr(ctx, a->t, tcg_im, tcg_r2, a->cf); =20 @@ -2994,7 +2987,7 @@ static bool trans_cmpb(DisasContext *ctx, arg_cmpb *a) static bool trans_cmpbi(DisasContext *ctx, arg_cmpbi *a) { nullify_over(ctx); - return do_cmpb(ctx, a->r, load_const(ctx, a->i), a->c, a->f, a->n, a->= disp); + return do_cmpb(ctx, a->r, tcg_constant_reg(a->i), a->c, a->f, a->n, a-= >disp); } =20 static bool do_addb(DisasContext *ctx, unsigned r, TCGv_reg in1, @@ -3033,7 +3026,7 @@ static bool trans_addb(DisasContext *ctx, arg_addb *a) static bool trans_addbi(DisasContext *ctx, arg_addbi *a) { nullify_over(ctx); - return do_addb(ctx, a->r, load_const(ctx, a->i), a->c, a->f, a->n, a->= disp); + return do_addb(ctx, a->r, tcg_constant_reg(a->i), a->c, a->f, a->n, a-= >disp); } =20 static bool trans_bb_sar(DisasContext *ctx, arg_bb_sar *a) @@ -3345,7 +3338,7 @@ static bool trans_depwi_sar(DisasContext *ctx, arg_de= pwi_sar *a) if (a->c) { nullify_over(ctx); } - return do_depw_sar(ctx, a->t, a->c, a->nz, a->clen, load_const(ctx, a-= >i)); + return do_depw_sar(ctx, a->t, a->c, a->nz, a->clen, tcg_constant_reg(a= ->i)); } =20 static bool trans_be(DisasContext *ctx, arg_be *a) @@ -3852,7 +3845,7 @@ static bool trans_ftest(DisasContext *ctx, arg_ftest = *a) return true; } if (inv) { - TCGv_reg c =3D load_const(ctx, mask); + TCGv_reg c =3D tcg_constant_reg(mask); tcg_gen_or_reg(t, t, c); ctx->null_cond =3D cond_make(TCG_COND_EQ, t, c); } else { --=20 2.34.1 From nobody Wed Nov 27 18:51:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id w17-20020a63f511000000b005b61a024ec7sm2176380pgh.74.2023.10.18.14.51.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Oct 2023 14:51:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1697665901; x=1698270701; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=F2CpBYHyN5WTjKAnF9eC52gwF9DPW7ui+s7AIy3W9Zs=; b=RNmoujDR7osnJn1omZfO8X0Q7DGMPFoqSHlR2bK2frPk6sH6n2EqzrCWqIq2wB9Y/K qtAaVdOrvNGrlYSOkMBOuceq1dxxYHTRMtyghyNr9V66mvSzZ2t4ZjDF7iiTuerONVfQ 7esRH05DC633ED6cL7M5mExAXrD/DdE1aw3zFwifhNEcPGEgAF9VPi2ucaRGCw10cQZT cL4FW8DaK+d+Xs87pLZQtIwtMZ2R/JCpSM+IPKATKG9aKEfVdaj3Lmu63iL7qn6E5akK C7kF876BZHyr0ZFjjQAIQL2J4EHxnQhDhukg/2pByX2Kb7GwDZ2nnafg4TEs/5K/T8QO RNLw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697665901; x=1698270701; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=F2CpBYHyN5WTjKAnF9eC52gwF9DPW7ui+s7AIy3W9Zs=; b=sogBXfbnoUGzMZstvxSEDiE5Cksc0DQfeuv3f+gXZxwY5fxFENeGKKg1qcvBPMVJat YT2N26lVa2W276T/yUR/wb0ThtOlR6rPrUfgBs6j1BxZV2kfnJSfBAV3F4MTgty/OvCC Wi05tyAXrptnuARUrjw1vyaS8MLsDmaVQFwbtaqQyl+fN6O9uiUFvlIVCI5PhjMGS+6E pGACR620FMN7Gibboyu6NSwgJapLLrxYpfhRwXFt9Qk1i6Fis3I8SXM5O894rX1mavEf 0iFBkDF7U6VQAA1QNIQh6ef6U00DvS+5C/hvdnSUH8uFOajSa132rGQEgzf/LEDtiad4 kJdA== X-Gm-Message-State: AOJu0Yw/7sltaX4nJv/2oFnvDob2xYhaG1c5u2J5BEI9OJh0GhjOc7id HzcuGTA/Aq0hUnBXyr0RJHMenMKDb8CFgzos/KE= X-Google-Smtp-Source: AGHT+IHYFQ+6BrYWrI3/d4T/bgwej28fvh99wIpAL3PIafA+FgvG5KVD3n+TYMjXik8PeWRPpDNq4Q== X-Received: by 2002:a05:6a00:1788:b0:690:38b6:b2db with SMTP id s8-20020a056a00178800b0069038b6b2dbmr452679pfg.6.1697665901043; Wed, 18 Oct 2023 14:51:41 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH 05/61] target/hppa: Fix hppa64 case in machine.c Date: Wed, 18 Oct 2023 14:50:39 -0700 Message-Id: <20231018215135.1561375-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231018215135.1561375-1-richard.henderson@linaro.org> References: <20231018215135.1561375-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42b; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697666038465100001 Content-Type: text/plain; charset="utf-8" Typo of VMSTATE_UINTTR_V and VMSTATE_UINTTR_ARRAY_V macros. Signed-off-by: Richard Henderson --- target/hppa/machine.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/hppa/machine.c b/target/hppa/machine.c index 905991d7f9..0c0bba68c0 100644 --- a/target/hppa/machine.c +++ b/target/hppa/machine.c @@ -24,9 +24,9 @@ #if TARGET_REGISTER_BITS =3D=3D 64 #define qemu_put_betr qemu_put_be64 #define qemu_get_betr qemu_get_be64 -#define VMSTATE_UINTTL_V(_f, _s, _v) \ +#define VMSTATE_UINTTR_V(_f, _s, _v) \ VMSTATE_UINT64_V(_f, _s, _v) -#define VMSTATE_UINTTL_ARRAY_V(_f, _s, _n, _v) \ +#define VMSTATE_UINTTR_ARRAY_V(_f, _s, _n, _v) \ VMSTATE_UINT64_ARRAY_V(_f, _s, _n, _v) #else #define qemu_put_betr qemu_put_be32 --=20 2.34.1 From nobody Wed Nov 27 18:51:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1697665975; cv=none; d=zohomail.com; s=zohoarc; b=ioTS4VoW96fz9t3t7xz+Xh8abQVyeRrpXc/G0uffMp171wiy9OF7p6lAIdhv1gtxVwbqlfFzmheCTWoG2kWjaD1z7PwbwixrLjuBpJOZFEysRVsdbTtHcUxntV1ITB4H+IQGROcMqmk8p6uj/0GrrDkBGBWkz989TejcxHuLvcw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1697665975; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=OQDrnustD9JMJVkf0X+C7sW4Z0qLBIQjQQllFpFrUUM=; b=hog3FheRpaxvl65iZKarKOsBOc8W9y8Jv8YF3reV5FNCsUedEHpvPALZdRhDbRV09tm8K9B/bVZKbgZEI9xFi15fhMhe/s7sV178pRqEyULNnln4k3P1V6/mqX8CAZbgv5lEGHAyxQZ+XFustSaZyL1lvNcm0E1iWh8Ln/6bw9Y= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 16976659756182.552835240319382; Wed, 18 Oct 2023 14:52:55 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qtESC-00014D-O2; Wed, 18 Oct 2023 17:51:48 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qtESA-0000rs-Cn for qemu-devel@nongnu.org; Wed, 18 Oct 2023 17:51:46 -0400 Received: from mail-oo1-xc2d.google.com ([2607:f8b0:4864:20::c2d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qtES7-0004Na-3i for qemu-devel@nongnu.org; Wed, 18 Oct 2023 17:51:44 -0400 Received: by mail-oo1-xc2d.google.com with SMTP id 006d021491bc7-581fb6f53fcso553858eaf.2 for ; Wed, 18 Oct 2023 14:51:42 -0700 (PDT) Received: from stoup.. ([71.212.149.95]) by smtp.gmail.com with ESMTPSA id w17-20020a63f511000000b005b61a024ec7sm2176380pgh.74.2023.10.18.14.51.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Oct 2023 14:51:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1697665902; x=1698270702; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=OQDrnustD9JMJVkf0X+C7sW4Z0qLBIQjQQllFpFrUUM=; b=YlCB5rbXHhXRgm0HIo1I/HY/j7JB7PrfPynCaGRzvlAv3tDWMnc9M6t74qxN3J4iq6 mlZnSH2Bf3Npv6BYltE/BsVZUmaIEnTpfUHbvGtBHKPbx+OiNff7nd4/aa+cU+Nt7/y3 OG7cPqlYBkRt6NOXFvdpyxeyGEdaIbbYZkL15EuL+MjZnOR3mZfA7J4eokf9y7IhskoP GydHyNmT5N24LkklYWv0VDwe3ivHWvHEv+6cerP9x+JJxqeWSu713Ys70FZuIrM874Et TLRYy/RvEM1Oa4Pm74HXrYxN0lufuxE5IRFAeteTDsxCRFpJvy5XV7fbVXefm60dm2Ia icBA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697665902; x=1698270702; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=OQDrnustD9JMJVkf0X+C7sW4Z0qLBIQjQQllFpFrUUM=; b=tHKU6y6zFBQOD3amX88s/QJJSax+sGH4H5RBzaX1EefsnUy2ha1bg4sQKlh/wcp5C1 i2C/uuV39veR7/ofIMKast7+gYWe6Dg7Lz7sEfbPRxtDd+nIxG2yNh+YangFIDMu1gAp NuORGzCD76HoBTsrNFCXu4Pa9VjAyjojHBLQaRqrlwglr5tP5sA3yppARBnbYZvk4rZu NUGNqc42iRBD2TOn1BN72fY51d+D5LO7p87IHlZQ+4ZESUnIgufzWz+uZD93nK7iompE jI/ugIGVfO03K4kJ7E9++xvD7qUMHEyi0/eW+G2cJojmJ7huO0MS8p46kmkhxq+r7Dfp FxNQ== X-Gm-Message-State: AOJu0YwILU3IrHlyA0wK5wcV+Y/hlPlLG7ZkyZ5kh2OZa0iO/7NYvDyx zp50RomWY7TwUkUWJBykqbSetJkOnyxU8CUTv+c= X-Google-Smtp-Source: AGHT+IGxT+uRZlfwIJxR1kAUAj6L47EAJEQTmD7UTKU5IGxqxg4WK0uCrX68YU/xfmi+CPYaTGYSZQ== X-Received: by 2002:a05:6358:c62a:b0:134:f326:e819 with SMTP id fd42-20020a056358c62a00b00134f326e819mr261045rwb.29.1697665901989; Wed, 18 Oct 2023 14:51:41 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH 06/61] target/hppa: Fix load in do_load_32 Date: Wed, 18 Oct 2023 14:50:40 -0700 Message-Id: <20231018215135.1561375-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231018215135.1561375-1-richard.henderson@linaro.org> References: <20231018215135.1561375-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::c2d; envelope-from=richard.henderson@linaro.org; helo=mail-oo1-xc2d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697665976301100001 Content-Type: text/plain; charset="utf-8" The destination is TCGv_i32, so use tcg_gen_qemu_ld_i32 not tcg_gen_qemu_ld_reg. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/hppa/translate.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 21f97f63a9..ff559ed21d 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -1430,7 +1430,7 @@ static void do_load_32(DisasContext *ctx, TCGv_i32 de= st, unsigned rb, =20 form_gva(ctx, &addr, &ofs, rb, rx, scale, disp, sp, modify, ctx->mmu_idx =3D=3D MMU_PHYS_IDX); - tcg_gen_qemu_ld_reg(dest, addr, ctx->mmu_idx, mop | UNALIGN(ctx)); + tcg_gen_qemu_ld_i32(dest, addr, ctx->mmu_idx, mop | UNALIGN(ctx)); if (modify) { save_gpr(ctx, rb, ofs); } --=20 2.34.1 From nobody Wed Nov 27 18:51:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1697666028; cv=none; d=zohomail.com; s=zohoarc; b=FHEx+HPdDPt2Fun+KI/MWNVOvpq9G6/1Odin4gcRU12jsuFPP16ZVai/u++fCb3AY7d5u64A6ZYImHgfQp1CkwQg8kMv1g3xiF78FUZir+1F/WULdCFvxBzvKZ/fGzC/o1mppEQ+Rq+mDGgMwcC+94DU6KB47LORrL0+pU7FQIA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1697666028; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=HcidF9Jk1N+Ej8dbQUUvFmfE2V7LiGtPgLbzAI4Qab4=; b=CErfT9tORkdfV+us1fsweLPDCbbSVSmrrYAXJ9sk9NFQ5ikZAf2gN9JthaboYnruVZqNruSYjZwi6ObeXnJ8GSnInWtE0DbagL2Tlw2cpJXR0UgF97v4S29QTgWtDCx3hWFtaazDNstCBpNr1MTS3XzklnMv4BwgqaQ+5deNUjo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 169766602895087.95480826135474; Wed, 18 Oct 2023 14:53:48 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qtESB-0000sv-3f; Wed, 18 Oct 2023 17:51:47 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qtESA-0000rt-Cu for qemu-devel@nongnu.org; Wed, 18 Oct 2023 17:51:46 -0400 Received: from mail-ot1-x32a.google.com ([2607:f8b0:4864:20::32a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qtES7-0004Nm-Sq for qemu-devel@nongnu.org; Wed, 18 Oct 2023 17:51:44 -0400 Received: by mail-ot1-x32a.google.com with SMTP id 46e09a7af769-6c4e30a3604so4809466a34.2 for ; Wed, 18 Oct 2023 14:51:43 -0700 (PDT) Received: from stoup.. ([71.212.149.95]) by smtp.gmail.com with ESMTPSA id w17-20020a63f511000000b005b61a024ec7sm2176380pgh.74.2023.10.18.14.51.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Oct 2023 14:51:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1697665903; x=1698270703; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=HcidF9Jk1N+Ej8dbQUUvFmfE2V7LiGtPgLbzAI4Qab4=; b=JTOUyhC/XUy7Gr2RsMUbu28dzfSfUr+dCgUrTh8sJyk76u5B48M0m8Z6xelUUjLrC+ DC6bCjJlw1gIR+K3FS4lLWhPrmFsBfw+TTz102t83RFIVpm0/3ki5c4wcly9gsEdo9eY SqPY8t+LIzPX2Ag2v4X1blivRdZ52oKoDmRDA4AWVSbO3P8ulKk6DdyE8xXBAcd4iKUs yzyiRtYcja7UsiJwns1UNA2tnxZ4rfAxNQ120iwqG5sqLyTfmNz8YRsI8UeX+D2DOmj5 nt70QsyGq8hlE1DkKVpDVfyb+C1N+paqMrblYD9+9kGO2xd616EIOV+HRBgXyEKmRsjN ElqQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697665903; x=1698270703; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=HcidF9Jk1N+Ej8dbQUUvFmfE2V7LiGtPgLbzAI4Qab4=; b=fWPCZ0giKHrpqMuQqVrUoAUL9Sl16nkOM4JF6/eZLP3dqBbPtlzx8mAC57FFwPRvm8 nq4Dz8wRBghq0B/KP3RX18S5Gout1ebOeWelZLfBH8UUZzCqzXqyPsk0oFm/ShltKNBs RzbPxpAq8lGGr5fejSUjNXlPm0lb+ghSDwIWgpakk6PBOxOonJX9ZdISAOcbP15jaRuT SLvTIXQSyP4zU9izMD/FHSFnBJ2vkbqwv0AYW5rRJrErUWE4C2phZxbxslmSIAa3rGCB j22IvZuervzdxOhIouU+cgzWsjnxydeDlrdbB2NO5al+Gz09BCH7QJWmca/Hqq08US0R 6LkA== X-Gm-Message-State: AOJu0Yz6yciU/CF/ZJk0nCKuduehhI0S7TdK2vp7es3f6qzDmsmM0oDk fzyXdiapmumiP+ZkF+5lr1BipoZeeAHosRivPLc= X-Google-Smtp-Source: AGHT+IHq8gq5WNv79G0npEBQO80O/8sCgsrm6J8tqgfPizeAssLpEMOdCtvHI3xxuhvwqOFlHLNBCw== X-Received: by 2002:a05:6830:2641:b0:6c4:aa6a:c4e7 with SMTP id f1-20020a056830264100b006c4aa6ac4e7mr513901otu.10.1697665902723; Wed, 18 Oct 2023 14:51:42 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH 07/61] target/hppa: Truncate rotate count in trans_shrpw_sar Date: Wed, 18 Oct 2023 14:50:41 -0700 Message-Id: <20231018215135.1561375-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231018215135.1561375-1-richard.henderson@linaro.org> References: <20231018215135.1561375-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::32a; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697666030438100001 Content-Type: text/plain; charset="utf-8" When forcing rotate by i32, the shift count must be as well. Signed-off-by: Richard Henderson --- target/hppa/translate.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index ff559ed21d..e6ab113a1c 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -3105,8 +3105,11 @@ static bool trans_shrpw_sar(DisasContext *ctx, arg_s= hrpw_sar *a) tcg_gen_shr_reg(dest, dest, cpu_sar); } else if (a->r1 =3D=3D a->r2) { TCGv_i32 t32 =3D tcg_temp_new_i32(); + TCGv_i32 s32 =3D tcg_temp_new_i32(); + tcg_gen_trunc_reg_i32(t32, load_gpr(ctx, a->r2)); - tcg_gen_rotr_i32(t32, t32, cpu_sar); + tcg_gen_trunc_reg_i32(s32, cpu_sar); + tcg_gen_rotr_i32(t32, t32, s32); tcg_gen_extu_i32_reg(dest, t32); } else { TCGv_i64 t =3D tcg_temp_new_i64(); --=20 2.34.1 From nobody Wed Nov 27 18:51:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1697665977; cv=none; d=zohomail.com; s=zohoarc; b=KsIqjpx3Hd6Uvn1gSEDN/Z3bqx8aMU56BbcSb7GFN3jGYWuI+QluhZ33EquxDLKOWLr1vVEtRZxBD2gSDhk2sw8M0YNau2C2MDkZ1qNZyIjn2LV5iqGJ618t2u+GMeg4T2BVBfU7brfvBErw09ZWLRCGu7Nc/Z1puB1Cvd2tx4w= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1697665977; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=jy+spAs5u7WgOQZspkjRSxDs5g0jtQCLczTslsy9ExE=; b=jvprdaWcrkcUDvNBOhD1eSZQRKzGddRsMFjclejtdbcIYsK3iuK4dmHd9YPT5YbtAyGS5YTI3s48yuXq94ijqh1lvLko6y3eh3XRY3Y4w6dTemSldMn3xFHj5IaMcH7m/bk3rtvTCgbjQRNpler4CD1IuI4s2WGBNL1jsFLTCJA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1697665977786456.5747106467636; Wed, 18 Oct 2023 14:52:57 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qtEST-0001BB-UW; Wed, 18 Oct 2023 17:52:07 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qtESB-0000y8-RO for qemu-devel@nongnu.org; Wed, 18 Oct 2023 17:51:47 -0400 Received: from mail-oo1-xc29.google.com ([2607:f8b0:4864:20::c29]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qtESA-0004O2-5S for qemu-devel@nongnu.org; Wed, 18 Oct 2023 17:51:47 -0400 Received: by mail-oo1-xc29.google.com with SMTP id 006d021491bc7-581d4f9a2c5so1258453eaf.0 for ; Wed, 18 Oct 2023 14:51:44 -0700 (PDT) Received: from stoup.. ([71.212.149.95]) by smtp.gmail.com with ESMTPSA id w17-20020a63f511000000b005b61a024ec7sm2176380pgh.74.2023.10.18.14.51.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Oct 2023 14:51:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1697665903; x=1698270703; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=jy+spAs5u7WgOQZspkjRSxDs5g0jtQCLczTslsy9ExE=; b=M+KngcJOuAS+GoE9u33VRTnk17iY9Z7CVFcqSxPRbzaRwv/5ebdysrBxgEDtlcg+C4 d090iouG/p5T8rq7d7JZA8JG5x1/tRDQRLPQbwLlQGFnqnD92LM+tVymwxSxXG3LUziT 76ZEUIozHCpP+OADMEWisUPBdzJhELQKOw/0HXD1mnDrKEsFI01ZISnaGRHP0o6WrUIk JNFKCcKo/Ne2w7ku09FbOBpz0n94Rk9sGsKy8amD+1Bt1ZqCX0Qhv5XgLFnBSOY5xjE/ j3ptcvvjxMTt2EqP6/vLoOrnzvjIlbi52zkW6V2T5hy0Jf/UNNK+MbR9kza8v4CcEWO2 B97g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697665903; x=1698270703; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=jy+spAs5u7WgOQZspkjRSxDs5g0jtQCLczTslsy9ExE=; b=srDK6sHMuPuLMzFs6SJja3OSEewLboYcHkp/+SHJoazp1qAcnSTmrdULGi/6BWDdad zo1R6L+Ndg19luJ+ub/2+8CxZ7jr50Iqqex818GAj9xgHWfz+87acrsbGqMjF+Kk4Ksp MdHvdBhxleZ9hJgZ8tECgsQwZTosjCP1fS+u1/akrA6e7EpxKuR+PB4VKDKW6LJZSnAa rlvWkB9YcFQnHE+DVlbvtssGgsC98VO8dD2l3UTQCIIaKoGYGMoVZQoHuVzNqYmx5/UP HTw+8JgcKPha8oYoYV6YwldIRt2Wn73C4sWEUytsq9jfo2h5lwYBS0e4tPEgPuVOx9Lf ++LA== X-Gm-Message-State: AOJu0YzPvP28EvL4pVGmvWBVRiylrhjFmg9nv+HyNGAymri+zB+H1EGJ p0Wz/BtfGXKc0ssxfcGQVs2jD2DODzPk/rQWoZA= X-Google-Smtp-Source: AGHT+IGzECKSV1Vbvuhc0R1GMyx171rvkk3NZ0iRgwxlQN10yIQ6/stbU6IyL8T8Jw9Gvz77SKs7+g== X-Received: by 2002:a05:6359:5d27:b0:139:c75f:63eb with SMTP id ps39-20020a0563595d2700b00139c75f63ebmr219978rwb.21.1697665903522; Wed, 18 Oct 2023 14:51:43 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH 08/61] target/hppa: Fix trans_ds for hppa64 Date: Wed, 18 Oct 2023 14:50:42 -0700 Message-Id: <20231018215135.1561375-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231018215135.1561375-1-richard.henderson@linaro.org> References: <20231018215135.1561375-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::c29; envelope-from=richard.henderson@linaro.org; helo=mail-oo1-xc29.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697665978336100005 Content-Type: text/plain; charset="utf-8" This instruction always uses the input carry from bit 32, but produces all 16 output carry bits. Signed-off-by: Richard Henderson --- target/hppa/translate.c | 48 +++++++++++++++++++++++++++++++---------- 1 file changed, 37 insertions(+), 11 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index e6ab113a1c..fb7a295367 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -803,6 +803,12 @@ static bool cond_need_cb(int c) return c =3D=3D 4 || c =3D=3D 5; } =20 +/* Need extensions from TCGv_i32 to TCGv_reg. */ +static bool cond_need_ext(DisasContext *ctx, bool d) +{ + return TARGET_REGISTER_BITS =3D=3D 64 && !d; +} + /* * Compute conditional for arithmetic. See Page 5-3, Table 5-1, of * the Parisc 1.1 Architecture Reference Manual for details. @@ -1040,6 +1046,22 @@ static DisasCond do_unit_cond(unsigned cf, TCGv_reg = res, return cond; } =20 +static TCGv_reg get_carry(DisasContext *ctx, bool d, + TCGv_reg cb, TCGv_reg cb_msb) +{ + if (cond_need_ext(ctx, d)) { + TCGv_reg t =3D tcg_temp_new(); + tcg_gen_extract_reg(t, cb, 32, 1); + return t; + } + return cb_msb; +} + +static TCGv_reg get_psw_carry(DisasContext *ctx, bool d) +{ + return get_carry(ctx, d, cpu_psw_cb, cpu_psw_cb_msb); +} + /* Compute signed overflow for addition. */ static TCGv_reg do_add_sv(DisasContext *ctx, TCGv_reg res, TCGv_reg in1, TCGv_reg in2) @@ -2712,6 +2734,7 @@ static bool trans_dcor_i(DisasContext *ctx, arg_rr_cf= *a) static bool trans_ds(DisasContext *ctx, arg_rrr_cf *a) { TCGv_reg dest, add1, add2, addc, zero, in1, in2; + TCGv_reg cout; =20 nullify_over(ctx); =20 @@ -2726,18 +2749,20 @@ static bool trans_ds(DisasContext *ctx, arg_rrr_cf = *a) =20 /* Form R1 << 1 | PSW[CB]{8}. */ tcg_gen_add_reg(add1, in1, in1); - tcg_gen_add_reg(add1, add1, cpu_psw_cb_msb); + tcg_gen_add_reg(add1, add1, get_psw_carry(ctx, false)); =20 - /* Add or subtract R2, depending on PSW[V]. Proper computation of - carry{8} requires that we subtract via + ~R2 + 1, as described in - the manual. By extracting and masking V, we can produce the - proper inputs to the addition without movcond. */ - tcg_gen_sari_reg(addc, cpu_psw_v, TARGET_REGISTER_BITS - 1); + /* + * Add or subtract R2, depending on PSW[V]. Proper computation of + * carry requires that we subtract via + ~R2 + 1, as described in + * the manual. By extracting and masking V, we can produce the + * proper inputs to the addition without movcond. + */ + tcg_gen_sextract_reg(addc, cpu_psw_v, 31, 1); tcg_gen_xor_reg(add2, in2, addc); tcg_gen_andi_reg(addc, addc, 1); - /* ??? This is only correct for 32-bit. */ - tcg_gen_add2_i32(dest, cpu_psw_cb_msb, add1, zero, add2, zero); - tcg_gen_add2_i32(dest, cpu_psw_cb_msb, dest, cpu_psw_cb_msb, addc, zer= o); + + tcg_gen_add2_reg(dest, cpu_psw_cb_msb, add1, zero, add2, zero); + tcg_gen_add2_reg(dest, cpu_psw_cb_msb, dest, cpu_psw_cb_msb, addc, zer= o); =20 /* Write back the result register. */ save_gpr(ctx, a->t, dest); @@ -2747,7 +2772,8 @@ static bool trans_ds(DisasContext *ctx, arg_rrr_cf *a) tcg_gen_xor_reg(cpu_psw_cb, cpu_psw_cb, dest); =20 /* Write back PSW[V] for the division step. */ - tcg_gen_neg_reg(cpu_psw_v, cpu_psw_cb_msb); + cout =3D get_psw_carry(ctx, false); + tcg_gen_neg_reg(cpu_psw_v, cout); tcg_gen_xor_reg(cpu_psw_v, cpu_psw_v, in2); =20 /* Install the new nullification. */ @@ -2757,7 +2783,7 @@ static bool trans_ds(DisasContext *ctx, arg_rrr_cf *a) /* ??? The lshift is supposed to contribute to overflow. */ sv =3D do_add_sv(ctx, dest, add1, add2); } - ctx->null_cond =3D do_cond(a->cf, dest, cpu_psw_cb_msb, sv); + ctx->null_cond =3D do_cond(a->cf, dest, cout, sv); } =20 return nullify_end(ctx); --=20 2.34.1 From nobody Wed Nov 27 18:51:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1697665957; cv=none; d=zohomail.com; s=zohoarc; b=hCB0SAqu/YX5i3rpDYRgWXUb4f+Rkvplu4r6N7EboHiOyQ+RwcS366qxukya0WRuWgv+i9yvX1FsnWttu21W1rhcYM67xjJ9AMyZ7xROR+CW749Dh6TRZ3U1NW3iEVa/R5U5gZt1ljZh7Lmy7iYe0lvkVa4vdWBIRtn7vUdM9sg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1697665957; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=vj5Zj+Bw57JH4E175sUuTw9SkCPkXc9sWUiIDH26gck=; b=nb47RxmvaU2Zp2MBT2PIX5809Ir9XIf1owjJI1uQqRvnk99o0ePpdNzznCB9bQu23SvTyqx4OOLtjSFqFZgECjGkE10CEk8JgiFqNBcXJhGuo/PzUdQ9IG+MUN3xVt0QWrKw1I4LJqhCBnbu/fz1uH4pvboqpubqqOgzrj/Yy2w= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1697665957931610.0662788651797; Wed, 18 Oct 2023 14:52:37 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qtESZ-0001U0-Es; Wed, 18 Oct 2023 17:52:11 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qtESB-0000z2-Uq for qemu-devel@nongnu.org; Wed, 18 Oct 2023 17:51:47 -0400 Received: from mail-oa1-x31.google.com ([2001:4860:4864:20::31]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qtESA-0004OE-5u for qemu-devel@nongnu.org; Wed, 18 Oct 2023 17:51:47 -0400 Received: by mail-oa1-x31.google.com with SMTP id 586e51a60fabf-1dd8304b980so4636093fac.2 for ; Wed, 18 Oct 2023 14:51:45 -0700 (PDT) Received: from stoup.. ([71.212.149.95]) by smtp.gmail.com with ESMTPSA id w17-20020a63f511000000b005b61a024ec7sm2176380pgh.74.2023.10.18.14.51.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Oct 2023 14:51:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1697665904; x=1698270704; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=vj5Zj+Bw57JH4E175sUuTw9SkCPkXc9sWUiIDH26gck=; b=qk2aoN7fFmPgsnPWRZCf58T0Ql4TMOdoXep+3P3YljWwveXOho3TkTiTRulA8guso0 qeNk8JIyckDYB9CTx8oPclLtwPMXguY7a2t+XvuvnZjCfAYFMQ+6ynPkCM+XUL3RnrzZ SgA9R+JmcZEFeZAgzDDbXmG/8oYvkVcR5Agdc+WFjHfgvdF/ilYTPlbYSJaVr9Yj5NU8 aI8TFA/8+zGAD/NH39BBNb9513E8Of+ZE5wkkgeeb6CTPDcsg9vhxGrWTCSVsseGb5Vl Y0ZKQszpC/Q3ctx2LzxcMyyfOndlclqLTqqDNOAhksYgjQPjNd2roUlYYp+/ErfQQikZ QQYw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697665904; x=1698270704; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=vj5Zj+Bw57JH4E175sUuTw9SkCPkXc9sWUiIDH26gck=; b=JpvBnOdrzB8EAt43VuVltItJEmsW/nEKoIkLUBI5by8FMSFM4g7IVl0RNSQOI+ShIS Ir1zRCe7SQcYqw3fe8BhylTViOeGPfucjua3S/v4RjQub4FcBiBD7qTK8JO97/jPwggj o7vSITCxarZr0GWbCZro1Rsad+ao7oNSy0N82GW6aPRe531fVsjeIlRhNs+Xl6rRAQ/A YEjt4DRahbS3c71tvz8KwmEitRY0GxyAxGj3OEBbgUB3bEjZkRQ4nz2r9j09+EZq4ju8 s4QVgrNTEIzJ+gaRTs8zTOPVrcXpYNd0z0oNKEAHFAifvQz4u8ucP6Cy1aF8KF/EtHuH EHKA== X-Gm-Message-State: AOJu0Yz964iWVrd2q/t0DfR4/qaf8TjDVhR6k2Jf4qynkZ3Q8Qk4nYJW bXDCmGMXrliko/i1s/oSGM8Tk6aX5ZliYVPctn4= X-Google-Smtp-Source: AGHT+IFFvHDe5GdkLcSPqu4syER2KKNUrOnM5S5I4vhUvz3MmdTZ/1s1nbt+4mW4ttniQTh+xk1VCA== X-Received: by 2002:a05:6870:8294:b0:1c0:f8a7:ec14 with SMTP id q20-20020a056870829400b001c0f8a7ec14mr635442oae.57.1697665904345; Wed, 18 Oct 2023 14:51:44 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH 09/61] target/hppa: Fix do_add, do_sub for hppa64 Date: Wed, 18 Oct 2023 14:50:43 -0700 Message-Id: <20231018215135.1561375-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231018215135.1561375-1-richard.henderson@linaro.org> References: <20231018215135.1561375-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:4860:4864:20::31; envelope-from=richard.henderson@linaro.org; helo=mail-oa1-x31.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697665958276100002 Content-Type: text/plain; charset="utf-8" Select the proper carry bit for input to the arithmetic and for output for the condition. Signed-off-by: Richard Henderson --- target/hppa/translate.c | 50 ++++++++++++++++++++++++++--------------- 1 file changed, 32 insertions(+), 18 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index fb7a295367..8ebe7523a7 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -1094,13 +1094,15 @@ static void do_add(DisasContext *ctx, unsigned rt, = TCGv_reg in1, TCGv_reg in2, unsigned shift, bool is_l, bool is_tsv, bool is_tc, bool is_c, unsigned cf) { - TCGv_reg dest, cb, cb_msb, sv, tmp; + TCGv_reg dest, cb, cb_msb, cb_cond, sv, tmp; unsigned c =3D cf >> 1; DisasCond cond; + bool d =3D false; =20 dest =3D tcg_temp_new(); cb =3D NULL; cb_msb =3D NULL; + cb_cond =3D NULL; =20 if (shift) { tmp =3D tcg_temp_new(); @@ -1111,19 +1113,22 @@ static void do_add(DisasContext *ctx, unsigned rt, = TCGv_reg in1, if (!is_l || cond_need_cb(c)) { TCGv_reg zero =3D tcg_constant_reg(0); cb_msb =3D tcg_temp_new(); + cb =3D tcg_temp_new(); + tcg_gen_add2_reg(dest, cb_msb, in1, zero, in2, zero); if (is_c) { - tcg_gen_add2_reg(dest, cb_msb, dest, cb_msb, cpu_psw_cb_msb, z= ero); + tcg_gen_add2_reg(dest, cb_msb, dest, cb_msb, + get_psw_carry(ctx, d), zero); } - if (!is_l) { - cb =3D tcg_temp_new(); - tcg_gen_xor_reg(cb, in1, in2); - tcg_gen_xor_reg(cb, cb, dest); + tcg_gen_xor_reg(cb, in1, in2); + tcg_gen_xor_reg(cb, cb, dest); + if (cond_need_cb(c)) { + cb_cond =3D get_carry(ctx, d, cb, cb_msb); } } else { tcg_gen_add_reg(dest, in1, in2); if (is_c) { - tcg_gen_add_reg(dest, dest, cpu_psw_cb_msb); + tcg_gen_add_reg(dest, dest, get_psw_carry(ctx, d)); } } =20 @@ -1138,7 +1143,7 @@ static void do_add(DisasContext *ctx, unsigned rt, TC= Gv_reg in1, } =20 /* Emit any conditional trap before any writeback. */ - cond =3D do_cond(cf, dest, cb_msb, sv); + cond =3D do_cond(cf, dest, cb_cond, sv); if (is_tc) { tmp =3D tcg_temp_new(); tcg_gen_setcond_reg(cond.c, tmp, cond.a0, cond.a1); @@ -1192,6 +1197,7 @@ static void do_sub(DisasContext *ctx, unsigned rt, TC= Gv_reg in1, TCGv_reg dest, sv, cb, cb_msb, zero, tmp; unsigned c =3D cf >> 1; DisasCond cond; + bool d =3D false; =20 dest =3D tcg_temp_new(); cb =3D tcg_temp_new(); @@ -1201,15 +1207,17 @@ static void do_sub(DisasContext *ctx, unsigned rt, = TCGv_reg in1, if (is_b) { /* DEST,C =3D IN1 + ~IN2 + C. */ tcg_gen_not_reg(cb, in2); - tcg_gen_add2_reg(dest, cb_msb, in1, zero, cpu_psw_cb_msb, zero); + tcg_gen_add2_reg(dest, cb_msb, in1, zero, get_psw_carry(ctx, d), z= ero); tcg_gen_add2_reg(dest, cb_msb, dest, cb_msb, cb, zero); tcg_gen_xor_reg(cb, cb, in1); tcg_gen_xor_reg(cb, cb, dest); } else { - /* DEST,C =3D IN1 + ~IN2 + 1. We can produce the same result in f= ewer - operations by seeding the high word with 1 and subtracting. */ - tcg_gen_movi_reg(cb_msb, 1); - tcg_gen_sub2_reg(dest, cb_msb, in1, cb_msb, in2, zero); + /* + * DEST,C =3D IN1 + ~IN2 + 1. We can produce the same result in f= ewer + * operations by seeding the high word with 1 and subtracting. + */ + TCGv_reg one =3D tcg_constant_reg(1); + tcg_gen_sub2_reg(dest, cb_msb, in1, one, in2, zero); tcg_gen_eqv_reg(cb, in1, in2); tcg_gen_xor_reg(cb, cb, dest); } @@ -1227,7 +1235,7 @@ static void do_sub(DisasContext *ctx, unsigned rt, TC= Gv_reg in1, if (!is_b) { cond =3D do_sub_cond(cf, dest, in1, in2, sv); } else { - cond =3D do_cond(cf, dest, cb_msb, sv); + cond =3D do_cond(cf, dest, get_carry(ctx, d, cb, cb_msb), sv); } =20 /* Emit any conditional trap before any writeback. */ @@ -3019,18 +3027,24 @@ static bool trans_cmpbi(DisasContext *ctx, arg_cmpb= i *a) static bool do_addb(DisasContext *ctx, unsigned r, TCGv_reg in1, unsigned c, unsigned f, unsigned n, int disp) { - TCGv_reg dest, in2, sv, cb_msb; + TCGv_reg dest, in2, sv, cb_cond; DisasCond cond; + bool d =3D false; =20 in2 =3D load_gpr(ctx, r); dest =3D tcg_temp_new(); sv =3D NULL; - cb_msb =3D NULL; + cb_cond =3D NULL; =20 if (cond_need_cb(c)) { - cb_msb =3D tcg_temp_new(); + TCGv_reg cb =3D tcg_temp_new(); + TCGv_reg cb_msb =3D tcg_temp_new(); + tcg_gen_movi_reg(cb_msb, 0); tcg_gen_add2_reg(dest, cb_msb, in1, cb_msb, in2, cb_msb); + tcg_gen_xor_reg(cb, in1, in2); + tcg_gen_xor_reg(cb, cb, dest); + cb_cond =3D get_carry(ctx, d, cb, cb_msb); } else { tcg_gen_add_reg(dest, in1, in2); } @@ -3038,7 +3052,7 @@ static bool do_addb(DisasContext *ctx, unsigned r, TC= Gv_reg in1, sv =3D do_add_sv(ctx, dest, in1, in2); } =20 - cond =3D do_cond(c * 2 + f, dest, cb_msb, sv); + cond =3D do_cond(c * 2 + f, dest, cb_cond, sv); save_gpr(ctx, r, dest); return do_cbranch(ctx, disp, n, &cond); } --=20 2.34.1 From nobody Wed Nov 27 18:51:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1697666484; cv=none; d=zohomail.com; s=zohoarc; b=XUcljg4rrJvHb7/7UMsaTWqrQ5H+fzqtHmRuk6gBGmMnC60FSmynQod2Jco9ja7ql1LrcZhOCylqr5hmjFyRIn2rTPtGxXHStCJMuOjeTp+X+xPwnzorRizb8P1StgxlCShi5bUrbs2CbgdSXUvAZQDfJeSYBQuvpuaIjMCvY0Q= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1697666484; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=+3Cca9a0dUfxOMmsrbDZSCnt4BuRnsfCclCPiSMy9B8=; b=TYbJR1sZxn1TqOjtviAC4z5iRyLRZ2wLFLvWCCRGceKVWPFVD+kOirp3rM0qrOE4pBpfnBj3ymJjiSoW8gJ5fRY7x+MQF/0QgAUvxp5Ki9zbxqn57plsUhth9073N//W0bqGwmcm9fB4m5wQS5N3q1m23c5NpohmTL+JcXNhivQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1697666484214271.7291184154765; Wed, 18 Oct 2023 15:01:24 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qtESl-0001y8-OJ; Wed, 18 Oct 2023 17:52:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qtESE-00015D-IR for qemu-devel@nongnu.org; Wed, 18 Oct 2023 17:51:50 -0400 Received: from mail-oa1-x2a.google.com ([2001:4860:4864:20::2a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qtESA-0004OH-AP for qemu-devel@nongnu.org; Wed, 18 Oct 2023 17:51:49 -0400 Received: by mail-oa1-x2a.google.com with SMTP id 586e51a60fabf-1c0fcbf7ae4so5076552fac.0 for ; Wed, 18 Oct 2023 14:51:45 -0700 (PDT) Received: from stoup.. ([71.212.149.95]) by smtp.gmail.com with ESMTPSA id w17-20020a63f511000000b005b61a024ec7sm2176380pgh.74.2023.10.18.14.51.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Oct 2023 14:51:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1697665905; x=1698270705; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=+3Cca9a0dUfxOMmsrbDZSCnt4BuRnsfCclCPiSMy9B8=; b=FVjQ2RAtxT2KrWlgEhrtiRn00QAYXOTeYlkbbVIN3yG3ng8WFSj96ZMMGaTah4QxFg QMZ1BrMAbIyp5aucF3Roz93ylnmrxIgAXD5GhwbjMbQug3okqnNj9tjDagXUbeOantxE nes0asv+XxAWQ1r6q1DgyVgoCUDVduyoqGiYenI3vB8JzF4VTxDGkVp4p+NMMgzliXit efZJKExF861l9kXuV1k8M8L7gCV49WW7mD+OI7DLkS+QMEAKxqYvFmuTRpQTC3O2Otfv 7C9uVOtLDFpRcz64/8lPV2Xk//7MI8olf00yHe4q022wke98WpL/NO0ZYPVDJDWBOr+6 z/pQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697665905; x=1698270705; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+3Cca9a0dUfxOMmsrbDZSCnt4BuRnsfCclCPiSMy9B8=; b=T3GX8F1zQ0vnFOkU4fRdZ2a8ACmCDSCaw5hTKGYArBbzXJyZBD0zAtgGWXbicy46KG fkVsPWVPU+F9LkjChEgkeJOr+Vh42CmSyvDOVg5UHoJC5lzS/d5SiHLeTOogvs4xOT4k ur9gnZteQO3VPsPsHglAA3kFcQ2/6UjpWVB/wUocfv02MrgYddIo4ZA3xZTN/+Npyc9B +U6/SkUhg/zSJU8vKseKsmsLvprWUlWdPZPOjsAdXhCAAeWr7EqmYtepGmDDeIP59JZq ARCZ4corBOQRucwEkuWCC4jzADGYey/HRX861UVU/vNwH2NTJdbO6Ecut/8WbWb228on 1XLQ== X-Gm-Message-State: AOJu0YxgMAu4LBiRObfjr6ztDbd4r1mzoxDB4oouXHkd1QOMuJQAiyM9 ySgGyTjcPkBLNI4PyHzU5Q6KqWSWTXXWpy0jgds= X-Google-Smtp-Source: AGHT+IHEPmoPeHeiK1hyU8bwnzH2S3Fc8i9VLTYf8jnAoXPIT2l5/4IEoWTO3RFjY7lWAQXR9/Lf7g== X-Received: by 2002:a05:6870:1094:b0:1e9:f0ef:dd8b with SMTP id 20-20020a056870109400b001e9f0efdd8bmr609837oaq.54.1697665905146; Wed, 18 Oct 2023 14:51:45 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH 10/61] target/hppa: Fix bb_sar for hppa64 Date: Wed, 18 Oct 2023 14:50:44 -0700 Message-Id: <20231018215135.1561375-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231018215135.1561375-1-richard.henderson@linaro.org> References: <20231018215135.1561375-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:4860:4864:20::2a; envelope-from=richard.henderson@linaro.org; helo=mail-oa1-x2a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697666484768100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/hppa/translate.c | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 8ebe7523a7..119422870c 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -3073,14 +3073,21 @@ static bool trans_bb_sar(DisasContext *ctx, arg_bb_= sar *a) { TCGv_reg tmp, tcg_r; DisasCond cond; + bool d =3D false; =20 nullify_over(ctx); =20 tmp =3D tcg_temp_new(); tcg_r =3D load_gpr(ctx, a->r); - tcg_gen_shl_reg(tmp, tcg_r, cpu_sar); + if (cond_need_ext(ctx, d)) { + /* Force shift into [32,63] */ + tcg_gen_ori_reg(tmp, cpu_sar, 32); + tcg_gen_shl_reg(tmp, tcg_r, tmp); + } else { + tcg_gen_shl_reg(tmp, tcg_r, cpu_sar); + } =20 - cond =3D cond_make_0(a->c ? TCG_COND_GE : TCG_COND_LT, tmp); + cond =3D cond_make_0_tmp(a->c ? TCG_COND_GE : TCG_COND_LT, tmp); return do_cbranch(ctx, a->disp, a->n, &cond); } =20 @@ -3088,12 +3095,15 @@ static bool trans_bb_imm(DisasContext *ctx, arg_bb_= imm *a) { TCGv_reg tmp, tcg_r; DisasCond cond; + bool d =3D false; + int p; =20 nullify_over(ctx); =20 tmp =3D tcg_temp_new(); tcg_r =3D load_gpr(ctx, a->r); - tcg_gen_shli_reg(tmp, tcg_r, a->p); + p =3D a->p | (cond_need_ext(ctx, d) ? 32 : 0); + tcg_gen_shli_reg(tmp, tcg_r, p); =20 cond =3D cond_make_0(a->c ? TCG_COND_GE : TCG_COND_LT, tmp); return do_cbranch(ctx, a->disp, a->n, &cond); --=20 2.34.1 From nobody Wed Nov 27 18:51:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1697666330; cv=none; d=zohomail.com; s=zohoarc; b=k+R0lx99yF1u36vTgkAmTCU1PU7J2kgPfiSduei2aMiTCGywga3P8x5gee53fovO39yot3uvjsHEDh179urTv9simFq17Zm90JmlLG7HvKy7A6HOyANOy9aN5E0uHV4q2GGfpdwppEvSKWPnJGkt7r8uwhB8dZodSYYUjnHdPV8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1697666330; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=T6DEfOhGSAuzHVOiFy6ZRmh1nqeZSzZi7HDKv5g8+j0=; b=XLVttqG24QTufT4xzXGzvchBDUlIO2K9kEHdKWyL+I34mg2uyMAjO2Y17qNT4vYocHaktFrCdIOSsprPawJT+cN86hzg9HDkzsW9nCcuLZIRcSZ6Mq068Y8HXt6mQysuzXzKRkBCGQauy+uQWqrLfs5hpHPHH0ko0KLEX/K+/mg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1697666330488257.96887355666206; Wed, 18 Oct 2023 14:58:50 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qtESb-0001cz-Hd; Wed, 18 Oct 2023 17:52:13 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qtESE-00015C-I1 for qemu-devel@nongnu.org; Wed, 18 Oct 2023 17:51:50 -0400 Received: from mail-il1-x135.google.com ([2607:f8b0:4864:20::135]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qtESB-0004OU-6b for qemu-devel@nongnu.org; Wed, 18 Oct 2023 17:51:49 -0400 Received: by mail-il1-x135.google.com with SMTP id e9e14a558f8ab-35749078a59so29497765ab.3 for ; Wed, 18 Oct 2023 14:51:46 -0700 (PDT) Received: from stoup.. ([71.212.149.95]) by smtp.gmail.com with ESMTPSA id w17-20020a63f511000000b005b61a024ec7sm2176380pgh.74.2023.10.18.14.51.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Oct 2023 14:51:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1697665906; x=1698270706; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=T6DEfOhGSAuzHVOiFy6ZRmh1nqeZSzZi7HDKv5g8+j0=; b=mAX1CG8eaS2c6s2OMWAjQWUkDDyiAPnzno2nxLyv2r/k9uVfJ/X9/pSs9L4NUlp6To +NPHljC0cb/DrPKRqMYzjJSR7HYjLZGF61H5eJTgwUOb0xiygJfk7G9sTV+9QDjkdAQU zCOcc7d835IIWCcP8wmzgTcm1QnpFdEIx4F+BCXz1J+mDc6hzDP5Wyju9TKdORB6BMhe dvKBRoSOyCQsL4bbcKm9DzHdb4nO6yxnigDcnHfz/mldNqo/rofm9d8SUrHdYBjOFTil ekiAIP/Yizl6NXbYBpF/+e06yAdefinB1676CLoXfLYct6zMGK21f5yq6EfnShpTIiwK PQSA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697665906; x=1698270706; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=T6DEfOhGSAuzHVOiFy6ZRmh1nqeZSzZi7HDKv5g8+j0=; b=guZi7vEECwSVvQlJBqbHKIyKkXD1vZ0WxOZ45upMOtWywgr3zTMxXhiOhk0iuqiKHM rMNexcMLsdwlxjmf5LNMgRha8Mdj5Zhe97Egix5R3dg4IW1Omq4IyLAmTn5vmi1rw7Tf i7BvjXcY/M/IymrSRBXLGCdITbhbo1Ai7+btTfGp0kI74nnpfgjeeGdwEvHVvfhgmsUi Xys5m9iA5/zYJR73yE9/mo1s4dKCudPRhTo6uT6GNb16D4k6y5MXrKdsfY4Oxd2HK4/O yrhHwmLwVgXLsOP4JISe56kDRtfPD937E4R33DllfB+R6ruCjS1AUK+N7sc1DzFzB88S PELw== X-Gm-Message-State: AOJu0YyIbn3wSs9ROW6tq7ScKYg7V5JEBrludFcxmckj3IO8tJXKoxWE KTWezIIUoiwKUCXNT0XN+/NEdiwVUFoqq6y6gP4= X-Google-Smtp-Source: AGHT+IF9c4+NsvBZhHxRGkjfJ8Wu2w/FNsbrkV2oI1v/n/t3sAGHgaKxLt6T+/LpVxbiKpC4x3b4UA== X-Received: by 2002:a05:6e02:b4b:b0:357:627a:52 with SMTP id f11-20020a056e020b4b00b00357627a0052mr761487ilu.28.1697665905976; Wed, 18 Oct 2023 14:51:45 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH 11/61] target/hppa: Fix extrw and depw with sar for hppa64 Date: Wed, 18 Oct 2023 14:50:45 -0700 Message-Id: <20231018215135.1561375-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231018215135.1561375-1-richard.henderson@linaro.org> References: <20231018215135.1561375-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::135; envelope-from=richard.henderson@linaro.org; helo=mail-il1-x135.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697666332097100007 Content-Type: text/plain; charset="utf-8" These are 32-bit operations regardless of processor. Signed-off-by: Richard Henderson --- target/hppa/translate.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 119422870c..f86ea9b9ca 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -3230,7 +3230,9 @@ static bool trans_extrw_sar(DisasContext *ctx, arg_ex= trw_sar *a) tmp =3D tcg_temp_new(); =20 /* Recall that SAR is using big-endian bit numbering. */ - tcg_gen_xori_reg(tmp, cpu_sar, TARGET_REGISTER_BITS - 1); + tcg_gen_andi_reg(tmp, cpu_sar, 31); + tcg_gen_xori_reg(tmp, tmp, 31); + if (a->se) { tcg_gen_sar_reg(dest, src, tmp); tcg_gen_sextract_reg(dest, dest, 0, len); @@ -3355,7 +3357,8 @@ static bool do_depw_sar(DisasContext *ctx, unsigned r= t, unsigned c, tmp =3D tcg_temp_new(); =20 /* Convert big-endian bit numbering in SAR to left-shift. */ - tcg_gen_xori_reg(shift, cpu_sar, TARGET_REGISTER_BITS - 1); + tcg_gen_andi_reg(shift, cpu_sar, 31); + tcg_gen_xori_reg(shift, shift, 31); =20 mask =3D tcg_temp_new(); tcg_gen_movi_reg(mask, msb + (msb - 1)); --=20 2.34.1 From nobody Wed Nov 27 18:51:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1697666066; cv=none; d=zohomail.com; s=zohoarc; b=IdyAqv8Bp8mLKky+Tg6QrFZjjutC2DRkmKFb+tySGVqggLiqx2ufeP8GRpgBQRw5cBBOZzS1QT7ZBzRC53Ly2rgCgHy6gPS4CR7rqoVJZI7hX9rShkdykywn3ml6C6YyEiwHmtn+vyFWy0jnjndjAVrCg2b8DD/bg6LhodToPcM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1697666066; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=cjdPIOgHmvrr+30vbWYAH4JEvq1rx9Ce0rUnUJEWHoQ=; b=TaOE4Tdhv13THELMuBQGat5h1J+QnAKEs7yuUF2d3xkCkhZNkr26EsYSP4buiqsnKTGdNtV4CcvaCT3Dx5n/8ucZTYOreKyzcamylZYYgMOXTIaByC78jhiCw9M0NHGCD34k7y7PpY/SFPmrtwjR+iHFfDA9CPwhGzv8mMhj9g4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1697666066408619.893463800442; Wed, 18 Oct 2023 14:54:26 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qtESN-00018r-R2; Wed, 18 Oct 2023 17:52:01 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qtESE-00015E-Ia for qemu-devel@nongnu.org; Wed, 18 Oct 2023 17:51:50 -0400 Received: from mail-oa1-x2d.google.com ([2001:4860:4864:20::2d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qtESB-0004Oa-PP for qemu-devel@nongnu.org; Wed, 18 Oct 2023 17:51:49 -0400 Received: by mail-oa1-x2d.google.com with SMTP id 586e51a60fabf-1ea82246069so1519476fac.3 for ; Wed, 18 Oct 2023 14:51:47 -0700 (PDT) Received: from stoup.. ([71.212.149.95]) by smtp.gmail.com with ESMTPSA id w17-20020a63f511000000b005b61a024ec7sm2176380pgh.74.2023.10.18.14.51.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Oct 2023 14:51:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1697665906; x=1698270706; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=cjdPIOgHmvrr+30vbWYAH4JEvq1rx9Ce0rUnUJEWHoQ=; b=SeD0Az0dBHb7xSoXjFMGlJbSuXXxDlZj/nB5zduenr34ujmDZMFUrg8ajQivjvNSHe QJXPddKJlyc6WVlOn6HVn6pQeeVeUoPJ5Rf8xnkKoHJJ9YiBAyNg1qaZXJTzVnJLOBbI vg7KMo01RkKPSL5rRWSurFkKptsi23R2hR9lJI4n6MveBsCgXxgPXGoE4seSIR/Jchd0 PX0oDxtx6dUWuJcoBUBPBE2BNq8KtdQr7WFLv7EePJyRVhO60plY5QvTvq9utcug0EfE wDQldeX8pKHGcq2xrTwveH96McjTaMNSH6tu3BUIVvQv5S6HCPHSPX4iFQQiXkrHpp2p PgLQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697665906; x=1698270706; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=cjdPIOgHmvrr+30vbWYAH4JEvq1rx9Ce0rUnUJEWHoQ=; b=T1L7A4xYcgn26mg5So6j00jU6eLpNJ2+H/zurqrimQb1aavKc66yXofW/0nQCl4QEh PV6QgAbV2BN3u18hmG5KYjn2gz1oho9lsT3yVD8rTSwS3KYjRtY0LzyW2tckiPYRGYYv GhvJ6srgfyjrmsFpHm8qbyRzUSaeufskp6IGJWbKUvmFnLzdX7TrsBPkmQ/Uco4hMTom zS3G4zNIehXJYsTCXbe9Sp5K2y3LqKOroMES5GsfhOFDX8+wwcvsdgVyOzPnb2eItM2I hYi5dUdJSu5IIHRU710GdmVqonXZhUe/KwRS9EU2+eXReo1WYah5qJtjTEJP4JuYjZIY DWRg== X-Gm-Message-State: AOJu0YyoR89mSVogSrmdvN8642Sf7PkaeOecF+NJhaTxGhUlCoxxoqNb B8QEWXIIgc/BBfp0GPnom+JfO0LiDj2dSnHmhDA= X-Google-Smtp-Source: AGHT+IE72wZEgbzWcSF1B2tVVJJos6PkL59U5SUugE2SWxzwn7ZiY763xj11NntGRAsVJeWsCay7IA== X-Received: by 2002:a05:6870:cb82:b0:1ea:478c:a26b with SMTP id ov2-20020a056870cb8200b001ea478ca26bmr788073oab.9.1697665906695; Wed, 18 Oct 2023 14:51:46 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH 12/61] target/hppa: Introduce TYPE_HPPA64_CPU Date: Wed, 18 Oct 2023 14:50:46 -0700 Message-Id: <20231018215135.1561375-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231018215135.1561375-1-richard.henderson@linaro.org> References: <20231018215135.1561375-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:4860:4864:20::2d; envelope-from=richard.henderson@linaro.org; helo=mail-oa1-x2d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697666068605100003 Content-Type: text/plain; charset="utf-8" Prepare for the qemu binary supporting both pa10 and pa20 at the same time. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/hppa/cpu-qom.h | 1 + target/hppa/cpu.h | 7 +++++++ target/hppa/cpu.c | 17 +++++++++++++++++ target/hppa/translate.c | 3 +++ 4 files changed, 28 insertions(+) diff --git a/target/hppa/cpu-qom.h b/target/hppa/cpu-qom.h index b96e0318c7..4a85ebf5e0 100644 --- a/target/hppa/cpu-qom.h +++ b/target/hppa/cpu-qom.h @@ -24,6 +24,7 @@ #include "qom/object.h" =20 #define TYPE_HPPA_CPU "hppa-cpu" +#define TYPE_HPPA64_CPU "hppa64-cpu" =20 OBJECT_DECLARE_CPU_TYPE(HPPACPU, HPPACPUClass, HPPA_CPU) =20 diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 798d0c26d7..743fc90e14 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -239,10 +239,17 @@ struct ArchCPU { =20 CPUHPPAState env; QEMUTimer *alarm_timer; + + bool is_pa20; }; =20 #include "exec/cpu-all.h" =20 +static inline bool hppa_is_pa20(HPPACPU *cpu) +{ + return cpu->is_pa20; +} + static inline int cpu_mmu_index(CPUHPPAState *env, bool ifetch) { #ifdef CONFIG_USER_ONLY diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 1644297bf8..ed5b6afd10 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -218,9 +218,26 @@ static const TypeInfo hppa_cpu_type_info =3D { .class_init =3D hppa_cpu_class_init, }; =20 +#ifdef TARGET_HPPA64 +static void hppa64_cpu_initfn(Object *obj) +{ + HPPACPU *cpu =3D HPPA_CPU(obj); + cpu->is_pa20 =3D true; +} + +static const TypeInfo hppa64_cpu_type_info =3D { + .name =3D TYPE_HPPA64_CPU, + .parent =3D TYPE_HPPA_CPU, + .instance_init =3D hppa64_cpu_initfn, +}; +#endif + static void hppa_cpu_register_types(void) { type_register_static(&hppa_cpu_type_info); +#ifdef TARGET_HPPA64 + type_register_static(&hppa64_cpu_type_info); +#endif } =20 type_init(hppa_cpu_register_types) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index f86ea9b9ca..9d6670f91c 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -262,6 +262,7 @@ typedef struct DisasContext { int mmu_idx; int privilege; bool psw_n_nonzero; + bool is_pa20; =20 #ifdef CONFIG_USER_ONLY MemOp unalign; @@ -4087,10 +4088,12 @@ static bool trans_diag(DisasContext *ctx, arg_diag = *a) static void hppa_tr_init_disas_context(DisasContextBase *dcbase, CPUState = *cs) { DisasContext *ctx =3D container_of(dcbase, DisasContext, base); + HPPACPU *cpu =3D HPPA_CPU(cs); int bound; =20 ctx->cs =3D cs; ctx->tb_flags =3D ctx->base.tb->flags; + ctx->is_pa20 =3D cpu->is_pa20; =20 #ifdef CONFIG_USER_ONLY ctx->privilege =3D MMU_IDX_TO_PRIV(MMU_USER_IDX); --=20 2.34.1 From nobody Wed Nov 27 18:51:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1697666004; cv=none; d=zohomail.com; s=zohoarc; b=kNLAhXxcG0OUVo3bvZHvzjzvMQIvHZNmXrIUxN/vi+Y/+j7n4Ho7ehYrzZy/UcpalOrrtSJQ6oCFFkMsOz046g30WtEMzMAPlfTZ43aAQLgiXKkb/AdpgiXlf5UxAOWwsqnwHvY8GsclqREtdKXjgYJw70NiGIEHJ4XiBP5ADB8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1697666004; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=4w9TuqB+Wh/IgMQszmtMNOuKxNZ/aMG7k6ZFrv3n6zg=; b=ZGLGtANhRnGUZCzFthv7Dy3hcp6Y6PKslJrKhn43o8ihsfTBn4JCEB7rJzOkW6hWrTz75JQOBWQv+/2taAIvq/iOt5fcIAWbql0EWa41Cb1juqlRYEDpR+MYfLe5sAtIP1vEuZAYu/LYVl84KDvoK8lshg0PgOheSlLXcc4TQrI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1697666004122617.6894371765393; Wed, 18 Oct 2023 14:53:24 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qtESQ-000196-Fz; Wed, 18 Oct 2023 17:52:05 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qtESF-00016t-54 for qemu-devel@nongnu.org; Wed, 18 Oct 2023 17:51:51 -0400 Received: from mail-oo1-xc2e.google.com ([2607:f8b0:4864:20::c2e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qtESC-0004Oq-Lp for qemu-devel@nongnu.org; Wed, 18 Oct 2023 17:51:50 -0400 Received: by mail-oo1-xc2e.google.com with SMTP id 006d021491bc7-57be3d8e738so4124982eaf.1 for ; Wed, 18 Oct 2023 14:51:48 -0700 (PDT) Received: from stoup.. ([71.212.149.95]) by smtp.gmail.com with ESMTPSA id w17-20020a63f511000000b005b61a024ec7sm2176380pgh.74.2023.10.18.14.51.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Oct 2023 14:51:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1697665907; x=1698270707; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=4w9TuqB+Wh/IgMQszmtMNOuKxNZ/aMG7k6ZFrv3n6zg=; b=f1fPYWVYztKEg0hCwjFVvX5Yspy4GcWq+q+jPstbdfPN0Povgw1etSBhXj6F3xm9W0 /zMysTA2j8BRh9WMsxIX/U95/48nBRUY6zgC5FCuK3Fys8wUlj4zN/+6RIwid9etY3+z yVfm53FiDRnaOF+Eia1Y2n0VIe9r3YEZhqH7eGqACGyPinJVPC6MvcV0VCCgvFaYMhEf Xkuhuv2WPz9SJ+ELUtFDCDD7/CRGApyK7TWEJsNpf/1SglCphG7UUV7Z9MHKwjYW7art rGRE7TYhmFEGKFXajHWnHuonsKFovBcQfCYxJ6rXpTmKP0R/KIXqwMF2U5aNdQF4N4gO 6DGQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697665907; x=1698270707; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=4w9TuqB+Wh/IgMQszmtMNOuKxNZ/aMG7k6ZFrv3n6zg=; b=bZ+545h6MMvk+5/adbfPGJ8jBPVsJuYSP1rxKcZmCuOnKc45OxTde6Xb9gr2J0aiaM ySm2TFILTxZjKcrgUkK9I/AiTuje7fS7F+XTDN/oqns2FI4VdHRxoatoKLg9grOIKJ/3 LQRKmyJ6kOJS3k06ZOdCaCkqgRy3xkQBTxPs0K/ZsH5ErWju4rlYBfwLMxw+W/HBDFwg VeJEr3pwhsSYcCtzFCtHyx1taETzGWu3vxxL71bnbfiooRtePUYKB40tTHZqNRgVnle4 5Ren2zEW7q5rHsQcF5TmIvRJ0TDSjEpaDZano0ukOf5UGb/UNhmaxaZbaP4Sk9zC1Szb Kw/g== X-Gm-Message-State: AOJu0YyCTGQwggZvYtmBoOqUL67CIx9kFbyXkmuFGZsjybeBMIVFQAuy 7lWj4DM3rNyvpGVF9EC8jdko22obAHx7QjpFg5o= X-Google-Smtp-Source: AGHT+IG6etGpjL+sjmEnIMrCxBC4n0MaKCbL5hTWGjxuhouHDEXC1TYejWAe1HvSV7PxPH2edZBmwg== X-Received: by 2002:a05:6358:c683:b0:141:8c:75ad with SMTP id fe3-20020a056358c68300b00141008c75admr262733rwb.28.1697665907467; Wed, 18 Oct 2023 14:51:47 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH 13/61] target/hppa: Make HPPA_BTLB_ENTRIES variable Date: Wed, 18 Oct 2023 14:50:47 -0700 Message-Id: <20231018215135.1561375-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231018215135.1561375-1-richard.henderson@linaro.org> References: <20231018215135.1561375-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::c2e; envelope-from=richard.henderson@linaro.org; helo=mail-oo1-xc2e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697666004393100002 Content-Type: text/plain; charset="utf-8" Depend on !HPPACPU.is_pa20. Signed-off-by: Richard Henderson --- target/hppa/cpu.h | 16 ++++++++-------- hw/hppa/machine.c | 6 +----- target/hppa/cpu.c | 3 +++ target/hppa/mem_helper.c | 41 ++++++++++++++++++++++------------------ 4 files changed, 35 insertions(+), 31 deletions(-) diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 743fc90e14..22690e351d 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -210,15 +210,15 @@ typedef struct CPUArchState { target_ureg cr_back[2]; /* back of cr17/cr18 */ target_ureg shadow[7]; /* shadow registers */ =20 - /* ??? The number of entries isn't specified by the architecture. */ -#ifdef TARGET_HPPA64 -#define HPPA_BTLB_FIXED 0 /* BTLBs are not supported in 64-b= it machines */ -#else -#define HPPA_BTLB_FIXED 16 -#endif -#define HPPA_BTLB_VARIABLE 0 + /* + * ??? The number of entries isn't specified by the architecture. + * BTLBs are not supported in 64-bit machines. + */ +#define PA10_BTLB_FIXED 16 +#define PA10_BTLB_VARIABLE 0 +#define HPPA_BTLB_ENTRIES(E) (env_archcpu(E)->is_pa20 ? 0 \ + : PA10_BTLB_FIXED + PA10_BTLB_VARIABLE) #define HPPA_TLB_ENTRIES 256 -#define HPPA_BTLB_ENTRIES (HPPA_BTLB_FIXED + HPPA_BTLB_VARIABLE) =20 /* ??? Implement a unified itlb/dtlb for the moment. */ /* ??? We should use a more intelligent data structure. */ diff --git a/hw/hppa/machine.c b/hw/hppa/machine.c index cf28cb9586..07f8ebeb6a 100644 --- a/hw/hppa/machine.c +++ b/hw/hppa/machine.c @@ -133,7 +133,7 @@ static FWCfgState *create_fw_cfg(MachineState *ms) fw_cfg_add_file(fw_cfg, "/etc/firmware-min-version", g_memdup(&val, sizeof(val)), sizeof(val)); =20 - val =3D cpu_to_le64(HPPA_TLB_ENTRIES - HPPA_BTLB_ENTRIES); + val =3D cpu_to_le64(HPPA_TLB_ENTRIES - HPPA_BTLB_ENTRIES(&cpu[0]->env)= ); fw_cfg_add_file(fw_cfg, "/etc/cpu/tlb_entries", g_memdup(&val, sizeof(val)), sizeof(val)); =20 @@ -429,10 +429,6 @@ static void hppa_machine_reset(MachineState *ms, Shutd= ownCause reason) =20 cs->exception_index =3D -1; cs->halted =3D 0; - - /* clear any existing TLB and BTLB entries */ - memset(cpu[i]->env.tlb, 0, sizeof(cpu[i]->env.tlb)); - cpu[i]->env.tlb_last =3D HPPA_BTLB_ENTRIES; } =20 /* already initialized by machine_hppa_init()? */ diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index ed5b6afd10..41abdb04d0 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -139,6 +139,9 @@ static void hppa_cpu_realizefn(DeviceState *dev, Error = **errp) HPPACPU *cpu =3D HPPA_CPU(cs); cpu->alarm_timer =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, hppa_cpu_alarm_timer, cpu); + + memset(cpu->env.tlb, 0, sizeof(cpu->env.tlb)); + cpu->env.tlb_last =3D HPPA_BTLB_ENTRIES(&cpu->env); } #endif } diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c index 350485f619..b2a75f6408 100644 --- a/target/hppa/mem_helper.c +++ b/target/hppa/mem_helper.c @@ -57,7 +57,7 @@ static void hppa_flush_tlb_ent(CPUHPPAState *env, hppa_tl= b_entry *ent, HPPA_MMU_FLUSH_MASK, TARGET_LONG_BITS); =20 /* never clear BTLBs, unless forced to do so. */ - if (ent < &env->tlb[HPPA_BTLB_ENTRIES] && !force_flush_btlb) { + if (ent < &env->tlb[HPPA_BTLB_ENTRIES(env)] && !force_flush_btlb) { return; } =20 @@ -68,11 +68,11 @@ static void hppa_flush_tlb_ent(CPUHPPAState *env, hppa_= tlb_entry *ent, static hppa_tlb_entry *hppa_alloc_tlb_ent(CPUHPPAState *env) { hppa_tlb_entry *ent; - uint32_t i; + uint32_t i, btlb_entries =3D HPPA_BTLB_ENTRIES(env); =20 - if (env->tlb_last < HPPA_BTLB_ENTRIES || env->tlb_last >=3D ARRAY_SIZE= (env->tlb)) { - i =3D HPPA_BTLB_ENTRIES; - env->tlb_last =3D HPPA_BTLB_ENTRIES + 1; + if (env->tlb_last < btlb_entries || env->tlb_last >=3D ARRAY_SIZE(env-= >tlb)) { + i =3D btlb_entries; + env->tlb_last =3D btlb_entries + 1; } else { i =3D env->tlb_last; env->tlb_last++; @@ -279,7 +279,7 @@ void HELPER(itlba)(CPUHPPAState *env, target_ulong addr= , target_ureg reg) int i; =20 /* Zap any old entries covering ADDR; notice empty entries on the way.= */ - for (i =3D HPPA_BTLB_ENTRIES; i < ARRAY_SIZE(env->tlb); ++i) { + for (i =3D HPPA_BTLB_ENTRIES(env); i < ARRAY_SIZE(env->tlb); ++i) { hppa_tlb_entry *ent =3D &env->tlb[i]; if (ent->va_b <=3D addr && addr <=3D ent->va_e) { if (ent->entry_valid) { @@ -363,11 +363,13 @@ void HELPER(ptlb)(CPUHPPAState *env, target_ulong add= r) number of pages/entries (we choose all), and is local to the cpu. */ void HELPER(ptlbe)(CPUHPPAState *env) { + uint32_t btlb_entries =3D HPPA_BTLB_ENTRIES(env); + trace_hppa_tlb_ptlbe(env); qemu_log_mask(CPU_LOG_MMU, "FLUSH ALL TLB ENTRIES\n"); - memset(&env->tlb[HPPA_BTLB_ENTRIES], 0, - sizeof(env->tlb) - HPPA_BTLB_ENTRIES * sizeof(env->tlb[0])); - env->tlb_last =3D HPPA_BTLB_ENTRIES; + memset(&env->tlb[btlb_entries], 0, + sizeof(env->tlb) - btlb_entries * sizeof(env->tlb[0])); + env->tlb_last =3D btlb_entries; tlb_flush_by_mmuidx(env_cpu(env), HPPA_MMU_FLUSH_MASK); } =20 @@ -427,13 +429,16 @@ void HELPER(diag_btlb)(CPUHPPAState *env) hppa_tlb_entry *btlb; uint64_t virt_page; uint32_t *vaddr; + uint32_t btlb_entries; =20 -#ifdef TARGET_HPPA64 /* BTLBs are not supported on 64-bit CPUs */ - env->gr[28] =3D -1; /* nonexistent procedure */ - return; -#endif + if (env_archcpu(env)->is_pa20) { + env->gr[28] =3D -1; /* nonexistent procedure */ + return; + } + env->gr[28] =3D 0; /* PDC_OK */ + btlb_entries =3D HPPA_BTLB_ENTRIES(env); =20 switch (env->gr[25]) { case 0: @@ -446,8 +451,8 @@ void HELPER(diag_btlb)(CPUHPPAState *env) } else { vaddr[0] =3D cpu_to_be32(1); vaddr[1] =3D cpu_to_be32(16 * 1024); - vaddr[2] =3D cpu_to_be32(HPPA_BTLB_FIXED); - vaddr[3] =3D cpu_to_be32(HPPA_BTLB_VARIABLE); + vaddr[2] =3D cpu_to_be32(PA10_BTLB_FIXED); + vaddr[3] =3D cpu_to_be32(PA10_BTLB_VARIABLE); } break; case 1: @@ -464,7 +469,7 @@ void HELPER(diag_btlb)(CPUHPPAState *env) (long long) virt_page << TARGET_PAGE_BITS, (long long) (virt_page + len) << TARGET_PAGE_BITS, (long long) virt_page, phys_page, len, slot); - if (slot < HPPA_BTLB_ENTRIES) { + if (slot < btlb_entries) { btlb =3D &env->tlb[slot]; /* force flush of possibly existing BTLB entry */ hppa_flush_tlb_ent(env, btlb, true); @@ -484,7 +489,7 @@ void HELPER(diag_btlb)(CPUHPPAState *env) slot =3D env->gr[22]; qemu_log_mask(CPU_LOG_MMU, "PDC_BLOCK_TLB: PDC_BTLB_PURGE slot %d\= n", slot); - if (slot < HPPA_BTLB_ENTRIES) { + if (slot < btlb_entries) { btlb =3D &env->tlb[slot]; hppa_flush_tlb_ent(env, btlb, true); } else { @@ -494,7 +499,7 @@ void HELPER(diag_btlb)(CPUHPPAState *env) case 3: /* Purge all BTLB entries */ qemu_log_mask(CPU_LOG_MMU, "PDC_BLOCK_TLB: PDC_BTLB_PURGE_ALL\n"); - for (slot =3D 0; slot < HPPA_BTLB_ENTRIES; slot++) { + for (slot =3D 0; slot < btlb_entries; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42d; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697666428378100003 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/hppa/cpu.h | 5 +++++ target/hppa/cpu.c | 24 ++++++++++++++++++++++++ 2 files changed, 29 insertions(+) diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 22690e351d..30010858a9 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -365,4 +365,9 @@ int hppa_artype_for_page(CPUHPPAState *env, target_ulon= g vaddr); #endif G_NORETURN void hppa_dynamic_excp(CPUHPPAState *env, int excp, uintptr_t r= a); =20 +#define CPU_RESOLVING_TYPE TYPE_HPPA_CPU + +#define cpu_list hppa_cpu_list +void hppa_cpu_list(void); + #endif /* HPPA_CPU_H */ diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 41abdb04d0..1975aa9621 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -162,6 +162,30 @@ static ObjectClass *hppa_cpu_class_by_name(const char = *cpu_model) return object_class_by_name(TYPE_HPPA_CPU); } =20 +static void hppa_cpu_list_entry(gpointer data, gpointer user_data) +{ + ObjectClass *oc =3D data; + CPUClass *cc =3D CPU_CLASS(oc); + const char *tname =3D object_class_get_name(oc); + g_autofree char *name =3D g_strndup(tname, strchr(tname, '-') - tname); + + if (cc->deprecation_note) { + qemu_printf(" %s (deprecated)\n", name); + } else { + qemu_printf(" %s\n", name); + } +} + +void hppa_cpu_list(void) +{ + GSList *list; + + list =3D object_class_get_list_sorted(TYPE_HPPA_CPU, false); + qemu_printf("Available CPUs:\n"); + g_slist_foreach(list, hppa_cpu_list_entry, NULL); + g_slist_free(list); +} + #ifndef CONFIG_USER_ONLY #include "hw/core/sysemu-cpu-ops.h" =20 --=20 2.34.1 From nobody Wed Nov 27 18:51:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1697666046; cv=none; d=zohomail.com; s=zohoarc; b=P5xZWqw6soIFYGYOhB2TDzktTkYravKWtO8O/N83bdXXMbG6ZLSci/W80ZM6jaYs8+6Uyh2LnL02iuOXHYZqaNafjV2fJL/eSc9ar9IGbxV9fnX7A0e5RVsxme5YFnfxjBind3KJsxWxVaLW2KKUZHX2KaLkJlAZcc50gGI0XfQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1697666046; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::32a; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697666048510100003 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- linux-user/hppa/target_elf.h | 2 +- target/hppa/cpu.c | 10 +++++++++- 2 files changed, 10 insertions(+), 2 deletions(-) diff --git a/linux-user/hppa/target_elf.h b/linux-user/hppa/target_elf.h index 82b4e9535e..9bb865ae92 100644 --- a/linux-user/hppa/target_elf.h +++ b/linux-user/hppa/target_elf.h @@ -9,6 +9,6 @@ #define HPPA_TARGET_ELF_H static inline const char *cpu_get_model(uint32_t eflags) { - return "any"; + return TYPE_HPPA_CPU; } #endif diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 1975aa9621..6bf415139f 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -159,7 +159,15 @@ static void hppa_cpu_initfn(Object *obj) =20 static ObjectClass *hppa_cpu_class_by_name(const char *cpu_model) { - return object_class_by_name(TYPE_HPPA_CPU); + g_autofree char *typename =3D g_strconcat(cpu_model, "-cpu", NULL); + ObjectClass *oc =3D object_class_by_name(typename); + + if (oc && + !object_class_is_abstract(oc) && + object_class_dynamic_cast(oc, TYPE_HPPA_CPU)) { + return oc; + } + return NULL; } =20 static void hppa_cpu_list_entry(gpointer data, gpointer user_data) --=20 2.34.1 From nobody Wed Nov 27 18:51:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id w17-20020a63f511000000b005b61a024ec7sm2176380pgh.74.2023.10.18.14.51.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Oct 2023 14:51:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1697665910; x=1698270710; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=KPk9VlCAjpCD8p3ZbSvb+o08mQKrjmWkggjvcwFuWFk=; b=rFx9Bv/MTRbEoI4GcHbtb8Ev+Jvvyq9OUZ/WSft2c1xZ2FC8EZ5GtC3iS5bt702Tzg osooo9FGLK2xF8Z6TZe4VFDx8AX4Him8ctHBKa+1zgfWg7EuiCwvGu/0pv2NipOJBFui Hmt4fjUje5lzW1ddI6fKVOIpmU0bG/hIoJ+qgyPCde2XGDnJqpuht6C4S/waMDFo8OKA XnRcjLzUB6P5BHFr+I52wDPZid/WTAWFdJorKnqYLUKz8Bpp6mvLQCekumga8T0deIHq 7BRgIbcMHzIC/X3iwVMMOdRpo/4AOTpMjj/BXfFLRn/MNSVXVnPetiu8avsdVLwJb2qc oMww== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697665910; x=1698270710; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=KPk9VlCAjpCD8p3ZbSvb+o08mQKrjmWkggjvcwFuWFk=; b=fg7Qup6fkhUljhWWztdEq5p/6iwHB+bcK/tzTHZkwpNe/WzRLVv9TJp+zqWkXD5cqD pRv25h2cDaOC2l2C6Uo3yavJi/+RA92LZMPLaF6exnGAxzztos1eS75wZjBw2MecoGCs SIr4lPkBvNuca6/IsQOAy3wOlPmU4l6WRkOE5IBGB0mPtam7NxMYY1A7Q7DBqLU2AyO9 5Bw3bKTrvcWzW58nmZ4pFGDz8xmB3dcxBUpweaEEd8uXWW8Sq29FDCYDu6Y0wLwexTME 1Cc8O+RyhG3yNrhgik+5ZYCnwD2ErTvbSPTZDSiUbvE7F7YVb0W+xRVxC6ymIy2X9ice xf6w== X-Gm-Message-State: AOJu0Yy8+ygBWLd5SHp7rcM0WVnPHe7FwrkYGhWT4j3A/yD8KQAJNqjN Hw56SXg8EmFqvHj6PyyKUFfvJ5w7QSs8W3liZPk= X-Google-Smtp-Source: AGHT+IEu6lRcHaIH6mRZQWe+8u9dv1OSOVnVU2fUalGkde9aQEE9LM9o15ALjEopuAivZFuX5aQ4Dw== X-Received: by 2002:a05:6359:6e8c:b0:166:e779:7ce7 with SMTP id ti12-20020a0563596e8c00b00166e7797ce7mr212479rwb.32.1697665909864; Wed, 18 Oct 2023 14:51:49 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH 16/61] target/hppa: Update cpu_hppa_get/put_psw for hppa64 Date: Wed, 18 Oct 2023 14:50:50 -0700 Message-Id: <20231018215135.1561375-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231018215135.1561375-1-richard.henderson@linaro.org> References: <20231018215135.1561375-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::c2b; envelope-from=richard.henderson@linaro.org; helo=mail-oo1-xc2b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697666289442100003 Content-Type: text/plain; charset="utf-8" With 64-bit registers, there are 16 carry bits in the PSW. Clear reserved bits based on cpu revision. Signed-off-by: Richard Henderson --- target/hppa/helper.c | 63 ++++++++++++++++++++++++++++++++++++-------- 1 file changed, 52 insertions(+), 11 deletions(-) diff --git a/target/hppa/helper.c b/target/hppa/helper.c index a8d3f456ee..40e859ba08 100644 --- a/target/hppa/helper.c +++ b/target/hppa/helper.c @@ -28,19 +28,35 @@ target_ureg cpu_hppa_get_psw(CPUHPPAState *env) { target_ureg psw; + target_ureg mask1 =3D (target_ureg)-1 / 0xf; + target_ureg maskf =3D (target_ureg)-1 / 0xffff * 0xf; =20 /* Fold carry bits down to 8 consecutive bits. */ - /* ??? Needs tweaking for hppa64. */ - /* .......b...c...d...e...f...g...h */ - psw =3D (env->psw_cb >> 4) & 0x01111111; - /* .......b..bc..cd..de..ef..fg..gh */ + /* ^^^b^^^c^^^d^^^e^^^f^^^g^^^h^^^i^^^j^^^k^^^l^^^m^^^n^^^o^^^p^^^^ */ + /* ^^^b^^^c^^^d^^^e^^^f^^^g^^^h^^^^ */ + psw =3D (env->psw_cb >> 4) & mask1; + /* .......b...c...d...e...f...g...h...i...j...k...l...m...n...o...p */ + /* .......b...c...d...e...f...g...h */ psw |=3D psw >> 3; - /* .............bcd............efgh */ - psw |=3D (psw >> 6) & 0x000f000f; - /* .........................bcdefgh */ - psw |=3D (psw >> 12) & 0xf; - psw |=3D env->psw_cb_msb << 7; - psw =3D (psw & 0xff) << 8; + /* .......b..bc..cd..de..ef..fg..gh..hi..ij..jk..kl..lm..mn..no..op */ + /* .......b..bc..cd..de..ef..fg..gh */ + psw |=3D psw >> 6; + psw &=3D maskf; + /* .............bcd............efgh............ijkl............mnop */ + /* .............bcd............efgh */ + psw |=3D psw >> 12; + /* .............bcd.........bcdefgh........efghijkl........ijklmnop */ + /* .............bcd.........bcdefgh */ + psw |=3D env->psw_cb_msb << (TARGET_REGISTER_BITS =3D=3D 64 ? 39 : 7); + /* .............bcd........abcdefgh........efghijkl........ijklmnop */ + /* .............bcd........abcdefgh */ + + /* For hppa64, the two 8-bit fields are discontiguous. */ + if (env_archcpu(env)->is_pa20) { + psw =3D (psw & 0xff00000000ull) | ((psw & 0xff) << 8); + } else { + psw =3D (psw & 0xff) << 8; + } =20 psw |=3D env->psw_n * PSW_N; psw |=3D (env->psw_v < 0) * PSW_V; @@ -51,14 +67,39 @@ target_ureg cpu_hppa_get_psw(CPUHPPAState *env) =20 void cpu_hppa_put_psw(CPUHPPAState *env, target_ureg psw) { + uint64_t reserved; target_ureg old_psw =3D env->psw; target_ureg cb =3D 0; =20 + /* Do not allow reserved bits to be set. */ + if (env_archcpu(env)->is_pa20) { + reserved =3D MAKE_64BIT_MASK(40, 24) | MAKE_64BIT_MASK(28, 4); + reserved |=3D PSW_G; /* PA1.x only */ + reserved |=3D PSW_E; /* not implemented */ + } else { + reserved =3D MAKE_64BIT_MASK(32, 32) | MAKE_64BIT_MASK(28, 2); + reserved |=3D PSW_O | PSW_W; /* PA2.0 only */ + reserved |=3D PSW_E | PSW_Y | PSW_Z; /* not implemented */ + } + psw &=3D ~reserved; + env->psw =3D psw & ~(PSW_N | PSW_V | PSW_CB); env->psw_n =3D (psw / PSW_N) & 1; env->psw_v =3D -((psw / PSW_V) & 1); - env->psw_cb_msb =3D (psw >> 15) & 1; =20 +#if TARGET_REGISTER_BITS =3D=3D 32 + env->psw_cb_msb =3D (psw >> 15) & 1; +#else + env->psw_cb_msb =3D (psw >> 39) & 1; + cb |=3D ((psw >> 38) & 1) << 60; + cb |=3D ((psw >> 37) & 1) << 56; + cb |=3D ((psw >> 36) & 1) << 52; + cb |=3D ((psw >> 35) & 1) << 48; + cb |=3D ((psw >> 34) & 1) << 44; + cb |=3D ((psw >> 33) & 1) << 40; + cb |=3D ((psw >> 32) & 1) << 36; + cb |=3D ((psw >> 15) & 1) << 32; +#endif cb |=3D ((psw >> 14) & 1) << 28; cb |=3D ((psw >> 13) & 1) << 24; cb |=3D ((psw >> 12) & 1) << 20; --=20 2.34.1 From nobody Wed Nov 27 18:51:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1697666654; cv=none; d=zohomail.com; s=zohoarc; b=n23aJMjrmoyQyrnvYidWXpWnTYjn/OQs309qo5nmByxeSBm1l0Blf+PYSPIdl969YC78UM8TWHsBmlTr5Y/xwYQtLRCuS7GiYl5hYl+mPLIugLIJk9SXqGDxXwWjURiVNZCYo82M2ycAMCTpk8sY9uvtqBwfYCqbutZg/XAQ/iM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1697666654; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=0ZXU+uJQmMW+4OCGtgI6BB8XXkY8PzpFUr5ZBWJJgxY=; b=CTX3PU9uxR7ng57TmtcBtOW1w8r9YJqzdq1nrtX94y6GMZbL9RJk7Q36/65oPlKkyUlROwZWkmoD1e9raep8UtetbAh3dbZo3xbh6M2Zr5cHrH22Pn6w7mTdTzCbG4j9OudzR4mSEkIp3cBiHVR7fw7CtB8vdD6A0vqxcaL1g1E= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 169766665424437.4686151394684; Wed, 18 Oct 2023 15:04:14 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qtESd-0001fc-3L; Wed, 18 Oct 2023 17:52:15 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qtESH-00017d-LU for qemu-devel@nongnu.org; Wed, 18 Oct 2023 17:51:54 -0400 Received: from mail-oi1-x233.google.com ([2607:f8b0:4864:20::233]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qtESF-0004Py-Vu for qemu-devel@nongnu.org; Wed, 18 Oct 2023 17:51:53 -0400 Received: by mail-oi1-x233.google.com with SMTP id 5614622812f47-3b2f5aed39cso139979b6e.1 for ; Wed, 18 Oct 2023 14:51:51 -0700 (PDT) Received: from stoup.. ([71.212.149.95]) by smtp.gmail.com with ESMTPSA id w17-20020a63f511000000b005b61a024ec7sm2176380pgh.74.2023.10.18.14.51.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Oct 2023 14:51:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1697665910; x=1698270710; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=0ZXU+uJQmMW+4OCGtgI6BB8XXkY8PzpFUr5ZBWJJgxY=; b=O+JSM06lhx7BJ0dhSVsnkju510ez08BeqgOpOrFUVIGB8+J2yqgx8p9jJVSi3DYQNo VBa0TSdfTlsWvPLHKXRYfJOIQe9NEt+4u9s58KUXmFOPLlZ6I/1YeELvAgpt2kKFNYGN fioElGPMop17jiaiDYbevX9TINTnE1+4XX4dHYpYI2m70kYANKOyQV+QxxEc+RsNg7PR 2FXrEB4S6zS2U8ktVqlldKqQI2I7Kwq9OuWF3yhMOUd00AMQoljNzuXTE5VeJUN4M0iJ tURuFT2cev/0V3J8r6uWECMXc0hlBDE69zJrViiamOTe/HAU6IUWH0zN8auduKCYPvWD H5nw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697665910; x=1698270710; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=0ZXU+uJQmMW+4OCGtgI6BB8XXkY8PzpFUr5ZBWJJgxY=; b=Alo8A5eosezsrP62rqSs/TvXJtcdVmdc7tktKd5dw01PQ/7LtFW5a7BT4Rad5v9jKh mAJt+wlU1QO9yota9KzeqlfFKDsvJk7iJcb4eU5BGqsYdsVWURToUNj8/n80zZVHSuGM 8BIBZtB8uP7RclzICMjnOGJFiXwdpeawvHH0MkpDWMNgSrXKtTUFSvC1cPRoITR9G2rX OGElRtYbgFb5Vq/DNI3hngMZX3kNNeupy0Pvc+8iG9+9Uj6uL+1LOm7uFJiztJtBzezR fUwaLYUZfx+H+WxeOdM+2551Lbd09qmJbC2TaocdlIEWt8Qd50IQcw9fiKM0o+j7NhQ4 ytMA== X-Gm-Message-State: AOJu0Yza+FaH17SrJzwzK1YokXwAi1uvgt7if6CSnkHATxbBqSBWklQw 2c9K50B8/DC3elab4Pmh8n9jPqJ63TBGxXUBjUU= X-Google-Smtp-Source: AGHT+IH+XuWHDsYdvgiaPEHbruawySBZGuNSo25EvvUPfxz9+7Nms6eZy8evgWuYBrOB9BlCdsipmg== X-Received: by 2002:a05:6870:10d8:b0:1ea:2e2c:e9e7 with SMTP id 24-20020a05687010d800b001ea2e2ce9e7mr579020oar.59.1697665910592; Wed, 18 Oct 2023 14:51:50 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH 17/61] target/hppa: Handle absolute addresses for pa2.0 Date: Wed, 18 Oct 2023 14:50:51 -0700 Message-Id: <20231018215135.1561375-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231018215135.1561375-1-richard.henderson@linaro.org> References: <20231018215135.1561375-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::233; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x233.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697666655387100003 Content-Type: text/plain; charset="utf-8" With pa2.0, absolute addresses are not the same as physical addresses, and undergo a transformation based on PSW_W. Signed-off-by: Richard Henderson --- target/hppa/cpu.h | 3 +++ target/hppa/helper.c | 4 ++-- target/hppa/mem_helper.c | 47 ++++++++++++++++++++++++++++++++++++++-- target/hppa/sys_helper.c | 9 ++++++++ 4 files changed, 59 insertions(+), 4 deletions(-) diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 30010858a9..671e43ebd8 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -283,6 +283,9 @@ static inline target_ulong hppa_form_gva(CPUHPPAState *= env, uint64_t spc, return hppa_form_gva_psw(env->psw, spc, off); } =20 +hwaddr hppa_abs_to_phys_pa2_w0(vaddr addr); +hwaddr hppa_abs_to_phys_pa2_w1(vaddr addr); + /* * Since PSW_{I,CB} will never need to be in tb->flags, reuse them. * TB_FLAG_SR_SAME indicates that SR4 through SR7 all contain the diff --git a/target/hppa/helper.c b/target/hppa/helper.c index 40e859ba08..0ef890184a 100644 --- a/target/hppa/helper.c +++ b/target/hppa/helper.c @@ -109,8 +109,8 @@ void cpu_hppa_put_psw(CPUHPPAState *env, target_ureg ps= w) cb |=3D ((psw >> 8) & 1) << 4; env->psw_cb =3D cb; =20 - /* If PSW_P changes, it affects how we translate addresses. */ - if ((psw ^ old_psw) & PSW_P) { + /* If P or W changes, it affects how we translate addresses. */ + if ((psw ^ old_psw) & (PSW_P | PSW_W)) { #ifndef CONFIG_USER_ONLY tlb_flush_by_mmuidx(env_cpu(env), HPPA_MMU_FLUSH_MASK); #endif diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c index b2a75f6408..169e878479 100644 --- a/target/hppa/mem_helper.c +++ b/target/hppa/mem_helper.c @@ -25,6 +25,45 @@ #include "hw/core/cpu.h" #include "trace.h" =20 +hwaddr hppa_abs_to_phys_pa2_w1(vaddr addr) +{ + if (likely(extract64(addr, 58, 4) !=3D 0xf)) { + /* Memory address space */ + return addr & MAKE_64BIT_MASK(0, 62); + } + if (extract64(addr, 54, 4) !=3D 0) { + /* I/O address space */ + return addr | MAKE_64BIT_MASK(62, 2); + } + /* PDC address space */ + return (addr & MAKE_64BIT_MASK(0, 54)) | MAKE_64BIT_MASK(60, 4); +} + +hwaddr hppa_abs_to_phys_pa2_w0(vaddr addr) +{ + if (likely(extract32(addr, 28, 4) !=3D 0xf)) { + /* Memory address space */ + return addr & MAKE_64BIT_MASK(0, 32); + } + if (extract32(addr, 24, 4) !=3D 0) { + /* I/O address space */ + return addr | MAKE_64BIT_MASK(32, 32); + } + /* PDC address space */ + return (addr & MAKE_64BIT_MASK(0, 24)) | MAKE_64BIT_MASK(60, 4); +} + +static hwaddr hppa_abs_to_phys(CPUHPPAState *env, vaddr addr) +{ + if (!env_archcpu(env)->is_pa20) { + return addr; + } else if (env->psw & PSW_W) { + return hppa_abs_to_phys_pa2_w1(addr); + } else { + return hppa_abs_to_phys_pa2_w0(addr); + } +} + static hppa_tlb_entry *hppa_find_tlb(CPUHPPAState *env, vaddr addr) { int i; @@ -99,7 +138,7 @@ int hppa_get_physical_address(CPUHPPAState *env, vaddr a= ddr, int mmu_idx, =20 /* Virtual translation disabled. Direct map virtual to physical. */ if (mmu_idx =3D=3D MMU_PHYS_IDX) { - phys =3D addr; + phys =3D hppa_abs_to_phys(env, addr); prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; goto egress; } @@ -299,7 +338,11 @@ void HELPER(itlba)(CPUHPPAState *env, target_ulong add= r, target_ureg reg) /* Note that empty->entry_valid =3D=3D 0 already. */ empty->va_b =3D addr & TARGET_PAGE_MASK; empty->va_e =3D empty->va_b + TARGET_PAGE_SIZE - 1; - empty->pa =3D extract32(reg, 5, 20) << TARGET_PAGE_BITS; + /* + * FIXME: This is wrong, as this is a pa1.1 function. + * But for the moment translate abs address for pa2.0. + */ + empty->pa =3D hppa_abs_to_phys(env, extract32(reg, 5, 20) << TARGET_PA= GE_BITS); trace_hppa_tlb_itlba(env, empty, empty->va_b, empty->va_e, empty->pa); } =20 diff --git a/target/hppa/sys_helper.c b/target/hppa/sys_helper.c index 4bb4cf611c..f0dd5a08e7 100644 --- a/target/hppa/sys_helper.c +++ b/target/hppa/sys_helper.c @@ -71,6 +71,15 @@ target_ureg HELPER(swap_system_mask)(CPUHPPAState *env, = target_ureg nsm) * so let this go without comment. */ env->psw =3D (psw & ~PSW_SM) | (nsm & PSW_SM); + + /* + * Changes to PSW_W change the translation of absolute to physical. + * This currently (incorrectly) affects all translations. + */ + if ((psw ^ env->psw) & (PSW_P | PSW_W)) { + tlb_flush(env_cpu(env)); + } + return psw & PSW_SM; } =20 --=20 2.34.1 From nobody Wed Nov 27 18:51:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1697666349; cv=none; d=zohomail.com; s=zohoarc; b=NI+qkNsKGcSlwLAdGcl03Iop8ZlgC6rmh9gF9n3Vmt+M6bdYOcWDJMKijJwdcxJTWhpKXj4u/I3nYmYi1STBAkToeAk+pBwt9KHefyZS23dtzlcEL5u0hDAHPRJ15jU1adHEWdu3Jq5GczHd/hir+wem7bTSt7L/ZtgzM+/riSs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1697666349; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=gxoeDFewjCpExZ9mTpKevDYx6+NicYXRP6vcBDYf3yo=; b=RAXu9ZPH88O7Wx6L7LWJ84cOXAwb+uzFJlthmW2CoX9ioYZVkKpRduxa8r6kBdrJ7XcHgjuqI0dopM8LYQ8lP8sTy132v2NRW6sDjj69320Db1IHzqmXtypkKYQqNS0/Y0KGpBQL79BSO3HMMgpnOPQyIyanhHoYFdupoO5mhmc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1697666349484473.60407905595844; Wed, 18 Oct 2023 14:59:09 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qtESY-0001Rq-4J; Wed, 18 Oct 2023 17:52:10 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qtESH-00017e-Rg for qemu-devel@nongnu.org; Wed, 18 Oct 2023 17:51:54 -0400 Received: from mail-oo1-xc34.google.com ([2607:f8b0:4864:20::c34]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qtESG-0004QA-EC for qemu-devel@nongnu.org; Wed, 18 Oct 2023 17:51:53 -0400 Received: by mail-oo1-xc34.google.com with SMTP id 006d021491bc7-57f0f81b2aeso4041299eaf.3 for ; Wed, 18 Oct 2023 14:51:52 -0700 (PDT) Received: from stoup.. ([71.212.149.95]) by smtp.gmail.com with ESMTPSA id w17-20020a63f511000000b005b61a024ec7sm2176380pgh.74.2023.10.18.14.51.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Oct 2023 14:51:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1697665911; x=1698270711; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=gxoeDFewjCpExZ9mTpKevDYx6+NicYXRP6vcBDYf3yo=; b=j5Aut7FItsu6la4W/zIHqt51lWIp6FKUBwn4hOOghnw8rf/uRYah8IZUQUCt1qC5bJ sxFVeaDOgxA9RQWU7/YIFSeAhGQrkGxDKlrz8sms4VCTZIVJCKrGHWpwCiMVXyBTU/J7 kjmh8kErE4T8grLQ0zTj5pAiXtSqgXWVV7YeSRITHMjJifEHQ8WVNdD3cHHAolclgAwq tIgCIndttowTr7QfL/qclJuYLMCNuW2zm/3EBgJaCxtUb7WBHGA8wRiLZMFg/FDxrdol BVQRf6eh/bKxIec7VIOa51UkUB62FWIPCZyTsUH+PM0UkF5oM/XJOCaN8hmP9lmRkQSU p3Qg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697665911; x=1698270711; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=gxoeDFewjCpExZ9mTpKevDYx6+NicYXRP6vcBDYf3yo=; b=RTw9LGSUEA8wpDwM+e1tZnIwcgxI4zuPYQKvAACMKyffvyNzCExZoLR5B7IY+pqb3/ Pswbmzhx7gcacQ6PGTkMFnpjyk1dI/SrabaHCL7RNlTvQ5nN1tkbW3XLe2AiEAMdUuwc v8W7nlHaFBX7aEpmA1wxaDx/l1WUkl1g7VVqWryVV4b3WuUCNI5K5AANfTsV2qh+1wZH ROv+XQC40NmoTJwxyPvghZ3Y512y9OJlcr3dANtmsaTGhPR1/FzVdzYZxAFXoOGoLcGy o+a5O/bVhgci1vK/dnYCV/c73Th95Zoq7i+N7Yd0SJZU4s0JWVhK1pgRX30UtwULyQ1o bFqw== X-Gm-Message-State: AOJu0YygV1/3NAMfi1x3u1BWTx2WHwgVligWNdEmEEPm6YwcT3j0Iqqt 7JQYW9k9WCsRkLjb2Q+oIBJGx9z9Wru2E/guFYM= X-Google-Smtp-Source: AGHT+IFSLl9+NCYVs6zKOsfGHV7vXziqgt+/AW89G0ZSG5VLnixcA07AEvC6GDVwSKZHdYV50Wd4nQ== X-Received: by 2002:a05:6358:c62a:b0:166:a6e3:cb9c with SMTP id fd42-20020a056358c62a00b00166a6e3cb9cmr296039rwb.5.1697665911306; Wed, 18 Oct 2023 14:51:51 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH 18/61] target/hppa: Adjust hppa_cpu_dump_state for hppa64 Date: Wed, 18 Oct 2023 14:50:52 -0700 Message-Id: <20231018215135.1561375-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231018215135.1561375-1-richard.henderson@linaro.org> References: <20231018215135.1561375-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::c34; envelope-from=richard.henderson@linaro.org; helo=mail-oo1-xc34.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697666350083100005 Content-Type: text/plain; charset="utf-8" Dump all 64 bits for pa2.0 and low 32 bits for pa1.x. Signed-off-by: Richard Henderson --- target/hppa/helper.c | 20 +++++++++++++------- 1 file changed, 13 insertions(+), 7 deletions(-) diff --git a/target/hppa/helper.c b/target/hppa/helper.c index 0ef890184a..04cdbafe9d 100644 --- a/target/hppa/helper.c +++ b/target/hppa/helper.c @@ -124,13 +124,17 @@ void hppa_cpu_dump_state(CPUState *cs, FILE *f, int f= lags) target_ureg psw =3D cpu_hppa_get_psw(env); target_ureg psw_cb; char psw_c[20]; - int i; + int i, w; + uint64_t m; + + w =3D cpu->is_pa20 ? 16 : 8; + m =3D cpu->is_pa20 ? UINT64_MAX : UINT32_MAX; =20 qemu_fprintf(f, "IA_F " TARGET_FMT_lx " IA_B " TARGET_FMT_lx - " IIR " TREG_FMT_lx "\n", + " IIR %0*" PRIx64 "\n", hppa_form_gva_psw(psw, env->iasq_f, env->iaoq_f), hppa_form_gva_psw(psw, env->iasq_b, env->iaoq_b), - env->cr[CR_IIR]); + w, m & env->cr[CR_IIR]); =20 psw_c[0] =3D (psw & PSW_W ? 'W' : '-'); psw_c[1] =3D (psw & PSW_E ? 'E' : '-'); @@ -151,13 +155,15 @@ void hppa_cpu_dump_state(CPUState *cs, FILE *f, int f= lags) psw_c[16] =3D (psw & PSW_D ? 'D' : '-'); psw_c[17] =3D (psw & PSW_I ? 'I' : '-'); psw_c[18] =3D '\0'; - psw_cb =3D ((env->psw_cb >> 4) & 0x01111111) | (env->psw_cb_msb << 28); + psw_cb =3D ((env->psw_cb >> 4) & ((target_ureg)-1 / 0xf)) + | (env->psw_cb_msb << (TARGET_REGISTER_BITS - 4)); =20 - qemu_fprintf(f, "PSW " TREG_FMT_lx " CB " TREG_FMT_lx " %s\n", - psw, psw_cb, psw_c); + qemu_fprintf(f, "PSW %0*" PRIx64 " CB %0*" PRIx64 " %s\n", + w, m & psw, w, m & psw_cb, psw_c); =20 for (i =3D 0; i < 32; i++) { - qemu_fprintf(f, "GR%02d " TREG_FMT_lx "%c", i, env->gr[i], + qemu_fprintf(f, "GR%02d %0*" PRIx64 "%c", + i, w, m & env->gr[i], (i & 3) =3D=3D 3 ? '\n' : ' '); } #ifndef CONFIG_USER_ONLY --=20 2.34.1 From nobody Wed Nov 27 18:51:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1697666308; cv=none; d=zohomail.com; s=zohoarc; b=PRkVtZWYb5ug/vreh3LtYiC3gB1RafvxMGcE6MvS64wWnuaZGOtqfVGStL2qLorGJxn6eBrHhkDUB7izecR2Uo2QHgwqvaJR6+n5ee/TIS43eYxg8OLrMobNXmSRHbPoZr6ShUYPimwSAnqyRtuj89RKfdrXZ0ag+Le9ZO0fOss= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1697666308; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=KZ59Wqyg2YQUe4NJ15oFoXlcwSLtPJhdE2Dc4QmCfGA=; b=WcYgA3EBu08RA/fIhGoeF4qLhZsazTVnIjp9q/gcT1rDgNxrSDczaormsmsvWei2j4GU7AC68oOhqf4pidtaW3gb7VuBPmS1IHCqAYRqKkW5BO9uQbCir0goC3GUyzcwOMIih0JjDJreW5C+EVfpC/wxEHXQRTZCbY0znP1klyY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1697666308832952.0422577737681; Wed, 18 Oct 2023 14:58:28 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qtESe-0001jC-0c; Wed, 18 Oct 2023 17:52:16 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qtESK-00018l-5z for qemu-devel@nongnu.org; Wed, 18 Oct 2023 17:51:57 -0400 Received: from mail-pf1-x42f.google.com ([2607:f8b0:4864:20::42f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qtESI-0004QT-1w for qemu-devel@nongnu.org; Wed, 18 Oct 2023 17:51:55 -0400 Received: by mail-pf1-x42f.google.com with SMTP id d2e1a72fcca58-68fb85afef4so6054511b3a.1 for ; Wed, 18 Oct 2023 14:51:53 -0700 (PDT) Received: from stoup.. ([71.212.149.95]) by smtp.gmail.com with ESMTPSA id w17-20020a63f511000000b005b61a024ec7sm2176380pgh.74.2023.10.18.14.51.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Oct 2023 14:51:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1697665912; x=1698270712; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=KZ59Wqyg2YQUe4NJ15oFoXlcwSLtPJhdE2Dc4QmCfGA=; b=lbLJPekVhsqw9nquZCAM5lJnt5aZjDn3MSwC3xBFQsKqWGUwAupxrjhciasQqsEYPW CdB15csPcTYHwoYnUDMSM8iMRLNvzBfbg/xxNDxB1VAl7KyTnU2ut8iInnlhvY31n7Y5 W3fJB2h5zZbv6A10YfxeCGbJRRrltrrRGiL0mvadRlAYmwOihTjXOn+Wpm+tGviwb11F YVB94eQIARzYknGlEdcRYSZ3X/oaHjDqNDsThI07sONJYSkOpDBHSv4tN5tTeqtpL7SP y+JWPiy4ilbWy+7EjqSQUgeOfjyQz+mVQGgjvWZUeYDOO+WPJXwyy9lAHp8ui+Z/x+4H 1BuQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697665912; x=1698270712; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=KZ59Wqyg2YQUe4NJ15oFoXlcwSLtPJhdE2Dc4QmCfGA=; b=GOI5vgsG/eIaTO9YAR2d+0GrSWQni0uNn8RKJk5leZlssnguElnQwmQ8ahnKtmwkig ioFufyRsJqPdWFdWfEWIiZwYHsj0nZrRcXD3fJClsba5331UcNH/8xw7yt7coByIxwl1 BfYBQThzcq4NrYJMH3eOCL5QagH14bBNVLAs6ODDV8aP3CWLUuODKvE1QfxwgCgZD9N0 2x+ekbJK/5BMe4Aqm/HEA/1NaACM7kOeh3dTMA+3bPyXJ6yqOJR1HutnYmeILSiCSxRS zgQf5d9SmKSKSGzQHtNyLhY9WvmPIMwxp2Do47kpPDHYIFZCBcVkyIpCXFGUUT4kogSP GD6g== X-Gm-Message-State: AOJu0YyH4J60dquhHZhRBFio1GNriXCb12xiMltRW/6mRu16/LZTcg1U /daxUrS5OetGhGbKhiyG209P+lHgI7fGBq79U1U= X-Google-Smtp-Source: AGHT+IF2l2C0el29QLejV3GqPiqHM9QsOCkLQ3jn+eiKahehydo+rXlgd+X+N7jx2KKGtKu5NnOAHA== X-Received: by 2002:a05:6a21:7985:b0:171:c88a:891e with SMTP id bh5-20020a056a21798500b00171c88a891emr397623pzc.55.1697665912230; Wed, 18 Oct 2023 14:51:52 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH 19/61] hw/hppa: Translate phys addresses for the cpu Date: Wed, 18 Oct 2023 14:50:53 -0700 Message-Id: <20231018215135.1561375-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231018215135.1561375-1-richard.henderson@linaro.org> References: <20231018215135.1561375-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42f; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697666309457100001 Content-Type: text/plain; charset="utf-8" Hack the machine to use pa2.0 physical layout when required, using the PSW.W=3D0 absolute to physical mapping. Signed-off-by: Richard Henderson --- hw/hppa/machine.c | 87 ++++++++++++++++++++++++++++------------------- 1 file changed, 52 insertions(+), 35 deletions(-) diff --git a/hw/hppa/machine.c b/hw/hppa/machine.c index 07f8ebeb6a..765f338544 100644 --- a/hw/hppa/machine.c +++ b/hw/hppa/machine.c @@ -81,7 +81,7 @@ static const MemoryRegionOps hppa_pci_ignore_ops =3D { }, }; =20 -static ISABus *hppa_isa_bus(void) +static ISABus *hppa_isa_bus(hwaddr addr) { ISABus *isa_bus; qemu_irq *isa_irqs; @@ -90,8 +90,7 @@ static ISABus *hppa_isa_bus(void) isa_region =3D g_new(MemoryRegion, 1); memory_region_init_io(isa_region, NULL, &hppa_pci_ignore_ops, NULL, "isa-io", 0x800); - memory_region_add_subregion(get_system_memory(), IDE_HPA, - isa_region); + memory_region_add_subregion(get_system_memory(), addr, isa_region); =20 isa_bus =3D isa_bus_new(NULL, get_system_memory(), isa_region, &error_abort); @@ -103,7 +102,7 @@ static ISABus *hppa_isa_bus(void) return isa_bus; } =20 -static uint64_t cpu_hppa_to_phys(void *opaque, uint64_t addr) +static uint64_t linux_kernel_virt_to_phys(void *opaque, uint64_t addr) { addr &=3D (0x10000000 - 1); return addr; @@ -118,13 +117,13 @@ static void fw_cfg_boot_set(void *opaque, const char = *boot_device, fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]); } =20 -static FWCfgState *create_fw_cfg(MachineState *ms) +static FWCfgState *create_fw_cfg(MachineState *ms, hwaddr addr) { FWCfgState *fw_cfg; uint64_t val; const char qemu_version[] =3D QEMU_VERSION; =20 - fw_cfg =3D fw_cfg_init_mem(FW_CFG_IO_BASE, FW_CFG_IO_BASE + 4); + fw_cfg =3D fw_cfg_init_mem(addr, addr + 4); fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, ms->smp.cpus); fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, HPPA_MAX_CPUS); fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, ms->ram_size); @@ -173,6 +172,16 @@ static DinoState *dino_init(MemoryRegion *addr_space) return DINO_PCI_HOST_BRIDGE(dev); } =20 +static uint64_t translate_pa10(void *dummy, uint64_t addr) +{ + return (uint32_t)addr; +} + +static uint64_t translate_pa20(void *dummy, uint64_t addr) +{ + return hppa_abs_to_phys_pa2_w0(addr); +} + static void machine_hppa_init(MachineState *machine) { const char *kernel_filename =3D machine->kernel_filename; @@ -188,20 +197,33 @@ static void machine_hppa_init(MachineState *machine) uint64_t kernel_entry =3D 0, kernel_low, kernel_high; MemoryRegion *addr_space =3D get_system_memory(); MemoryRegion *rom_region; - MemoryRegion *cpu_region; long i; unsigned int smp_cpus =3D machine->smp.cpus; SysBusDevice *s; + uint64_t (*translate)(void *, uint64_t); =20 /* Create CPUs. */ for (i =3D 0; i < smp_cpus; i++) { - char *name =3D g_strdup_printf("cpu%ld-io-eir", i); cpu[i] =3D HPPA_CPU(cpu_create(machine->cpu_type)); + } =20 - cpu_region =3D g_new(MemoryRegion, 1); + /* + * For now, treat address layout as if PSW_W is clear. + * TODO: create a proper hppa64 board model and load elf64 firmware. + */ + if (cpu[0]->is_pa20) { + translate =3D translate_pa20; + } else { + translate =3D translate_pa10; + } + + for (i =3D 0; i < smp_cpus; i++) { + char *name =3D g_strdup_printf("cpu%ld-io-eir", i); + MemoryRegion *cpu_region =3D g_new(MemoryRegion, 1); memory_region_init_io(cpu_region, OBJECT(cpu[i]), &hppa_io_eir_ops, cpu[i], name, 4); - memory_region_add_subregion(addr_space, CPU_HPA + i * 0x1000, + memory_region_add_subregion(addr_space, + translate(NULL, CPU_HPA + i * 0x1000), cpu_region); g_free(name); } @@ -216,41 +238,41 @@ static void machine_hppa_init(MachineState *machine) =20 /* Init Lasi chip */ lasi_dev =3D DEVICE(lasi_init()); - memory_region_add_subregion(addr_space, LASI_HPA, + memory_region_add_subregion(addr_space, translate(NULL, LASI_HPA), sysbus_mmio_get_region( SYS_BUS_DEVICE(lasi_dev), 0)); =20 /* Init Dino (PCI host bus chip). */ dino_dev =3D DEVICE(dino_init(addr_space)); - memory_region_add_subregion(addr_space, DINO_HPA, + memory_region_add_subregion(addr_space, translate(NULL, DINO_HPA), sysbus_mmio_get_region( SYS_BUS_DEVICE(dino_dev), 0)); pci_bus =3D PCI_BUS(qdev_get_child_bus(dino_dev, "pci")); assert(pci_bus); =20 /* Create ISA bus. */ - isa_bus =3D hppa_isa_bus(); + isa_bus =3D hppa_isa_bus(translate(NULL, IDE_HPA)); assert(isa_bus); =20 /* Realtime clock, used by firmware for PDC_TOD call. */ mc146818_rtc_init(isa_bus, 2000, NULL); =20 /* Serial ports: Lasi and Dino use a 7.272727 MHz clock. */ - serial_mm_init(addr_space, LASI_UART_HPA + 0x800, 0, + serial_mm_init(addr_space, translate(NULL, LASI_UART_HPA + 0x800), 0, qdev_get_gpio_in(lasi_dev, LASI_IRQ_UART_HPA), 7272727 / 16, serial_hd(0), DEVICE_BIG_ENDIAN); =20 - serial_mm_init(addr_space, DINO_UART_HPA + 0x800, 0, + serial_mm_init(addr_space, translate(NULL, DINO_UART_HPA + 0x800), 0, qdev_get_gpio_in(dino_dev, DINO_IRQ_RS232INT), 7272727 / 16, serial_hd(1), DEVICE_BIG_ENDIAN); =20 /* Parallel port */ - parallel_mm_init(addr_space, LASI_LPT_HPA + 0x800, 0, + parallel_mm_init(addr_space, translate(NULL, LASI_LPT_HPA + 0x800), 0, qdev_get_gpio_in(lasi_dev, LASI_IRQ_LAN_HPA), parallel_hds[0]); =20 /* fw_cfg configuration interface */ - create_fw_cfg(machine); + create_fw_cfg(machine, translate(NULL, FW_CFG_IO_BASE)); =20 /* SCSI disk setup. */ dev =3D DEVICE(pci_create_simple(pci_bus, -1, "lsi53c895a")); @@ -262,13 +284,13 @@ static void machine_hppa_init(MachineState *machine) dev =3D qdev_new("artist"); s =3D SYS_BUS_DEVICE(dev); sysbus_realize_and_unref(s, &error_fatal); - sysbus_mmio_map(s, 0, LASI_GFX_HPA); - sysbus_mmio_map(s, 1, ARTIST_FB_ADDR); + sysbus_mmio_map(s, 0, translate(NULL, LASI_GFX_HPA)); + sysbus_mmio_map(s, 1, translate(NULL, ARTIST_FB_ADDR)); } =20 /* Network setup. */ if (enable_lasi_lan()) { - lasi_82596_init(addr_space, LASI_LAN_HPA, + lasi_82596_init(addr_space, translate(NULL, LASI_LAN_HPA), qdev_get_gpio_in(lasi_dev, LASI_IRQ_LAN_HPA)); } =20 @@ -283,10 +305,11 @@ static void machine_hppa_init(MachineState *machine) sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, qdev_get_gpio_in(lasi_dev, LASI_IRQ_PS2KBD_HPA)); - memory_region_add_subregion(addr_space, LASI_PS2KBD_HPA, + memory_region_add_subregion(addr_space, translate(NULL, LASI_PS2KBD_HP= A), sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0)); - memory_region_add_subregion(addr_space, LASI_PS2KBD_HPA + 0x100, + memory_region_add_subregion(addr_space, + translate(NULL, LASI_PS2KBD_HPA + 0x100), sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1)); =20 @@ -303,15 +326,10 @@ static void machine_hppa_init(MachineState *machine) exit(1); } =20 - size =3D load_elf(firmware_filename, NULL, NULL, NULL, + size =3D load_elf(firmware_filename, NULL, translate, NULL, &firmware_entry, &firmware_low, &firmware_high, NULL, true, EM_PARISC, 0, 0); =20 - /* Unfortunately, load_elf sign-extends reading elf32. */ - firmware_entry =3D (target_ureg)firmware_entry; - firmware_low =3D (target_ureg)firmware_low; - firmware_high =3D (target_ureg)firmware_high; - if (size < 0) { error_report("could not load firmware '%s'", firmware_filename); exit(1); @@ -319,7 +337,8 @@ static void machine_hppa_init(MachineState *machine) qemu_log_mask(CPU_LOG_PAGE, "Firmware loaded at 0x%08" PRIx64 "-0x%08" PRIx64 ", entry at 0x%08" PRIx64 ".\n", firmware_low, firmware_high, firmware_entry); - if (firmware_low < FIRMWARE_START || firmware_high >=3D FIRMWARE_END) { + if (firmware_low < translate(NULL, FIRMWARE_START) || + firmware_high >=3D translate(NULL, FIRMWARE_END)) { error_report("Firmware overlaps with memory or IO space"); exit(1); } @@ -328,18 +347,16 @@ static void machine_hppa_init(MachineState *machine) rom_region =3D g_new(MemoryRegion, 1); memory_region_init_ram(rom_region, NULL, "firmware", (FIRMWARE_END - FIRMWARE_START), &error_fatal); - memory_region_add_subregion(addr_space, FIRMWARE_START, rom_region); + memory_region_add_subregion(addr_space, + translate(NULL, FIRMWARE_START), rom_regio= n); =20 /* Load kernel */ if (kernel_filename) { - size =3D load_elf(kernel_filename, NULL, &cpu_hppa_to_phys, + size =3D load_elf(kernel_filename, NULL, linux_kernel_virt_to_phys, NULL, &kernel_entry, &kernel_low, &kernel_high, NU= LL, true, EM_PARISC, 0, 0); =20 - /* Unfortunately, load_elf sign-extends reading elf32. */ - kernel_entry =3D (target_ureg) cpu_hppa_to_phys(NULL, kernel_entry= ); - kernel_low =3D (target_ureg)kernel_low; - kernel_high =3D (target_ureg)kernel_high; + kernel_entry =3D linux_kernel_virt_to_phys(NULL, kernel_entry); =20 if (size < 0) { error_report("could not load kernel '%s'", kernel_filename); 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id w17-20020a63f511000000b005b61a024ec7sm2176380pgh.74.2023.10.18.14.51.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Oct 2023 14:51:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1697665913; x=1698270713; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=G9nUcdEt7w+NCkvnMW2YnG2igY5bd41b5qtUzVj7Mew=; b=GguMiPaldiSe/RdlR54LmFbmFXs6tyish59fcM3bwQlNmfkDSPnAEBePKfgV2ttwgJ msimo1/SNkxS1PVZ8AsLmT/2EfvhhqAI0b1wOEpTHvugQwK1sT1IppCv8XR3GYKTcOWQ 66yJpB0HMcDME9YF2rrbTQ4+iqLhQSfOoxjsFySfeFPqkVjhyB/HElM1Jr5FbHcXf8Cj WO3p88QfE6mFXihEMrWn5dbZyPUHxljSx2xvryFcgUrfPfFyrDRcIqrYiOGO3BwonCQX 5HKPaGvAnboxL1df7d3wYAuGPj8QkEF7rcnbl1QdfA8K3kidPx0Uddp4BLwf06e1VP5C eEhQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697665913; x=1698270713; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=G9nUcdEt7w+NCkvnMW2YnG2igY5bd41b5qtUzVj7Mew=; b=ZN491XaWMaTNoorIkxrC1L7oPUOtht3Ooi9+jECXe6mKtyGNu8a6CBuKK/uqKe8hxR ozxzI2sHt/JbcArEPXv+uKQWIG0KbgQgSpmwuyvQBgOBFjM9EzwzSOBuWQgs/Z09pwNC jHkafhgCrtKAnccJ2J7oMfUxuzQMwKU35qPkMzq2Npn9g/vYD2sIASuoSZHpyHWQjGvy nTVrAfCKeyzqBPvRzax35xMzEuxf+FRiHc5nI8OWJtQdh2m2UMUoVwDCh4mz49YQk1RN o7ZF5qYkQL6aj7jG7ddXlYEVcdHyM/DAFW1hzl7cUuNRHQzi9p2EOUXBGsPNPruwgIPr rfKg== X-Gm-Message-State: AOJu0Yw83egH2qASlM+kZYVmgKEKYxyq4Q7qHFtpN4jTZRkGAe3SHRrw wBAtzM6KzuKlVR6rrz+5dH/ujDeFBsBnRVTAwD4= X-Google-Smtp-Source: AGHT+IHdEDRoynh+oJMM40mbGuB/x7sP9Wu0L52H9F8wUXlw+/ZoKJosPfc2aC9Um3GipnJTF+Q0tA== X-Received: by 2002:a05:6870:98a7:b0:1e9:d8a4:5523 with SMTP id eg39-20020a05687098a700b001e9d8a45523mr543486oab.41.1697665913171; Wed, 18 Oct 2023 14:51:53 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH 20/61] target/hppa: Fix hppa64 addressing Date: Wed, 18 Oct 2023 14:50:54 -0700 Message-Id: <20231018215135.1561375-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231018215135.1561375-1-richard.henderson@linaro.org> References: <20231018215135.1561375-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:4860:4864:20::30; envelope-from=richard.henderson@linaro.org; helo=mail-oa1-x30.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697666322329100002 Content-Type: text/plain; charset="utf-8" In form_gva and cpu_get_tb_cpu_state, we must truncate when PSW_W =3D=3D 0. In space_select, the bits that choose the space depend on PSW_W. Signed-off-by: Richard Henderson --- target/hppa/cpu.h | 7 +++---- target/hppa/translate.c | 22 +++++++++++++--------- 2 files changed, 16 insertions(+), 13 deletions(-) diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 671e43ebd8..1a12b2a186 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -272,7 +272,7 @@ static inline target_ulong hppa_form_gva_psw(target_ure= g psw, uint64_t spc, #ifdef CONFIG_USER_ONLY return off; #else - off &=3D (psw & PSW_W ? 0x3fffffffffffffffull : 0xffffffffull); + off &=3D psw & PSW_W ? MAKE_64BIT_MASK(0, 62) : MAKE_64BIT_MASK(0, 32); return spc | off; #endif } @@ -313,9 +313,8 @@ static inline void cpu_get_tb_cpu_state(CPUHPPAState *e= nv, vaddr *pc, flags |=3D env->psw & (PSW_W | PSW_C | PSW_D); flags |=3D (env->iaoq_f & 3) << TB_FLAG_PRIV_SHIFT; =20 - *pc =3D (env->psw & PSW_C - ? hppa_form_gva_psw(env->psw, env->iasq_f, env->iaoq_f & -4) - : env->iaoq_f & -4); + *pc =3D hppa_form_gva_psw(env->psw, (env->psw & PSW_C ? env->iasq_f : = 0), + env->iaoq_f & -4); *cs_base =3D env->iasq_f; =20 /* Insert a difference between IAOQ_B and IAOQ_F within the otherwise = zero diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 9d6670f91c..ace6fb0ab2 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -764,6 +764,13 @@ static bool gen_illegal(DisasContext *ctx) } while (0) #endif =20 +static target_ureg gva_offset_mask(DisasContext *ctx) +{ + return (ctx->tb_flags & PSW_W + ? MAKE_64BIT_MASK(0, 62) + : MAKE_64BIT_MASK(0, 32)); +} + static bool use_goto_tb(DisasContext *ctx, target_ureg dest) { return translator_use_goto_tb(&ctx->base, dest); @@ -1398,7 +1405,8 @@ static TCGv_i64 space_select(DisasContext *ctx, int s= p, TCGv_reg base) tmp =3D tcg_temp_new(); spc =3D tcg_temp_new_tl(); =20 - tcg_gen_shri_reg(tmp, base, TARGET_REGISTER_BITS - 5); + /* Extract top 2 bits of the address, shift left 3 for uint64_t index.= */ + tcg_gen_shri_reg(tmp, base, (ctx->tb_flags & PSW_W ? 64 : 32) - 5); tcg_gen_andi_reg(tmp, tmp, 030); tcg_gen_trunc_reg_ptr(ptr, tmp); =20 @@ -1415,6 +1423,7 @@ static void form_gva(DisasContext *ctx, TCGv_tl *pgva= , TCGv_reg *pofs, { TCGv_reg base =3D load_gpr(ctx, rb); TCGv_reg ofs; + TCGv_tl addr; =20 /* Note that RX is mutually exclusive with DISP. */ if (rx) { @@ -1429,18 +1438,13 @@ static void form_gva(DisasContext *ctx, TCGv_tl *pg= va, TCGv_reg *pofs, } =20 *pofs =3D ofs; -#ifdef CONFIG_USER_ONLY - *pgva =3D (modify <=3D 0 ? ofs : base); -#else - TCGv_tl addr =3D tcg_temp_new_tl(); + *pgva =3D addr =3D tcg_temp_new_tl(); tcg_gen_extu_reg_tl(addr, modify <=3D 0 ? ofs : base); - if (ctx->tb_flags & PSW_W) { - tcg_gen_andi_tl(addr, addr, 0x3fffffffffffffffull); - } + tcg_gen_andi_tl(addr, addr, gva_offset_mask(ctx)); +#ifndef CONFIG_USER_ONLY if (!is_phys) { tcg_gen_or_tl(addr, addr, space_select(ctx, sp, base)); } - *pgva =3D addr; #endif } =20 --=20 2.34.1 From nobody Wed Nov 27 18:51:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1697666463; cv=none; d=zohomail.com; s=zohoarc; b=epcTbr5/myzw7IIc+c2MdM76wUDWVyHxlXcap0P+eglwVstRTuk6CihMgwLmla4f3zrclX9AkH4u1M8pHD4e+7wgA+ZEehA+R2WyyxygnigDaiNeaUE0de/94k3VVvsRr5BTXMYVGTESOrf0LdGxUiM8oPxcIi7XsQBKEfkBJ6k= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1697666463; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=WGDc36lTRQBdhZQkVmDvdtL0QhZmZu6PdPoUP7sd7r8=; b=kKMkzogldJo/vNTSAk5t0mwEaxVdK8dUnF0CxmgUxnJNFESnM45HNaRzSLOAIqkuNYG9uRrZRDxw64j4QXfuwLxUoOSDLthRlRJQ2YO6XE0b+2WYTlHdWPngv2tzJke1bjvJWx6OxvOx1G35qNinidVoCylIUJrYLos0RMDWlXA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1697666463203763.4035059579932; Wed, 18 Oct 2023 15:01:03 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qtESm-0001z7-FL; Wed, 18 Oct 2023 17:52:24 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qtESL-00018s-8U for qemu-devel@nongnu.org; Wed, 18 Oct 2023 17:51:59 -0400 Received: from mail-pf1-x430.google.com ([2607:f8b0:4864:20::430]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qtESJ-0004Qw-Gp for qemu-devel@nongnu.org; Wed, 18 Oct 2023 17:51:57 -0400 Received: by mail-pf1-x430.google.com with SMTP id d2e1a72fcca58-6b7f0170d7bso4677528b3a.2 for ; Wed, 18 Oct 2023 14:51:55 -0700 (PDT) Received: from stoup.. ([71.212.149.95]) by smtp.gmail.com with ESMTPSA id w17-20020a63f511000000b005b61a024ec7sm2176380pgh.74.2023.10.18.14.51.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Oct 2023 14:51:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1697665914; x=1698270714; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=WGDc36lTRQBdhZQkVmDvdtL0QhZmZu6PdPoUP7sd7r8=; b=JyXQtQsOMxFSd5Mxfs9hY4yueiVg6NpOyncv513blOTqoKCy0/MMxkC9T5jzf63iSv fjaj7PyrkBIuYKB/rxViAZfN1T931RdYVc7+hzJ6goPalEiZyiErWXLuAHKJWEHnLoC1 R69fwuezVcD5eDiT/KUxnfy8/ejpkzozyLZrg85xZDsYThjlQdNd786j0OPSI3PRzYG+ NRL9nhjL8vex9cKIMA7CxSFH8vaSIPM4TRMxT1laGtVbf5pLl+9yWKNeQJieTQaSz/sf yPNqThE7FL1Dd3xruX/XDWW/bk6+ifwEIcyyQIbLcZSf1u5pKVZbWcOZslGRGybt5ynH SaDg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697665914; x=1698270714; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=WGDc36lTRQBdhZQkVmDvdtL0QhZmZu6PdPoUP7sd7r8=; b=s116RtT1sM+l4/LKIDAT6a8+LL3Fw9a72fEPmi933hM/W0EsreSGgUM+q5C7rX+gkB qJSzRI0OiyzDO/iicHEDuRzVfIy6N30ykmDmfxpUZj/53eWqMpr+6L4KJMOTs3Y9ncUg 6gTjouNbVp6nMHeNUx5AXXj7cHZRodeKN36tZ1oYBA8CAfTVInrMkyekkkjNCoohpYlK I2DCDKfobPvSx02P9ymTVkCW5bPnaEnrvv5wn479VGYVuyTCR89qKmTQfhpKfuHQjosk rdF8Yupli3dtZu5YvjT9uir3HT9Sjapc8LPho4wYS2kKKbjcOdMJvtqL3aWiO4SPvK1m YZbw== X-Gm-Message-State: AOJu0YyJBUwXuC6NuLz5BJgFhW91Q0daeVm1vIR+m22MSwx1YHDl/zUr DLwZ6aDklqjac18g7OoVgRWNI0wJbmy+qrhaOBI= X-Google-Smtp-Source: AGHT+IGY1/0H/YhgR4r3ZRahYmGlmzSo6MjIN0To9YHigpUkvDMMhtdMZKlh44KxRBVq3+N3DKqihg== X-Received: by 2002:a05:6a20:6a1f:b0:162:ee29:d3c0 with SMTP id p31-20020a056a206a1f00b00162ee29d3c0mr393529pzk.42.1697665914139; Wed, 18 Oct 2023 14:51:54 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH 21/61] target/hppa: sar register allows only 5 bits on 32-bit CPU Date: Wed, 18 Oct 2023 14:50:55 -0700 Message-Id: <20231018215135.1561375-22-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231018215135.1561375-1-richard.henderson@linaro.org> References: <20231018215135.1561375-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::430; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697666464622100001 Content-Type: text/plain; charset="utf-8" From: Helge Deller The sar shift amount register is limited to 5 bits when running a 32-bit CPU. Strip off the remaining bits. The interesting part is, that this register allows to detect at runtime if a physical CPU is capable to execute PA2.0 (64-bit) instructions. Signed-off-by: Helge Deller --- target/hppa/translate.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index ace6fb0ab2..e2b692a6c5 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -2155,7 +2155,7 @@ static bool trans_mtctl(DisasContext *ctx, arg_mtctl = *a) if (ctl =3D=3D CR_SAR) { reg =3D load_gpr(ctx, a->r); tmp =3D tcg_temp_new(); - tcg_gen_andi_reg(tmp, reg, TARGET_REGISTER_BITS - 1); + tcg_gen_andi_reg(tmp, reg, ctx->is_pa20 ? 63 : 31); save_or_nullify(ctx, cpu_sar, tmp); =20 cond_free(&ctx->null_cond); @@ -2216,7 +2216,7 @@ static bool trans_mtsarcm(DisasContext *ctx, arg_mtsa= rcm *a) TCGv_reg tmp =3D tcg_temp_new(); =20 tcg_gen_not_reg(tmp, load_gpr(ctx, a->r)); - tcg_gen_andi_reg(tmp, tmp, TARGET_REGISTER_BITS - 1); + tcg_gen_andi_reg(tmp, tmp, ctx->is_pa20 ? 63 : 31); save_or_nullify(ctx, cpu_sar, tmp); =20 cond_free(&ctx->null_cond); --=20 2.34.1 From nobody Wed Nov 27 18:51:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1697666088; cv=none; d=zohomail.com; s=zohoarc; b=dlKB8qdO7fljR6mSHHFGui2J7G1KhglohUA2nAITUwODvMjd9pDZvw9Q0tbq//qRnyTnINveZvuOE6Q9H0sRqVXrJ0g/um14kn1rBangefu8SMbkRTv2kO0CU4J8psVjYrDbgAjTbBzkey0+l7IecdFmqq7GAqGUn1Pey49qdak= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1697666088; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=io7/0k/pOO+TKp7Ec9Fj4OHEiClXaVK9yG3Lda49zh8=; b=fD1Ejlk8GMxMleOmd9ArPfLvpj42iyt0aI2f1N/ChtPtzEa6utG22nGq6AFK/jLhG24mNQzBxKawR+x6+REvWIxKopncyHAXSlBnSX/rEwUgJORuOKDTEwJAC2+kqMkQXnfB/VkjsCvkFjS9TTorUdEQuMy+UtCvbY9nEU77+V0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1697666088157284.85964470327747; Wed, 18 Oct 2023 14:54:48 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qtESi-0001n2-33; Wed, 18 Oct 2023 17:52:20 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qtESM-00018y-4E for qemu-devel@nongnu.org; Wed, 18 Oct 2023 17:51:59 -0400 Received: from mail-oa1-x2a.google.com ([2001:4860:4864:20::2a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qtESK-0004R2-4M for qemu-devel@nongnu.org; Wed, 18 Oct 2023 17:51:57 -0400 Received: by mail-oa1-x2a.google.com with SMTP id 586e51a60fabf-1e9c9d181d6so3933298fac.0 for ; Wed, 18 Oct 2023 14:51:55 -0700 (PDT) Received: from stoup.. ([71.212.149.95]) by smtp.gmail.com with ESMTPSA id w17-20020a63f511000000b005b61a024ec7sm2176380pgh.74.2023.10.18.14.51.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Oct 2023 14:51:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1697665915; x=1698270715; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=io7/0k/pOO+TKp7Ec9Fj4OHEiClXaVK9yG3Lda49zh8=; b=Zr2PzKBNK44CINttQlE5jN5RD74XF9JTJpe55i1/Af8yuM90jY570FLWFN2VOiH/wi CR/L0LyGcB7vposOfVTWh+c9lC3CIEha8ggO0t0ED20kBznrbk6RER4bWH4YqT73x4zS JAtoEu9zUGDZStxUDuaLi4MQA4bXrjLi6rSf38/XJ/Sfuo1MnK2w5PsbQeXbfk95MErR K+TfKnTqEVTjKd6cpGjHaA7xrgiKvfofoGZ3kIzFcafu0AD6srknCu5zjiYcPkkmsjNe e5lS1Jdl1/+vgppJSy4y9dj06JjUlV7ATONOjnCcdewHbLZaCqRU4n8BbrfwWvCnh2u5 2YTA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697665915; x=1698270715; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=io7/0k/pOO+TKp7Ec9Fj4OHEiClXaVK9yG3Lda49zh8=; b=uYo4up3ApLrtJwE6u9WqHqEp/XCGnUjPBdtmZWtCUIR8n3/oj1YISpMw/IO+HbHr6d 7lsTHJTYZig+m/gRzRC8oPNJJx/W7oGrzP74CeFzWcgBpUVJrODHAA2OtVh8Gk6pt16D jl2ombI3uDi5wa1wnuUyLJI1zhMBZc7ouCBSkX7/JDdMSu/6S3y0T+HhltAWLK6qFFDg xFygFuVtzdK6TMl+HXBvGX1XW6JV20gLFAMcDgOKF599D7ZLsnBXRPc+/r5KlYgukoo2 MI75AMn6A6NSzNbS2kZIl3CGKjn4bDTdcSwTXIPxUvBa7IBhws5rs3iiAdoXYeZZIAGA LogA== X-Gm-Message-State: AOJu0YwnCYhDX+F/2oN2HoY2PHmtgZWhVDxMaWljmITy1lye1CUz5hlz 05bK/5DNA17KXO3AM7jy8X6LBgrZvKmone+bbQM= X-Google-Smtp-Source: AGHT+IEZ41v1fhC8JMM4JZ7zHR4YWf/tJNwSFXgmFDf+PNEJYCUcuwEG8VotdyY5VKvzP4xwyYe1iA== X-Received: by 2002:a05:6871:6183:b0:1e9:a8ff:67e8 with SMTP id rb3-20020a056871618300b001e9a8ff67e8mr608688oab.50.1697665914999; Wed, 18 Oct 2023 14:51:54 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH 22/61] target/hppa: Pass d to do_cond Date: Wed, 18 Oct 2023 14:50:56 -0700 Message-Id: <20231018215135.1561375-23-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231018215135.1561375-1-richard.henderson@linaro.org> References: <20231018215135.1561375-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:4860:4864:20::2a; envelope-from=richard.henderson@linaro.org; helo=mail-oa1-x2a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697666088633100001 Content-Type: text/plain; charset="utf-8" Hoist the resolution of d up one level above do_cond. Signed-off-by: Richard Henderson --- target/hppa/translate.c | 82 +++++++++++++++++++++++++++-------------- 1 file changed, 54 insertions(+), 28 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index e2b692a6c5..d6edad9adb 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -814,7 +814,7 @@ static bool cond_need_cb(int c) /* Need extensions from TCGv_i32 to TCGv_reg. */ static bool cond_need_ext(DisasContext *ctx, bool d) { - return TARGET_REGISTER_BITS =3D=3D 64 && !d; + return TARGET_REGISTER_BITS =3D=3D 64 && !(ctx->is_pa20 && d); } =20 /* @@ -822,8 +822,8 @@ static bool cond_need_ext(DisasContext *ctx, bool d) * the Parisc 1.1 Architecture Reference Manual for details. */ =20 -static DisasCond do_cond(unsigned cf, TCGv_reg res, - TCGv_reg cb_msb, TCGv_reg sv) +static DisasCond do_cond(DisasContext *ctx, unsigned cf, bool d, + TCGv_reg res, TCGv_reg cb_msb, TCGv_reg sv) { DisasCond cond; TCGv_reg tmp; @@ -833,11 +833,19 @@ static DisasCond do_cond(unsigned cf, TCGv_reg res, cond =3D cond_make_f(); break; case 1: /* =3D / <> (Z / !Z) */ + if (cond_need_ext(ctx, d)) { + tmp =3D tcg_temp_new(); + tcg_gen_ext32u_reg(tmp, res); + res =3D tmp; + } cond =3D cond_make_0(TCG_COND_EQ, res); break; case 2: /* < / >=3D (N ^ V / !(N ^ V) */ tmp =3D tcg_temp_new(); tcg_gen_xor_reg(tmp, res, sv); + if (cond_need_ext(ctx, d)) { + tcg_gen_ext32s_reg(tmp, tmp); + } cond =3D cond_make_0_tmp(TCG_COND_LT, tmp); break; case 3: /* <=3D / > (N ^ V) | Z / !((N ^ V) | Z) */ @@ -852,20 +860,35 @@ static DisasCond do_cond(unsigned cf, TCGv_reg res, */ tmp =3D tcg_temp_new(); tcg_gen_eqv_reg(tmp, res, sv); - tcg_gen_sari_reg(tmp, tmp, TARGET_REGISTER_BITS - 1); - tcg_gen_and_reg(tmp, tmp, res); + if (cond_need_ext(ctx, d)) { + tcg_gen_sextract_reg(tmp, tmp, 31, 1); + tcg_gen_and_reg(tmp, tmp, res); + tcg_gen_ext32u_reg(tmp, tmp); + } else { + tcg_gen_sari_reg(tmp, tmp, TARGET_REGISTER_BITS - 1); + tcg_gen_and_reg(tmp, tmp, res); + } cond =3D cond_make_0_tmp(TCG_COND_EQ, tmp); break; case 4: /* NUV / UV (!C / C) */ + /* Only bit 0 of cb_msb is ever set. */ cond =3D cond_make_0(TCG_COND_EQ, cb_msb); break; case 5: /* ZNV / VNZ (!C | Z / C & !Z) */ tmp =3D tcg_temp_new(); tcg_gen_neg_reg(tmp, cb_msb); tcg_gen_and_reg(tmp, tmp, res); + if (cond_need_ext(ctx, d)) { + tcg_gen_ext32u_reg(tmp, tmp); + } cond =3D cond_make_0_tmp(TCG_COND_EQ, tmp); break; case 6: /* SV / NSV (V / !V) */ + if (cond_need_ext(ctx, d)) { + tmp =3D tcg_temp_new(); + tcg_gen_ext32s_reg(tmp, sv); + sv =3D tmp; + } cond =3D cond_make_0(TCG_COND_LT, sv); break; case 7: /* OD / EV */ @@ -887,10 +910,11 @@ static DisasCond do_cond(unsigned cf, TCGv_reg res, can use the inputs directly. This can allow other computation to be deleted as unused. */ =20 -static DisasCond do_sub_cond(unsigned cf, TCGv_reg res, +static DisasCond do_sub_cond(DisasContext *ctx, unsigned cf, TCGv_reg res, TCGv_reg in1, TCGv_reg in2, TCGv_reg sv) { DisasCond cond; + bool d =3D false; =20 switch (cf >> 1) { case 1: /* =3D / <> */ @@ -909,7 +933,7 @@ static DisasCond do_sub_cond(unsigned cf, TCGv_reg res, cond =3D cond_make(TCG_COND_LEU, in1, in2); break; default: - return do_cond(cf, res, NULL, sv); + return do_cond(ctx, cf, d, res, NULL, sv); } if (cf & 1) { cond.c =3D tcg_invert_cond(cond.c); @@ -927,8 +951,10 @@ static DisasCond do_sub_cond(unsigned cf, TCGv_reg res, * how cases c=3D{2,3} are treated. */ =20 -static DisasCond do_log_cond(unsigned cf, TCGv_reg res) +static DisasCond do_log_cond(DisasContext *ctx, unsigned cf, TCGv_reg res) { + bool d =3D false; + switch (cf) { case 0: /* never */ case 9: /* undef, C */ @@ -957,7 +983,7 @@ static DisasCond do_log_cond(unsigned cf, TCGv_reg res) =20 case 14: /* OD */ case 15: /* EV */ - return do_cond(cf, res, NULL, NULL); + return do_cond(ctx, cf, d, res, NULL, NULL); =20 default: g_assert_not_reached(); @@ -966,7 +992,7 @@ static DisasCond do_log_cond(unsigned cf, TCGv_reg res) =20 /* Similar, but for shift/extract/deposit conditions. */ =20 -static DisasCond do_sed_cond(unsigned orig, TCGv_reg res) +static DisasCond do_sed_cond(DisasContext *ctx, unsigned orig, TCGv_reg re= s) { unsigned c, f; =20 @@ -979,7 +1005,7 @@ static DisasCond do_sed_cond(unsigned orig, TCGv_reg r= es) } f =3D (orig & 4) / 4; =20 - return do_log_cond(c * 2 + f, res); + return do_log_cond(ctx, c * 2 + f, res); } =20 /* Similar, but for unit conditions. */ @@ -1151,7 +1177,7 @@ static void do_add(DisasContext *ctx, unsigned rt, TC= Gv_reg in1, } =20 /* Emit any conditional trap before any writeback. */ - cond =3D do_cond(cf, dest, cb_cond, sv); + cond =3D do_cond(ctx, cf, d, dest, cb_cond, sv); if (is_tc) { tmp =3D tcg_temp_new(); tcg_gen_setcond_reg(cond.c, tmp, cond.a0, cond.a1); @@ -1241,9 +1267,9 @@ static void do_sub(DisasContext *ctx, unsigned rt, TC= Gv_reg in1, =20 /* Compute the condition. We cannot use the special case for borrow. = */ if (!is_b) { - cond =3D do_sub_cond(cf, dest, in1, in2, sv); + cond =3D do_sub_cond(ctx, cf, dest, in1, in2, sv); } else { - cond =3D do_cond(cf, dest, get_carry(ctx, d, cb, cb_msb), sv); + cond =3D do_cond(ctx, cf, d, dest, get_carry(ctx, d, cb, cb_msb), = sv); } =20 /* Emit any conditional trap before any writeback. */ @@ -1306,7 +1332,7 @@ static void do_cmpclr(DisasContext *ctx, unsigned rt,= TCGv_reg in1, } =20 /* Form the condition for the compare. */ - cond =3D do_sub_cond(cf, dest, in1, in2, sv); + cond =3D do_sub_cond(ctx, cf, dest, in1, in2, sv); =20 /* Clear. */ tcg_gen_movi_reg(dest, 0); @@ -1330,7 +1356,7 @@ static void do_log(DisasContext *ctx, unsigned rt, TC= Gv_reg in1, /* Install the new nullification. */ cond_free(&ctx->null_cond); if (cf) { - ctx->null_cond =3D do_log_cond(cf, dest); + ctx->null_cond =3D do_log_cond(ctx, cf, dest); } } =20 @@ -2796,7 +2822,7 @@ static bool trans_ds(DisasContext *ctx, arg_rrr_cf *a) /* ??? The lshift is supposed to contribute to overflow. */ sv =3D do_add_sv(ctx, dest, add1, add2); } - ctx->null_cond =3D do_cond(a->cf, dest, cout, sv); + ctx->null_cond =3D do_cond(ctx, a->cf, false, dest, cout, sv); } =20 return nullify_end(ctx); @@ -3013,7 +3039,7 @@ static bool do_cmpb(DisasContext *ctx, unsigned r, TC= Gv_reg in1, sv =3D do_sub_sv(ctx, dest, in1, in2); } =20 - cond =3D do_sub_cond(c * 2 + f, dest, in1, in2, sv); + cond =3D do_sub_cond(ctx, c * 2 + f, dest, in1, in2, sv); return do_cbranch(ctx, disp, n, &cond); } =20 @@ -3057,7 +3083,7 @@ static bool do_addb(DisasContext *ctx, unsigned r, TC= Gv_reg in1, sv =3D do_add_sv(ctx, dest, in1, in2); } =20 - cond =3D do_cond(c * 2 + f, dest, cb_cond, sv); + cond =3D do_cond(ctx, c * 2 + f, d, dest, cb_cond, sv); save_gpr(ctx, r, dest); return do_cbranch(ctx, disp, n, &cond); } @@ -3128,7 +3154,7 @@ static bool trans_movb(DisasContext *ctx, arg_movb *a) tcg_gen_mov_reg(dest, cpu_gr[a->r1]); } =20 - cond =3D do_sed_cond(a->c, dest); + cond =3D do_sed_cond(ctx, a->c, dest); return do_cbranch(ctx, a->disp, a->n, &cond); } =20 @@ -3142,7 +3168,7 @@ static bool trans_movbi(DisasContext *ctx, arg_movbi = *a) dest =3D dest_gpr(ctx, a->r); tcg_gen_movi_reg(dest, a->i); =20 - cond =3D do_sed_cond(a->c, dest); + cond =3D do_sed_cond(ctx, a->c, dest); return do_cbranch(ctx, a->disp, a->n, &cond); } =20 @@ -3180,7 +3206,7 @@ static bool trans_shrpw_sar(DisasContext *ctx, arg_sh= rpw_sar *a) /* Install the new nullification. */ cond_free(&ctx->null_cond); if (a->c) { - ctx->null_cond =3D do_sed_cond(a->c, dest); + ctx->null_cond =3D do_sed_cond(ctx, a->c, dest); } return nullify_end(ctx); } @@ -3216,7 +3242,7 @@ static bool trans_shrpw_imm(DisasContext *ctx, arg_sh= rpw_imm *a) /* Install the new nullification. */ cond_free(&ctx->null_cond); if (a->c) { - ctx->null_cond =3D do_sed_cond(a->c, dest); + ctx->null_cond =3D do_sed_cond(ctx, a->c, dest); } return nullify_end(ctx); } @@ -3250,7 +3276,7 @@ static bool trans_extrw_sar(DisasContext *ctx, arg_ex= trw_sar *a) /* Install the new nullification. */ cond_free(&ctx->null_cond); if (a->c) { - ctx->null_cond =3D do_sed_cond(a->c, dest); + ctx->null_cond =3D do_sed_cond(ctx, a->c, dest); } return nullify_end(ctx); } @@ -3277,7 +3303,7 @@ static bool trans_extrw_imm(DisasContext *ctx, arg_ex= trw_imm *a) /* Install the new nullification. */ cond_free(&ctx->null_cond); if (a->c) { - ctx->null_cond =3D do_sed_cond(a->c, dest); + ctx->null_cond =3D do_sed_cond(ctx, a->c, dest); } return nullify_end(ctx); } @@ -3314,7 +3340,7 @@ static bool trans_depwi_imm(DisasContext *ctx, arg_de= pwi_imm *a) /* Install the new nullification. */ cond_free(&ctx->null_cond); if (a->c) { - ctx->null_cond =3D do_sed_cond(a->c, dest); + ctx->null_cond =3D do_sed_cond(ctx, a->c, dest); } return nullify_end(ctx); } @@ -3344,7 +3370,7 @@ static bool trans_depw_imm(DisasContext *ctx, arg_dep= w_imm *a) /* Install the new nullification. */ cond_free(&ctx->null_cond); if (a->c) { - ctx->null_cond =3D do_sed_cond(a->c, dest); + ctx->null_cond =3D do_sed_cond(ctx, a->c, dest); } return nullify_end(ctx); } @@ -3381,7 +3407,7 @@ static bool do_depw_sar(DisasContext *ctx, unsigned r= t, unsigned c, /* Install the new nullification. */ cond_free(&ctx->null_cond); if (c) { - ctx->null_cond =3D do_sed_cond(c, dest); + ctx->null_cond =3D do_sed_cond(ctx, c, dest); } return nullify_end(ctx); } --=20 2.34.1 From nobody Wed Nov 27 18:51:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1697666774; cv=none; d=zohomail.com; s=zohoarc; b=MMCt7fkXA0DDHXkw95apw2kTlC/JGH9GE7sslFFqykO8Sq9DTk6CoEuvuU3l0AvNH/YvoUQ7EL3JFgjUXHV3zbVVl81AcJlnHSJsFG23Gq1/wVOck3TZKmTDdyNaz+bq7e0q7i+Fmw6tTQg9uXeQZ+vkWDjSRrdUKA5tfPG4qzI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1697666774; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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Signed-off-by: Richard Henderson --- target/hppa/translate.c | 77 ++++++++++++++++++++++++++--------------- 1 file changed, 49 insertions(+), 28 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index d6edad9adb..7c95c479dc 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -446,12 +446,15 @@ static DisasCond cond_make_n(void) }; } =20 -static DisasCond cond_make_0_tmp(TCGCond c, TCGv_reg a0) +static DisasCond cond_make_tmp(TCGCond c, TCGv_reg a0, TCGv_reg a1) { assert (c !=3D TCG_COND_NEVER && c !=3D TCG_COND_ALWAYS); - return (DisasCond){ - .c =3D c, .a0 =3D a0, .a1 =3D tcg_constant_reg(0) - }; + return (DisasCond){ .c =3D c, .a0 =3D a0, .a1 =3D a1 }; +} + +static DisasCond cond_make_0_tmp(TCGCond c, TCGv_reg a0) +{ + return cond_make_tmp(c, a0, tcg_constant_reg(0)); } =20 static DisasCond cond_make_0(TCGCond c, TCGv_reg a0) @@ -463,15 +466,12 @@ static DisasCond cond_make_0(TCGCond c, TCGv_reg a0) =20 static DisasCond cond_make(TCGCond c, TCGv_reg a0, TCGv_reg a1) { - DisasCond r =3D { .c =3D c }; + TCGv_reg t0 =3D tcg_temp_new(); + TCGv_reg t1 =3D tcg_temp_new(); =20 - assert (c !=3D TCG_COND_NEVER && c !=3D TCG_COND_ALWAYS); - r.a0 =3D tcg_temp_new(); - tcg_gen_mov_reg(r.a0, a0); - r.a1 =3D tcg_temp_new(); - tcg_gen_mov_reg(r.a1, a1); - - return r; + tcg_gen_mov_reg(t0, a0); + tcg_gen_mov_reg(t1, a1); + return cond_make_tmp(c, t0, t1); } =20 static void cond_free(DisasCond *cond) @@ -910,36 +910,55 @@ static DisasCond do_cond(DisasContext *ctx, unsigned = cf, bool d, can use the inputs directly. This can allow other computation to be deleted as unused. */ =20 -static DisasCond do_sub_cond(DisasContext *ctx, unsigned cf, TCGv_reg res, - TCGv_reg in1, TCGv_reg in2, TCGv_reg sv) +static DisasCond do_sub_cond(DisasContext *ctx, unsigned cf, bool d, + TCGv_reg res, TCGv_reg in1, + TCGv_reg in2, TCGv_reg sv) { - DisasCond cond; - bool d =3D false; + TCGCond tc; + bool ext_uns; =20 switch (cf >> 1) { case 1: /* =3D / <> */ - cond =3D cond_make(TCG_COND_EQ, in1, in2); + tc =3D TCG_COND_EQ; + ext_uns =3D true; break; case 2: /* < / >=3D */ - cond =3D cond_make(TCG_COND_LT, in1, in2); + tc =3D TCG_COND_LT; + ext_uns =3D false; break; case 3: /* <=3D / > */ - cond =3D cond_make(TCG_COND_LE, in1, in2); + tc =3D TCG_COND_LE; + ext_uns =3D false; break; case 4: /* << / >>=3D */ - cond =3D cond_make(TCG_COND_LTU, in1, in2); + tc =3D TCG_COND_LTU; + ext_uns =3D true; break; case 5: /* <<=3D / >> */ - cond =3D cond_make(TCG_COND_LEU, in1, in2); + tc =3D TCG_COND_LEU; + ext_uns =3D true; break; default: return do_cond(ctx, cf, d, res, NULL, sv); } - if (cf & 1) { - cond.c =3D tcg_invert_cond(cond.c); - } =20 - return cond; + if (cf & 1) { + tc =3D tcg_invert_cond(tc); + } + if (cond_need_ext(ctx, d)) { + TCGv_reg t1 =3D tcg_temp_new(); + TCGv_reg t2 =3D tcg_temp_new(); + + if (ext_uns) { + tcg_gen_ext32u_reg(t1, in1); + tcg_gen_ext32u_reg(t2, in2); + } else { + tcg_gen_ext32s_reg(t1, in1); + tcg_gen_ext32s_reg(t2, in2); + } + return cond_make_tmp(tc, t1, t2); + } + return cond_make(tc, in1, in2); } =20 /* @@ -1267,7 +1286,7 @@ static void do_sub(DisasContext *ctx, unsigned rt, TC= Gv_reg in1, =20 /* Compute the condition. We cannot use the special case for borrow. = */ if (!is_b) { - cond =3D do_sub_cond(ctx, cf, dest, in1, in2, sv); + cond =3D do_sub_cond(ctx, cf, d, dest, in1, in2, sv); } else { cond =3D do_cond(ctx, cf, d, dest, get_carry(ctx, d, cb, cb_msb), = sv); } @@ -1321,6 +1340,7 @@ static void do_cmpclr(DisasContext *ctx, unsigned rt,= TCGv_reg in1, { TCGv_reg dest, sv; DisasCond cond; + bool d =3D false; =20 dest =3D tcg_temp_new(); tcg_gen_sub_reg(dest, in1, in2); @@ -1332,7 +1352,7 @@ static void do_cmpclr(DisasContext *ctx, unsigned rt,= TCGv_reg in1, } =20 /* Form the condition for the compare. */ - cond =3D do_sub_cond(ctx, cf, dest, in1, in2, sv); + cond =3D do_sub_cond(ctx, cf, d, dest, in1, in2, sv); =20 /* Clear. */ tcg_gen_movi_reg(dest, 0); @@ -3028,6 +3048,7 @@ static bool do_cmpb(DisasContext *ctx, unsigned r, TC= Gv_reg in1, { TCGv_reg dest, in2, sv; DisasCond cond; + bool d =3D false; =20 in2 =3D load_gpr(ctx, r); dest =3D tcg_temp_new(); @@ -3039,7 +3060,7 @@ static bool do_cmpb(DisasContext *ctx, unsigned r, TC= Gv_reg in1, sv =3D do_sub_sv(ctx, dest, in1, in2); } =20 - cond =3D do_sub_cond(ctx, c * 2 + f, dest, in1, in2, sv); + cond =3D do_sub_cond(ctx, c * 2 + f, d, dest, in1, in2, sv); return do_cbranch(ctx, disp, n, &cond); } =20 --=20 2.34.1 From nobody Wed Nov 27 18:51:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1697666672; cv=none; d=zohomail.com; s=zohoarc; b=VHDlzWWGau7DMAuzo9voFHo3q/3V8VG1w8TPgiKSJqoAc+X9sGvrRxcxdXDBanrMvTbKlDwhcxWPS8HT2cb4AqBoFLomAOu5C7xckpKDmmxiId+TWnwZW49j0hrKqgXEddvOoEOC1WYniWKsLfAmVZEUZ22dOpVlb/+6phBlG8I= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1697666672; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=IzgNOQnYTPtvhWHame0+1TsFsoAlkTYKxkzC3eocI48=; b=GycZ8un//hXg65GYL9ZCtW+cmq6E79nLTZRp8IDPw8xZqCLmkVfyfYSmawD+RxcV9FSCwpA0r1QaoRfwV7kwsQ8GQyo+zGeHTO2EN3prMydPyWI2JiAO6YWYB+QO5/oekz9ix9h3vlNiJM5nuNQRMaO5NpgHTiYxoo5qhKN9ARw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1697666672235252.96708233952438; Wed, 18 Oct 2023 15:04:32 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qtESj-0001tR-Ox; Wed, 18 Oct 2023 17:52:21 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qtESQ-00019o-Aq for qemu-devel@nongnu.org; Wed, 18 Oct 2023 17:52:05 -0400 Received: from mail-il1-x12b.google.com ([2607:f8b0:4864:20::12b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qtESN-0004RS-29 for qemu-devel@nongnu.org; Wed, 18 Oct 2023 17:52:00 -0400 Received: by mail-il1-x12b.google.com with SMTP id e9e14a558f8ab-3514bf96fd2so29603295ab.0 for ; Wed, 18 Oct 2023 14:51:58 -0700 (PDT) Received: from stoup.. ([71.212.149.95]) by smtp.gmail.com with ESMTPSA id w17-20020a63f511000000b005b61a024ec7sm2176380pgh.74.2023.10.18.14.51.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Oct 2023 14:51:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1697665917; x=1698270717; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=IzgNOQnYTPtvhWHame0+1TsFsoAlkTYKxkzC3eocI48=; b=XO+OaPlEVOURV6KPPhALzuBw+5A8nUD3Brb+1gCYuGvbVDULSUSx5Nt1MWOp92p/Y6 q/UQ9LmPYfB+SkKPMe8bvibxTz0E+oHfMRqJtB4oi7/W+t0jh+Cw+Y8FTy8VflMpijwv 1IIDUSKXC2+WNqbON/HGGtlYOPJTwZXxYEyIWKZqzuopS8j8kSmHetGa7iRefLfHDf9v 2NiavH1HuhD2TNuIzmZEoVKRDFGWbbpMlNyBg0wdZH0uGcWsZZk0GYUn3xaZP0+f5/Lm u5stPykyKOcnupH4AA6te53JcKsFSEmVozN5iOrue40DXF8mS2118XkR1symf5BRFmSm IVFA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697665917; x=1698270717; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=IzgNOQnYTPtvhWHame0+1TsFsoAlkTYKxkzC3eocI48=; b=iJBCpdQMM0SgpZQz8ZhAir/W15HdXnpaVFsHgQwyzQ3ADd+vgSwm7otSkMRQNXlU0q ckQCAJY5Ma4Ri9AZ/SwB943VEBMERThAXJ8oAu9exnFE0OpbC8w2mLo2bdTB6lG3pYwp RB21uHBxKXbeJHv2DbyX4oJA7L/EVZ17aYwV+amt+CYJDzZjSonPTklPXPHYLHkwLWlu 0gWgd2tdeEJ8UZ0NWQ61NdCA5H3+pm1egfEcweAFE25hhid5smjyFQcMxiaNV0cEdnz3 mup19x9nmMQdM0V/txgHkuYluKgPu2TtSR8i74+vY5xwYNWgFc+bIenBUZq5Ms1419fU b9gA== X-Gm-Message-State: AOJu0YylHit97kIeCekAYgkK5dmwDCxgc63L1T0WAQKF2tRpbjWWBes+ fY1opA+tB0XMo/13ODs2tARhq9LN6g5UzTqrcQs= X-Google-Smtp-Source: AGHT+IEmKxzWzFrC/YN16KUkVbUwDbP0wLQsfsJs1XnPqBcdD18sut7HuebsE/YBKRCQpxKSa4KB+Q== X-Received: by 2002:a92:c14a:0:b0:357:3d32:bf76 with SMTP id b10-20020a92c14a000000b003573d32bf76mr658827ilh.1.1697665917234; Wed, 18 Oct 2023 14:51:57 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH 24/61] target/hppa: Pass d to do_log_cond Date: Wed, 18 Oct 2023 14:50:58 -0700 Message-Id: <20231018215135.1561375-25-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231018215135.1561375-1-richard.henderson@linaro.org> References: <20231018215135.1561375-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::12b; envelope-from=richard.henderson@linaro.org; helo=mail-il1-x12b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697666673467100002 Content-Type: text/plain; charset="utf-8" Hoist the resolution of d up one level above do_log_cond. Signed-off-by: Richard Henderson --- target/hppa/translate.c | 48 ++++++++++++++++++++++++++++++++--------- 1 file changed, 38 insertions(+), 10 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 7c95c479dc..7a3b0f1de7 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -970,9 +970,11 @@ static DisasCond do_sub_cond(DisasContext *ctx, unsign= ed cf, bool d, * how cases c=3D{2,3} are treated. */ =20 -static DisasCond do_log_cond(DisasContext *ctx, unsigned cf, TCGv_reg res) +static DisasCond do_log_cond(DisasContext *ctx, unsigned cf, bool d, + TCGv_reg res) { - bool d =3D false; + TCGCond tc; + bool ext_uns; =20 switch (cf) { case 0: /* never */ @@ -988,17 +990,29 @@ static DisasCond do_log_cond(DisasContext *ctx, unsig= ned cf, TCGv_reg res) return cond_make_t(); =20 case 2: /* =3D=3D */ - return cond_make_0(TCG_COND_EQ, res); + tc =3D TCG_COND_EQ; + ext_uns =3D true; + break; case 3: /* <> */ - return cond_make_0(TCG_COND_NE, res); + tc =3D TCG_COND_NE; + ext_uns =3D true; + break; case 4: /* < */ - return cond_make_0(TCG_COND_LT, res); + tc =3D TCG_COND_LT; + ext_uns =3D false; + break; case 5: /* >=3D */ - return cond_make_0(TCG_COND_GE, res); + tc =3D TCG_COND_GE; + ext_uns =3D false; + break; case 6: /* <=3D */ - return cond_make_0(TCG_COND_LE, res); + tc =3D TCG_COND_LE; + ext_uns =3D false; + break; case 7: /* > */ - return cond_make_0(TCG_COND_GT, res); + tc =3D TCG_COND_GT; + ext_uns =3D false; + break; =20 case 14: /* OD */ case 15: /* EV */ @@ -1007,6 +1021,18 @@ static DisasCond do_log_cond(DisasContext *ctx, unsi= gned cf, TCGv_reg res) default: g_assert_not_reached(); } + + if (cond_need_ext(ctx, d)) { + TCGv_reg tmp =3D tcg_temp_new(); + + if (ext_uns) { + tcg_gen_ext32u_reg(tmp, res); + } else { + tcg_gen_ext32s_reg(tmp, res); + } + return cond_make_0_tmp(tc, tmp); + } + return cond_make_0(tc, res); } =20 /* Similar, but for shift/extract/deposit conditions. */ @@ -1014,6 +1040,7 @@ static DisasCond do_log_cond(DisasContext *ctx, unsig= ned cf, TCGv_reg res) static DisasCond do_sed_cond(DisasContext *ctx, unsigned orig, TCGv_reg re= s) { unsigned c, f; + bool d =3D false; =20 /* Convert the compressed condition codes to standard. 0-2 are the same as logicals (nv,<,<=3D), while 3 is OD. @@ -1024,7 +1051,7 @@ static DisasCond do_sed_cond(DisasContext *ctx, unsig= ned orig, TCGv_reg res) } f =3D (orig & 4) / 4; =20 - return do_log_cond(ctx, c * 2 + f, res); + return do_log_cond(ctx, c * 2 + f, d, res); } =20 /* Similar, but for unit conditions. */ @@ -1368,6 +1395,7 @@ static void do_log(DisasContext *ctx, unsigned rt, TC= Gv_reg in1, void (*fn)(TCGv_reg, TCGv_reg, TCGv_reg)) { TCGv_reg dest =3D dest_gpr(ctx, rt); + bool d =3D false; =20 /* Perform the operation, and writeback. */ fn(dest, in1, in2); @@ -1376,7 +1404,7 @@ static void do_log(DisasContext *ctx, unsigned rt, TC= Gv_reg in1, /* Install the new nullification. */ cond_free(&ctx->null_cond); if (cf) { - ctx->null_cond =3D do_log_cond(ctx, cf, dest); + ctx->null_cond =3D do_log_cond(ctx, cf, d, dest); } } =20 --=20 2.34.1 From nobody Wed Nov 27 18:51:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id w17-20020a63f511000000b005b61a024ec7sm2176380pgh.74.2023.10.18.14.51.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Oct 2023 14:51:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1697665918; x=1698270718; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=pahNvfSbaXH7GCmgh8txSi9o/B1oidjE9rEfxQaDzTc=; b=Crh1We5TM6avpIpDTdEZaZHk5/WK/BAj4bMe+eHLo/FETb3TWr9uCy5cJsbwiSZhuq UsBvF61sVudl4y4ZRGGA90vSJZc6QPoMXxSG6ga73eJppyHiiG1vKYKSsFCtaX/DWOOR ZEaO0Y20Y0QfAaUDHypIPZ0J1LZEFC/tJ5uVP3tKW33zjHe1RqTZE09zLFM+PZoW0cmV 1Bfpx2O7NW/YkL1+kdbXSM3mKWl6nZ7E7p8G8LBSMe6BR5xYY6ss8IYSZDRMXhi+6v2E XXJbm2tYd6m3m+3nnjYw1BiNpPv3Jvi6fNpEgLhrcd5/jvidXsxbZIIjyuuMxom9O8VJ 8ZbA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697665918; x=1698270718; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=pahNvfSbaXH7GCmgh8txSi9o/B1oidjE9rEfxQaDzTc=; b=nkZe47GGAEL0gozueS2sYR4Lgy4FY4gqFYkT/WPzD14vao9bUqLXAw7tdX3vb2DcVN E9sHBOtz6eve+nfC7y0i0bkd0LkVjeSnL6wZn5NtWNk2BMHCbatPdw2BEKvkAcMxkqlw /V/wAv4pvUFiHjKVQZGqaO6Qg+F65heQagtUrqj3P/USr7Xz8qNfI8Sx7ZFEOhzxn1eL DgQHZ9Pu9mUiQ5btf3muOPVSSqCVDQTM8NcP3jHxLjMlcTvcSM72cDBEfguBA9F3iKg0 OKapwVx0sMGQkvyltUxmvH5BxoEvaYrrFvbGZmIefRAT2LxVjzI2gqGusL5gx9lgUnSn aC1Q== X-Gm-Message-State: AOJu0YxJtB8mYHqmxt27iE/Rl9kvuWGG1MNm+11R5AD4k3hSn0gur/10 /urhFhcLiFy+JxedFnaCnsZuRR+GJKRQ6gZmsBU= X-Google-Smtp-Source: AGHT+IGf5Q7xFJ+Oxqmpxgr4D5D9Q4oe/j7REOL0a973jv2jA6owJP63G9YuXXF942I86CwWdMHF+g== X-Received: by 2002:a05:6359:3015:b0:166:dcf6:cd82 with SMTP id rf21-20020a056359301500b00166dcf6cd82mr248039rwb.14.1697665918070; Wed, 18 Oct 2023 14:51:58 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH 25/61] target/hppa: Pass d to do_sed_cond Date: Wed, 18 Oct 2023 14:50:59 -0700 Message-Id: <20231018215135.1561375-26-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231018215135.1561375-1-richard.henderson@linaro.org> References: <20231018215135.1561375-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::c2a; envelope-from=richard.henderson@linaro.org; helo=mail-oo1-xc2a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697666044498100003 Content-Type: text/plain; charset="utf-8" Hoist the resolution of d up one level above do_sed_cond. The MOVB comparison and the existing shift/extract/deposit are all 32-bit. Signed-off-by: Richard Henderson --- target/hppa/translate.c | 24 +++++++++++++----------- 1 file changed, 13 insertions(+), 11 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 7a3b0f1de7..1a51ac4869 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -1037,10 +1037,10 @@ static DisasCond do_log_cond(DisasContext *ctx, uns= igned cf, bool d, =20 /* Similar, but for shift/extract/deposit conditions. */ =20 -static DisasCond do_sed_cond(DisasContext *ctx, unsigned orig, TCGv_reg re= s) +static DisasCond do_sed_cond(DisasContext *ctx, unsigned orig, bool d, + TCGv_reg res) { unsigned c, f; - bool d =3D false; =20 /* Convert the compressed condition codes to standard. 0-2 are the same as logicals (nv,<,<=3D), while 3 is OD. @@ -3203,7 +3203,8 @@ static bool trans_movb(DisasContext *ctx, arg_movb *a) tcg_gen_mov_reg(dest, cpu_gr[a->r1]); } =20 - cond =3D do_sed_cond(ctx, a->c, dest); + /* All MOVB conditions are 32-bit. */ + cond =3D do_sed_cond(ctx, a->c, false, dest); return do_cbranch(ctx, a->disp, a->n, &cond); } =20 @@ -3217,7 +3218,8 @@ static bool trans_movbi(DisasContext *ctx, arg_movbi = *a) dest =3D dest_gpr(ctx, a->r); tcg_gen_movi_reg(dest, a->i); =20 - cond =3D do_sed_cond(ctx, a->c, dest); + /* All MOVBI conditions are 32-bit. */ + cond =3D do_sed_cond(ctx, a->c, false, dest); return do_cbranch(ctx, a->disp, a->n, &cond); } =20 @@ -3255,7 +3257,7 @@ static bool trans_shrpw_sar(DisasContext *ctx, arg_sh= rpw_sar *a) /* Install the new nullification. */ cond_free(&ctx->null_cond); if (a->c) { - ctx->null_cond =3D do_sed_cond(ctx, a->c, dest); + ctx->null_cond =3D do_sed_cond(ctx, a->c, false, dest); } return nullify_end(ctx); } @@ -3291,7 +3293,7 @@ static bool trans_shrpw_imm(DisasContext *ctx, arg_sh= rpw_imm *a) /* Install the new nullification. */ cond_free(&ctx->null_cond); if (a->c) { - ctx->null_cond =3D do_sed_cond(ctx, a->c, dest); + ctx->null_cond =3D do_sed_cond(ctx, a->c, false, dest); } return nullify_end(ctx); } @@ -3325,7 +3327,7 @@ static bool trans_extrw_sar(DisasContext *ctx, arg_ex= trw_sar *a) /* Install the new nullification. */ cond_free(&ctx->null_cond); if (a->c) { - ctx->null_cond =3D do_sed_cond(ctx, a->c, dest); + ctx->null_cond =3D do_sed_cond(ctx, a->c, false, dest); } return nullify_end(ctx); } @@ -3352,7 +3354,7 @@ static bool trans_extrw_imm(DisasContext *ctx, arg_ex= trw_imm *a) /* Install the new nullification. */ cond_free(&ctx->null_cond); if (a->c) { - ctx->null_cond =3D do_sed_cond(ctx, a->c, dest); + ctx->null_cond =3D do_sed_cond(ctx, a->c, false, dest); } return nullify_end(ctx); } @@ -3389,7 +3391,7 @@ static bool trans_depwi_imm(DisasContext *ctx, arg_de= pwi_imm *a) /* Install the new nullification. */ cond_free(&ctx->null_cond); if (a->c) { - ctx->null_cond =3D do_sed_cond(ctx, a->c, dest); + ctx->null_cond =3D do_sed_cond(ctx, a->c, false, dest); } return nullify_end(ctx); } @@ -3419,7 +3421,7 @@ static bool trans_depw_imm(DisasContext *ctx, arg_dep= w_imm *a) /* Install the new nullification. */ cond_free(&ctx->null_cond); if (a->c) { - ctx->null_cond =3D do_sed_cond(ctx, a->c, dest); + ctx->null_cond =3D do_sed_cond(ctx, a->c, false, dest); } return nullify_end(ctx); } @@ -3456,7 +3458,7 @@ static bool do_depw_sar(DisasContext *ctx, unsigned r= t, unsigned c, /* Install the new nullification. */ cond_free(&ctx->null_cond); if (c) { - ctx->null_cond =3D do_sed_cond(ctx, c, dest); + ctx->null_cond =3D do_sed_cond(ctx, c, false, dest); } return nullify_end(ctx); } --=20 2.34.1 From nobody Wed Nov 27 18:51:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1697666526; cv=none; d=zohomail.com; s=zohoarc; b=ah9Qe78LHbKEkjYwyWflh5WjjFlpCUvdoNsg1q8VULAHCII+YMjJSryQXXsaWSMf0H2VAWXQ9WB8x++bOVnY34qVCNvckGsfntpHm5NEu8is2DTJeqJ5Mgb+LGThUCUULiDyOlg9LcjGX0HKOUi8i0ooNHIgNTyYUX1KupXgarg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id w17-20020a63f511000000b005b61a024ec7sm2176380pgh.74.2023.10.18.14.51.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Oct 2023 14:51:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1697665919; x=1698270719; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=J7IvWHKNslLXyxg2gDsUoAZIYZRNssROan/QZtA5zx8=; b=C5MnWHZoTGAv0Z3nTmEM8dpenBbjFupjo4DxWkzPdQar78cyjTymNq8VglYO23Dkfu sTnfQIEE6oWz+nawwK+NSxTpJ8xwWNXh+YCfD/nId+VVwNnG8FiZGg35JfwTBWXlNoco yMVl853X8qiU6ykwCpnBysL5g9zBTWNQufWwsND+VZpQhAGgIC/nhWoG5+EQh1TrquWj IJd/7HqekQ/mteeHxpqxwkTP9AgTJBIFS/4IL3EOse20Z7eFVHR+6TPGhaAKdhFTVnGs PR+DQdqqdggWoWXlBIWccSRwJYFKbXIum71949tFF99k4M0+rF6aWhN2toxCwf4MAz9h QHqQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697665919; x=1698270719; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=J7IvWHKNslLXyxg2gDsUoAZIYZRNssROan/QZtA5zx8=; b=WO4TrnPht+d7KRi64U17dZ2qMbuSS//+/dWQkBvgkzy93uKmFNOcHHzgGXxM33wEYa L9B/MEEqYpQVsXvzGRRD8o5u/XN/IYJCOkoRwbez7O46mWt13Olt5om9OEPcSy7n9COw GHqwmkzRKmBq+n/EBa8H52oLdXC0N7eWyWVwTuWjgtrqS8P+BFePRcwvjoiJDNM2QpP3 l5aPATzaUABfOaxbaEqxjRqBivraY+942tib4kGTLx9W8k0IvOfGtw8x9KdK/ZnXtkFr NalTc4cyK5ZgaZx8xYYzVBrE3dYPmhTopEhP3acWri9GaXpkSRjB3JUakcVbvmTA4pTv I+2A== X-Gm-Message-State: AOJu0YzDckaNj1eoIPYTUq/fQzc63+xfcC99ZRbS2B5yVp97GyieR3K3 DzhQMSSbin268cU8zABU8nYaCUEMEV1GZduqO1o= X-Google-Smtp-Source: AGHT+IH3qtik9S79chgKlomdD8n790b7kf8E/DYGA19itm2Yjfbp1pfn8ZzI3uxz4j+4AMNb7clmqA== X-Received: by 2002:a05:6a20:42a0:b0:16b:c9f2:b632 with SMTP id o32-20020a056a2042a000b0016bc9f2b632mr456356pzj.62.1697665918873; Wed, 18 Oct 2023 14:51:58 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH 26/61] target/hppa: Pass d to do_unit_cond Date: Wed, 18 Oct 2023 14:51:00 -0700 Message-Id: <20231018215135.1561375-27-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231018215135.1561375-1-richard.henderson@linaro.org> References: <20231018215135.1561375-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52f; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697666528841100003 Content-Type: text/plain; charset="utf-8" Hoist the resolution of d up one level above do_unit_cond. All computations are logical, and are simplified by using a mask of the correct width, after which the result may be compared with zero. Signed-off-by: Richard Henderson --- target/hppa/translate.c | 20 +++++++++++--------- 1 file changed, 11 insertions(+), 9 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 1a51ac4869..8bea28f0fd 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -1056,11 +1056,12 @@ static DisasCond do_sed_cond(DisasContext *ctx, uns= igned orig, bool d, =20 /* Similar, but for unit conditions. */ =20 -static DisasCond do_unit_cond(unsigned cf, TCGv_reg res, +static DisasCond do_unit_cond(unsigned cf, bool d, TCGv_reg res, TCGv_reg in1, TCGv_reg in2) { DisasCond cond; TCGv_reg tmp, cb =3D NULL; + target_ureg d_repl =3D d ? 0x0000000100000001ull : 1; =20 if (cf & 8) { /* Since we want to test lots of carry-out bits all at once, do not @@ -1087,32 +1088,32 @@ static DisasCond do_unit_cond(unsigned cf, TCGv_reg= res, * https://graphics.stanford.edu/~seander/bithacks.html#ZeroInWord */ tmp =3D tcg_temp_new(); - tcg_gen_subi_reg(tmp, res, 0x01010101u); + tcg_gen_subi_reg(tmp, res, d_repl * 0x01010101u); tcg_gen_andc_reg(tmp, tmp, res); - tcg_gen_andi_reg(tmp, tmp, 0x80808080u); + tcg_gen_andi_reg(tmp, tmp, d_repl * 0x80808080u); cond =3D cond_make_0(TCG_COND_NE, tmp); break; =20 case 3: /* SHZ / NHZ */ tmp =3D tcg_temp_new(); - tcg_gen_subi_reg(tmp, res, 0x00010001u); + tcg_gen_subi_reg(tmp, res, d_repl * 0x00010001u); tcg_gen_andc_reg(tmp, tmp, res); - tcg_gen_andi_reg(tmp, tmp, 0x80008000u); + tcg_gen_andi_reg(tmp, tmp, d_repl * 0x80008000u); cond =3D cond_make_0(TCG_COND_NE, tmp); break; =20 case 4: /* SDC / NDC */ - tcg_gen_andi_reg(cb, cb, 0x88888888u); + tcg_gen_andi_reg(cb, cb, d_repl * 0x88888888u); cond =3D cond_make_0(TCG_COND_NE, cb); break; =20 case 6: /* SBC / NBC */ - tcg_gen_andi_reg(cb, cb, 0x80808080u); + tcg_gen_andi_reg(cb, cb, d_repl * 0x80808080u); cond =3D cond_make_0(TCG_COND_NE, cb); break; =20 case 7: /* SHC / NHC */ - tcg_gen_andi_reg(cb, cb, 0x80008000u); + tcg_gen_andi_reg(cb, cb, d_repl * 0x80008000u); cond =3D cond_make_0(TCG_COND_NE, cb); break; =20 @@ -1428,6 +1429,7 @@ static void do_unit(DisasContext *ctx, unsigned rt, T= CGv_reg in1, { TCGv_reg dest; DisasCond cond; + bool d =3D false; =20 if (cf =3D=3D 0) { dest =3D dest_gpr(ctx, rt); @@ -1438,7 +1440,7 @@ static void do_unit(DisasContext *ctx, unsigned rt, T= CGv_reg in1, dest =3D tcg_temp_new(); fn(dest, in1, in2); =20 - cond =3D do_unit_cond(cf, dest, in1, in2); + cond =3D do_unit_cond(cf, d, dest, in1, in2); =20 if (is_tc) { TCGv_reg tmp =3D tcg_temp_new(); --=20 2.34.1 From nobody Wed Nov 27 18:51:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1697666348; cv=none; d=zohomail.com; s=zohoarc; b=b/DV0QebH9ZMj/6zFrFbeBF3ANsXNBjavYhl1WIay8zW3dGg55nDaWJ9UHPPw+MtlNjqnUou1OfHNbdEdlNYDROTw1tmaIr3vFEtaj68AG+CySjg5YS7lac30hDauHXvlglVc+naIlKIbGHH2CXPS054ag1QKv54zhB2ey4fF5E= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1697666348; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=yOt4L4RU9DBVWKbMxLcMk3VZCZC7MfUNBnEhx3kY+Fc=; b=EWg51jlou1UBjXw8x/AEkmn2Co5WaanR5rwjD/PoTuonyltDeyScnZ7NgAtNgsLOQb8p1/bhEH2cGBCHUOSyeYPbuYVArONeKQ0CTYQxrQNbWW58tDymuSQN7+9s01iHu1kYGrJ1o3QsdUCZKtIr1DOLAnEWmYtxoP0bFZdzXKs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1697666348883522.9616469383373; Wed, 18 Oct 2023 14:59:08 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qtESg-0001me-9T; Wed, 18 Oct 2023 17:52:18 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qtESR-00019x-IL for qemu-devel@nongnu.org; Wed, 18 Oct 2023 17:52:05 -0400 Received: from mail-ot1-x332.google.com ([2607:f8b0:4864:20::332]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qtESQ-0004Rq-3M for qemu-devel@nongnu.org; Wed, 18 Oct 2023 17:52:03 -0400 Received: by mail-ot1-x332.google.com with SMTP id 46e09a7af769-6cd1918afb2so459275a34.0 for ; Wed, 18 Oct 2023 14:52:00 -0700 (PDT) Received: from stoup.. ([71.212.149.95]) by smtp.gmail.com with ESMTPSA id w17-20020a63f511000000b005b61a024ec7sm2176380pgh.74.2023.10.18.14.51.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Oct 2023 14:51:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1697665919; x=1698270719; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=yOt4L4RU9DBVWKbMxLcMk3VZCZC7MfUNBnEhx3kY+Fc=; b=SHniBY42fKvkFZkXlqSSDnyFbnOI1oRYeApv7cMj5QslXTWlZ6u757kcceMPj8qcBQ 34dVaAKN0cLSRtq8Mmc0B0jygMsapQUIXiJ9MfVfD9WASmMYzpDQGVCPc111zpiXErYt +9e2a4KVn7ehfMikwaZIYoI9+orAcEBKwcpjtnDDeKBMCGBDLzw10a0UnNg1QikPN+hr /bkmulezy7KurS02gVUkGyTcy5/Q42TISAqG+kwlsDPFcmGRYMpYsEdlciZkq9fDajFO NyqhdmAv2qqN19yZrnC9U1HH0vR0az3EhaiJdDd33Jk9or/1k0AtCQr3BUx3wK/kEwk+ K8Ag== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697665919; x=1698270719; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=yOt4L4RU9DBVWKbMxLcMk3VZCZC7MfUNBnEhx3kY+Fc=; b=Ke8Z0/imzeLHp6i43kkKpt2TgXlccGi3tzLXAYY9sxNZUF/OZcM8fxEE2rtMMjrGlm oJ2/3rd/+77pofFFr3T0aSgaWW4aW5JP3kXXB+UGApHNhkbeDVAipBwMhOwkwXhvlA0h eNzWEo8efygk6hK074zr8hV/i7cxgBzdMPnqoTXqNqxJjIx6JclbW84fjFVNdK89E3DN xzb1sD803c02VuTKR1+gt1HR2bd0yRpLRVu0wP/JnO6PDlB/hc+S8eUG0nW+tywPSGeH OuSZSYBuEvRYeyPt0KEjfHzzfuJykfJDAG7ilBFb2ouYuN1y+b7SFOXf5W36astWwODA Q2pA== X-Gm-Message-State: AOJu0Yyy434UgniAjoga0Syft67Lx0130Lwk70kCCi0ucthQiiN8ZR3D cA4zKzE1hHKch4jrY6lF+HMb2VZ/+feNi/xlPcA= X-Google-Smtp-Source: AGHT+IHRF1clxXTp2U3f5YzyVIN4Dsxlz7k9YQy4L0f5OctGtXtu11YpRUqVX8CX7sTg3fb+aKWdGw== X-Received: by 2002:a05:6870:b406:b0:1e9:b496:ce2d with SMTP id x6-20020a056870b40600b001e9b496ce2dmr862259oap.12.1697665919588; Wed, 18 Oct 2023 14:51:59 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH 27/61] linux-user/hppa: Fixes for TARGET_ABI32 Date: Wed, 18 Oct 2023 14:51:01 -0700 Message-Id: <20231018215135.1561375-28-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231018215135.1561375-1-richard.henderson@linaro.org> References: <20231018215135.1561375-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::332; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697666350085100006 Content-Type: text/plain; charset="utf-8" Avoid target_ulong and use abi_* types. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- linux-user/hppa/signal.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/linux-user/hppa/signal.c b/linux-user/hppa/signal.c index ec5f5412d1..4400ce4df4 100644 --- a/linux-user/hppa/signal.c +++ b/linux-user/hppa/signal.c @@ -72,7 +72,7 @@ static void setup_sigcontext(struct target_sigcontext *sc= , CPUArchState *env) =20 static void restore_sigcontext(CPUArchState *env, struct target_sigcontext= *sc) { - target_ulong psw; + abi_ulong psw; int i; =20 __get_user(psw, &sc->sc_gr[0]); @@ -146,10 +146,10 @@ void setup_rt_frame(int sig, struct target_sigaction = *ka, haddr =3D ka->_sa_handler; if (haddr & 2) { /* Function descriptor. */ - target_ulong *fdesc, dest; + abi_ptr *fdesc, dest; =20 haddr &=3D -4; - fdesc =3D lock_user(VERIFY_READ, haddr, 2 * sizeof(target_ulong), = 1); + fdesc =3D lock_user(VERIFY_READ, haddr, 2 * sizeof(abi_ptr), 1); if (!fdesc) { goto give_sigsegv; } --=20 2.34.1 From nobody Wed Nov 27 18:51:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1697666259; cv=none; d=zohomail.com; s=zohoarc; b=cMXfYr7lO5UJ5HFUr1Ab0uX4jJPUekOMyFbBDGnmq5JlqnZiinqnWAJw5VxtwuQ+5jKV10EpFlpUMHNI+twUW4UQYwAoJJ40SrM/lmP9xBFdB4QN3VF48E1nwodq41dzt6nTTytpCbdGEL4ywQUvpe+EZyGHmmAvxNqMDiYYMWs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1697666259; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=q9hX0qQk5CZemXO2IHvqPOvMFc4SeZE7uxuiBohTGeQ=; b=UMWtZLqGNP2NNZ/6IBOIfV4hQf7A3pc2EzzOj6fAoaJj2QTSUIo2Cd0B4lSRofsO0OgyaDweX0l+Gt7PMXFqVYRDKmvwK/7HKaLnj9hMeNpYZwRY35AU1tv4vfIcwR/t4kwL7CuLWPEkDJ9PLIyYyTDsMehaCHAPsG9DpKqnO5o= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1697666259890822.2885517998888; Wed, 18 Oct 2023 14:57:39 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qtESf-0001mS-B2; Wed, 18 Oct 2023 17:52:17 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qtESS-00019y-Re for qemu-devel@nongnu.org; Wed, 18 Oct 2023 17:52:05 -0400 Received: from mail-oa1-x29.google.com ([2001:4860:4864:20::29]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qtESQ-0004Ry-3f for qemu-devel@nongnu.org; Wed, 18 Oct 2023 17:52:04 -0400 Received: by mail-oa1-x29.google.com with SMTP id 586e51a60fabf-1ea98ad294cso1059494fac.3 for ; Wed, 18 Oct 2023 14:52:01 -0700 (PDT) Received: from stoup.. ([71.212.149.95]) by smtp.gmail.com with ESMTPSA id w17-20020a63f511000000b005b61a024ec7sm2176380pgh.74.2023.10.18.14.51.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Oct 2023 14:51:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1697665920; x=1698270720; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=q9hX0qQk5CZemXO2IHvqPOvMFc4SeZE7uxuiBohTGeQ=; b=rP0aYlJLBYRj504qc9z1I05HOSUqpF3the29/j95i84+dNWVPpd+nidN7KD/8GZDqF u+Y10DWf76k5zZZ4xQCLggXvz5xg3L8o0exWMl76c2hIgBrAjwyjl4Na0YVg+GT7cuYm nwTZ6UDF2YSKdKvRHBvqEVPANOblpPWcMXEBKZHwrGCQEsRM2ye6/eHrXUQXzamGAOud 1TGGdQWY11BANXk/thDDupfQPrPO8WuKliIe4omDCJrJj9qxM3GTaW95nARmq2+u/qXM Il+L4CgDwtEJM82aXazMpWsl/2W9XsyV8BgUMnZX7mXFLJ5bsIhNL+FHK+4DZoEgsAQC U7Kg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697665920; x=1698270720; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=q9hX0qQk5CZemXO2IHvqPOvMFc4SeZE7uxuiBohTGeQ=; b=h2su3SH541tw8wggf7QI81oj/pE2R//N/LDbmEj8YEh0JGBL/ZX4JVXgJsiv3yzNrv r5wXGGVhVeKH77Ox6/0JVcib13lPTKUINbaKfs7sx3im24WD3jxaUwpw4FMj1MfuVbRe udmU8KsAv4B790WQqjsuDE0fs2TESJT1ZHKGbmiX+b38PhmBnxHhxYbRyc1jqX07pZGT 2Emnyjf5XCSrIXa9IOzUZ7ybQAr7nT+5g/TSiiFXpAC29hFRFCMGZ0K1kdI0twc32GKl DVDSdYMICHVGlsCjv/tpVbj5kbaVatpnEmXQW95qIHLbPVBGl49n+lrPFThhvWXfu5ER syTQ== X-Gm-Message-State: AOJu0YwytO9MyVCVY/IwRMLwCmbOte6iBdXxNsYFFuB1iyCAQmp9EeH5 k1FU2xAa9XETefa2JPpl4Gs1XO2MZmc4APKNx/o= X-Google-Smtp-Source: AGHT+IEog97UlMW0gZeFJ6RkV1S187RZItmbTzJGBNvKrCF1BkobQi2ljRKxomnaOMecRaOTPtJkaQ== X-Received: by 2002:a05:6870:ec90:b0:1e9:db34:a573 with SMTP id eo16-20020a056870ec9000b001e9db34a573mr600614oab.26.1697665920325; Wed, 18 Oct 2023 14:52:00 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH 28/61] target/hppa: Drop attempted gdbstub support for hppa64 Date: Wed, 18 Oct 2023 14:51:02 -0700 Message-Id: <20231018215135.1561375-29-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231018215135.1561375-1-richard.henderson@linaro.org> References: <20231018215135.1561375-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:4860:4864:20::29; envelope-from=richard.henderson@linaro.org; helo=mail-oa1-x29.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697666261339100003 Content-Type: text/plain; charset="utf-8" There is no support for hppa64 in gdb. Any attempt to provide the data for the larger hppa64 registers results in an error from gdb. Signed-off-by: Richard Henderson --- target/hppa/gdbstub.c | 26 +++++++++++--------------- 1 file changed, 11 insertions(+), 15 deletions(-) diff --git a/target/hppa/gdbstub.c b/target/hppa/gdbstub.c index 48a514384f..748431097c 100644 --- a/target/hppa/gdbstub.c +++ b/target/hppa/gdbstub.c @@ -21,11 +21,17 @@ #include "cpu.h" #include "gdbstub/helpers.h" =20 +/* + * GDB 15 only supports PA1.0 via the remote protocol, and ignores + * any provided xml. Which means that any attempt to provide more + * data results in "Remote 'g' packet reply is too long". + */ + int hppa_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) { HPPACPU *cpu =3D HPPA_CPU(cs); CPUHPPAState *env =3D &cpu->env; - target_ureg val; + uint32_t val; =20 switch (n) { case 0: @@ -139,24 +145,14 @@ int hppa_cpu_gdb_read_register(CPUState *cs, GByteArr= ay *mem_buf, int n) break; } =20 - if (TARGET_REGISTER_BITS =3D=3D 64) { - return gdb_get_reg64(mem_buf, val); - } else { - return gdb_get_reg32(mem_buf, val); - } + return gdb_get_reg32(mem_buf, val); } =20 int hppa_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) { HPPACPU *cpu =3D HPPA_CPU(cs); CPUHPPAState *env =3D &cpu->env; - target_ureg val; - - if (TARGET_REGISTER_BITS =3D=3D 64) { - val =3D ldq_p(mem_buf); - } else { - val =3D ldl_p(mem_buf); - } + uint32_t val =3D ldl_p(mem_buf); =20 switch (n) { case 0: @@ -166,7 +162,7 @@ int hppa_cpu_gdb_write_register(CPUState *cs, uint8_t *= mem_buf, int n) env->gr[n] =3D val; break; case 32: - env->cr[CR_SAR] =3D val; + env->cr[CR_SAR] =3D val & (cpu->is_pa20 ? 63 : 31); break; case 33: env->iaoq_f =3D val; @@ -278,5 +274,5 @@ int hppa_cpu_gdb_write_register(CPUState *cs, uint8_t *= mem_buf, int n) } break; } - return sizeof(target_ureg); + return 4; } --=20 2.34.1 From nobody Wed Nov 27 18:51:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1697666459; cv=none; d=zohomail.com; s=zohoarc; b=I/+o9yqQjXmNVuiheaZlGpr7MOVcdJHnocJTOjkXNcPnbEMsclv2jLOaYVi8gFwJS52HC44LRyjQAxQpCoR9jXh3KNBOxy9kVfKpxHl+JF9JqLOwunXQFB+E5o6B/rxjg186jZYNcmQnOou/aAALEq7j5t5A4gu21Mm/e1cCzVw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1697666459; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=HV5pYQwKSuXLoav6s1Qqsg8a/tXHn3qomGwcXH2ymT4=; b=CdVRS7v44hXFdA4Kgv3XaV9VLa3ItSL+7tB90AyJXXa3fWhLkNRTQqDWqWzdDECFD5hyQZokf+dXnKG+KIIRcvtq/ojiynowd8oZL8bGsGoSPRyC3o1hYSp5QBbKIpqwO38fpHMwz+OWwKj8jmGGDq277+1GM3CtXJ7bn+9w2ew= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1697666459615813.6816424816268; Wed, 18 Oct 2023 15:00:59 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qtESl-0001xf-2t; Wed, 18 Oct 2023 17:52:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qtEST-0001A0-4L for qemu-devel@nongnu.org; Wed, 18 Oct 2023 17:52:05 -0400 Received: from mail-oo1-xc31.google.com ([2607:f8b0:4864:20::c31]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qtESQ-0004S4-Hx for qemu-devel@nongnu.org; Wed, 18 Oct 2023 17:52:04 -0400 Received: by mail-oo1-xc31.google.com with SMTP id 006d021491bc7-57be3d8e738so4125076eaf.1 for ; Wed, 18 Oct 2023 14:52:02 -0700 (PDT) Received: from stoup.. ([71.212.149.95]) by smtp.gmail.com with ESMTPSA id w17-20020a63f511000000b005b61a024ec7sm2176380pgh.74.2023.10.18.14.52.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Oct 2023 14:52:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1697665921; x=1698270721; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=HV5pYQwKSuXLoav6s1Qqsg8a/tXHn3qomGwcXH2ymT4=; b=FXEbzw3/TunQaUY92D9mvMlzady8XDQYNijmU6HUESZ4IVUocOSxDNZQbY21VhN30Z ZFGeL1RTx95scBBv67dHpZVp+5LVtZUu6xQQSfAh8dzGsUsaStPSGEw9aP/dhsdJ50Hw ZCx9ZrweYLWy/t3kEQ5//zGn3lqv9v2k4meM41BJRHT9ImWEVrmkTkGygt7OwcazLGp0 wMbrr4oj+UlQwNJCbv6vC2Yc9gS/UpAjQeypC4oxjFIMbkG7xR+meUm2nlWrZkZO88o8 YUUWqWDZiRbdVNcoWt5AruLCCgke35lTSkVG6eBlBxoFlmDEaFGBnKGJmwJVD2gm7OmV GydA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697665921; x=1698270721; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=HV5pYQwKSuXLoav6s1Qqsg8a/tXHn3qomGwcXH2ymT4=; b=a20wjBagtUxpU4WhfnP9bYBYbzfg18/mGVOVsNDCwogbyX/G5tj5KO75LTiC2CeBlh wWa+gvxnchRGYrAW2CGJ6t/MsGanmxG7QNEI++oF8nSCTtdaJC/ucM2nu+6HRI5uQX2d YM/ZaCxAiXqmXwEjLmBLiDVIbg5eiUQAzu0yIXNAs/2G+B4Poj+wOdG+8XBYHDUqlGCz 3vTt7Dnt0ETJmGtsDW/rMl7qbS5z1y5DhHfG9LPqd+Xcxslnh/alnACzv6G/Vb2dq0YB PmBx9Sq0TR9xfYS9fDfBoiJLkjPf+auC2u/xeYpQZ/eqcn7E9oem9vhmWlxYWjLDNlpc zcUQ== X-Gm-Message-State: AOJu0Yzh0J5dGna5YahOCMUQ09iq0ZPboB0qhfEFELwlsSDuja+xPZP0 aJucSkr3waM8G4Z30If/7G1hnAxuvrBdnKIjh2o= X-Google-Smtp-Source: AGHT+IFoqNYlD6iI+Q1M7TtOh14x7QD58jjq/eYq7CdSblPu86iu0H3NdrQjyxFmS/jqJ1ED+fWvgA== X-Received: by 2002:a05:6358:c609:b0:142:d097:3725 with SMTP id fd9-20020a056358c60900b00142d0973725mr269953rwb.9.1697665921158; Wed, 18 Oct 2023 14:52:01 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH 29/61] target/hppa: Remove TARGET_HPPA64 Date: Wed, 18 Oct 2023 14:51:03 -0700 Message-Id: <20231018215135.1561375-30-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231018215135.1561375-1-richard.henderson@linaro.org> References: <20231018215135.1561375-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::c31; envelope-from=richard.henderson@linaro.org; helo=mail-oo1-xc31.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697666460798100002 Content-Type: text/plain; charset="utf-8" Allow both user-only and system mode to run pa2.0 cpus. Avoid creating a separate qemu-system-hppa64 binary; force the qemu-hppa binary to use TARGET_ABI32. Signed-off-by: Richard Henderson --- configs/targets/hppa-linux-user.mak | 1 + target/hppa/cpu-param.h | 23 +++++++---------------- target/hppa/cpu.h | 9 --------- target/hppa/cpu.c | 4 ---- target/hppa/translate.c | 2 -- 5 files changed, 8 insertions(+), 31 deletions(-) diff --git a/configs/targets/hppa-linux-user.mak b/configs/targets/hppa-lin= ux-user.mak index 361ea39d71..8e0a80492f 100644 --- a/configs/targets/hppa-linux-user.mak +++ b/configs/targets/hppa-linux-user.mak @@ -1,4 +1,5 @@ TARGET_ARCH=3Dhppa +TARGET_ABI32=3Dy TARGET_SYSTBL_ABI=3Dcommon,32 TARGET_SYSTBL=3Dsyscall.tbl TARGET_BIG_ENDIAN=3Dy diff --git a/target/hppa/cpu-param.h b/target/hppa/cpu-param.h index c2791ae5f2..2fb8e7924b 100644 --- a/target/hppa/cpu-param.h +++ b/target/hppa/cpu-param.h @@ -8,26 +8,17 @@ #ifndef HPPA_CPU_PARAM_H #define HPPA_CPU_PARAM_H =20 -#ifdef TARGET_HPPA64 -# define TARGET_LONG_BITS 64 -# define TARGET_REGISTER_BITS 64 -# define TARGET_VIRT_ADDR_SPACE_BITS 64 -# define TARGET_PHYS_ADDR_SPACE_BITS 64 -#elif defined(CONFIG_USER_ONLY) -# define TARGET_LONG_BITS 32 -# define TARGET_REGISTER_BITS 32 +#define TARGET_LONG_BITS 64 +#define TARGET_REGISTER_BITS 64 + +#if defined(CONFIG_USER_ONLY) && defined(TARGET_ABI32) +# define TARGET_PHYS_ADDR_SPACE_BITS 32 # define TARGET_VIRT_ADDR_SPACE_BITS 32 -# define TARGET_PHYS_ADDR_SPACE_BITS 32 #else -/* - * In order to form the GVA from space:offset, - * we need a 64-bit virtual address space. - */ -# define TARGET_LONG_BITS 64 -# define TARGET_REGISTER_BITS 32 +# define TARGET_PHYS_ADDR_SPACE_BITS 64 # define TARGET_VIRT_ADDR_SPACE_BITS 64 -# define TARGET_PHYS_ADDR_SPACE_BITS 32 #endif + #define TARGET_PAGE_BITS 12 =20 #endif diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 1a12b2a186..251f85444a 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -107,11 +107,7 @@ #define PSW_T 0x01000000 #define PSW_S 0x02000000 #define PSW_E 0x04000000 -#ifdef TARGET_HPPA64 #define PSW_W 0x08000000 /* PA2.0 only */ -#else -#define PSW_W 0 -#endif #define PSW_Z 0x40000000 /* PA1.x only */ #define PSW_Y 0x80000000 /* PA1.x only */ =20 @@ -124,13 +120,8 @@ #define PSW_SM_P PSW_P #define PSW_SM_Q PSW_Q /* Enable Interrupt State Collection */ #define PSW_SM_R PSW_R /* Enable Recover Counter Trap */ -#ifdef TARGET_HPPA64 #define PSW_SM_E 0x100 #define PSW_SM_W 0x200 /* PA2.0 only : Enable Wide Mode */ -#else -#define PSW_SM_E 0 -#define PSW_SM_W 0 -#endif =20 #define CR_RC 0 #define CR_PID1 8 diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 6bf415139f..bbb6080e2d 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -253,7 +253,6 @@ static const TypeInfo hppa_cpu_type_info =3D { .class_init =3D hppa_cpu_class_init, }; =20 -#ifdef TARGET_HPPA64 static void hppa64_cpu_initfn(Object *obj) { HPPACPU *cpu =3D HPPA_CPU(obj); @@ -265,14 +264,11 @@ static const TypeInfo hppa64_cpu_type_info =3D { .parent =3D TYPE_HPPA_CPU, .instance_init =3D hppa64_cpu_initfn, }; -#endif =20 static void hppa_cpu_register_types(void) { type_register_static(&hppa_cpu_type_info); -#ifdef TARGET_HPPA64 type_register_static(&hppa64_cpu_type_info); -#endif } =20 type_init(hppa_cpu_register_types) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 8bea28f0fd..94969cf2f0 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -2156,7 +2156,6 @@ static bool trans_mfctl(DisasContext *ctx, arg_mfctl = *a) =20 switch (ctl) { case CR_SAR: -#ifdef TARGET_HPPA64 if (a->e =3D=3D 0) { /* MFSAR without ,W masks low 5 bits. */ tmp =3D dest_gpr(ctx, rt); @@ -2164,7 +2163,6 @@ static bool trans_mfctl(DisasContext *ctx, arg_mfctl = *a) save_gpr(ctx, rt, tmp); goto done; } -#endif save_gpr(ctx, rt, cpu_sar); goto done; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::536; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x536.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697666386184100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/hppa/insns.decode | 10 ++++++---- target/hppa/translate.c | 15 +++++++-------- 2 files changed, 13 insertions(+), 12 deletions(-) diff --git a/target/hppa/insns.decode b/target/hppa/insns.decode index aebe03ccfd..26ca9f1063 100644 --- a/target/hppa/insns.decode +++ b/target/hppa/insns.decode @@ -61,6 +61,7 @@ =20 &rr_cf t r cf &rrr_cf t r1 r2 cf +&rrr_cf_d t r1 r2 cf d &rrr_cf_sh t r1 r2 cf sh &rri_cf t r i cf =20 @@ -73,6 +74,7 @@ =20 @rr_cf ...... r:5 ..... cf:4 ....... t:5 &rr_cf @rrr_cf ...... r2:5 r1:5 cf:4 ....... t:5 &rrr_cf +@rrr_cf_d ...... r2:5 r1:5 cf:4 ...... d:1 t:5 &rrr_cf_d @rrr_cf_sh ...... r2:5 r1:5 cf:4 .... sh:2 . t:5 &rrr_cf_sh @rrr_cf_sh0 ...... r2:5 r1:5 cf:4 ....... t:5 &rrr_cf_sh sh=3D0 @rri_cf ...... r:5 t:5 cf:4 . ........... &rri_cf i=3D%lowsi= gn_11 @@ -150,10 +152,10 @@ lci 000001 ----- ----- -- 01001100 0 t:5 # Arith/Log #### =20 -andcm 000010 ..... ..... .... 000000 - ..... @rrr_cf -and 000010 ..... ..... .... 001000 - ..... @rrr_cf -or 000010 ..... ..... .... 001001 - ..... @rrr_cf -xor 000010 ..... ..... .... 001010 0 ..... @rrr_cf +andcm 000010 ..... ..... .... 000000 . ..... @rrr_cf_d +and 000010 ..... ..... .... 001000 . ..... @rrr_cf_d +or 000010 ..... ..... .... 001001 . ..... @rrr_cf_d +xor 000010 ..... ..... .... 001010 . ..... @rrr_cf_d uxor 000010 ..... ..... .... 001110 0 ..... @rrr_cf ds 000010 ..... ..... .... 010001 0 ..... @rrr_cf cmpclr 000010 ..... ..... .... 100010 0 ..... @rrr_cf diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 94969cf2f0..5eecced442 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -1392,11 +1392,10 @@ static void do_cmpclr(DisasContext *ctx, unsigned r= t, TCGv_reg in1, } =20 static void do_log(DisasContext *ctx, unsigned rt, TCGv_reg in1, - TCGv_reg in2, unsigned cf, + TCGv_reg in2, unsigned cf, bool d, void (*fn)(TCGv_reg, TCGv_reg, TCGv_reg)) { TCGv_reg dest =3D dest_gpr(ctx, rt); - bool d =3D false; =20 /* Perform the operation, and writeback. */ fn(dest, in1, in2); @@ -1409,7 +1408,7 @@ static void do_log(DisasContext *ctx, unsigned rt, TC= Gv_reg in1, } } =20 -static bool do_log_reg(DisasContext *ctx, arg_rrr_cf *a, +static bool do_log_reg(DisasContext *ctx, arg_rrr_cf_d *a, void (*fn)(TCGv_reg, TCGv_reg, TCGv_reg)) { TCGv_reg tcg_r1, tcg_r2; @@ -1419,7 +1418,7 @@ static bool do_log_reg(DisasContext *ctx, arg_rrr_cf = *a, } tcg_r1 =3D load_gpr(ctx, a->r1); tcg_r2 =3D load_gpr(ctx, a->r2); - do_log(ctx, a->t, tcg_r1, tcg_r2, a->cf, fn); + do_log(ctx, a->t, tcg_r1, tcg_r2, a->cf, a->d, fn); return nullify_end(ctx); } =20 @@ -2672,17 +2671,17 @@ static bool trans_sub_b_tsv(DisasContext *ctx, arg_= rrr_cf *a) return do_sub_reg(ctx, a, true, true, false); } =20 -static bool trans_andcm(DisasContext *ctx, arg_rrr_cf *a) +static bool trans_andcm(DisasContext *ctx, arg_rrr_cf_d *a) { return do_log_reg(ctx, a, tcg_gen_andc_reg); } =20 -static bool trans_and(DisasContext *ctx, arg_rrr_cf *a) +static bool trans_and(DisasContext *ctx, arg_rrr_cf_d *a) { return do_log_reg(ctx, a, tcg_gen_and_reg); } =20 -static bool trans_or(DisasContext *ctx, arg_rrr_cf *a) +static bool trans_or(DisasContext *ctx, arg_rrr_cf_d *a) { if (a->cf =3D=3D 0) { unsigned r2 =3D a->r2; @@ -2734,7 +2733,7 @@ static bool trans_or(DisasContext *ctx, arg_rrr_cf *a) return do_log_reg(ctx, a, tcg_gen_or_reg); } =20 -static bool trans_xor(DisasContext *ctx, arg_rrr_cf *a) +static bool trans_xor(DisasContext *ctx, arg_rrr_cf_d *a) { return do_log_reg(ctx, a, tcg_gen_xor_reg); } --=20 2.34.1 From nobody Wed Nov 27 18:51:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1697666682; cv=none; d=zohomail.com; s=zohoarc; b=URGG9PHPdxHRgsrXLPWoJRgse4nUxROyPAr3oMuwmeHXhPZ5zOXs4kYinMo3UYJQkXYqoVhYDqgnCbkCXiPzDc/6llkVmgVhopHfKZaFURbLkAUR0iDTB8y7VAt22hlFoBNFRPWNUCeWI/3NZJF/oE3AHnxLBgO5+3zWFSz2B6k= ARC-Message-Signature: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:4860:4864:20::36; envelope-from=richard.henderson@linaro.org; helo=mail-oa1-x36.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697666683482100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/hppa/insns.decode | 14 +++++++------- target/hppa/translate.c | 25 ++++++++++++------------- 2 files changed, 19 insertions(+), 20 deletions(-) diff --git a/target/hppa/insns.decode b/target/hppa/insns.decode index 26ca9f1063..03b1a11cac 100644 --- a/target/hppa/insns.decode +++ b/target/hppa/insns.decode @@ -59,7 +59,7 @@ # All insns that need to form a virtual address should use this set. &ldst t b x disp sp m scale size =20 -&rr_cf t r cf +&rr_cf_d t r cf d &rrr_cf t r1 r2 cf &rrr_cf_d t r1 r2 cf d &rrr_cf_sh t r1 r2 cf sh @@ -72,7 +72,7 @@ # Format definitions #### =20 -@rr_cf ...... r:5 ..... cf:4 ....... t:5 &rr_cf +@rr_cf_d ...... r:5 ..... cf:4 ...... d:1 t:5 &rr_cf_d @rrr_cf ...... r2:5 r1:5 cf:4 ....... t:5 &rrr_cf @rrr_cf_d ...... r2:5 r1:5 cf:4 ...... d:1 t:5 &rrr_cf_d @rrr_cf_sh ...... r2:5 r1:5 cf:4 .... sh:2 . t:5 &rrr_cf_sh @@ -156,13 +156,13 @@ andcm 000010 ..... ..... .... 000000 . ....= . @rrr_cf_d and 000010 ..... ..... .... 001000 . ..... @rrr_cf_d or 000010 ..... ..... .... 001001 . ..... @rrr_cf_d xor 000010 ..... ..... .... 001010 . ..... @rrr_cf_d -uxor 000010 ..... ..... .... 001110 0 ..... @rrr_cf +uxor 000010 ..... ..... .... 001110 . ..... @rrr_cf_d ds 000010 ..... ..... .... 010001 0 ..... @rrr_cf cmpclr 000010 ..... ..... .... 100010 0 ..... @rrr_cf -uaddcm 000010 ..... ..... .... 100110 0 ..... @rrr_cf -uaddcm_tc 000010 ..... ..... .... 100111 0 ..... @rrr_cf -dcor 000010 ..... 00000 .... 101110 0 ..... @rr_cf -dcor_i 000010 ..... 00000 .... 101111 0 ..... @rr_cf +uaddcm 000010 ..... ..... .... 100110 . ..... @rrr_cf_d +uaddcm_tc 000010 ..... ..... .... 100111 . ..... @rrr_cf_d +dcor 000010 ..... 00000 .... 101110 . ..... @rr_cf_d +dcor_i 000010 ..... 00000 .... 101111 . ..... @rr_cf_d =20 add 000010 ..... ..... .... 0110.. - ..... @rrr_cf_sh add_l 000010 ..... ..... .... 1010.. 0 ..... @rrr_cf_sh diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 5eecced442..ed00b58fbc 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -1423,12 +1423,11 @@ static bool do_log_reg(DisasContext *ctx, arg_rrr_c= f_d *a, } =20 static void do_unit(DisasContext *ctx, unsigned rt, TCGv_reg in1, - TCGv_reg in2, unsigned cf, bool is_tc, + TCGv_reg in2, unsigned cf, bool d, bool is_tc, void (*fn)(TCGv_reg, TCGv_reg, TCGv_reg)) { TCGv_reg dest; DisasCond cond; - bool d =3D false; =20 if (cf =3D=3D 0) { dest =3D dest_gpr(ctx, rt); @@ -2751,7 +2750,7 @@ static bool trans_cmpclr(DisasContext *ctx, arg_rrr_c= f *a) return nullify_end(ctx); } =20 -static bool trans_uxor(DisasContext *ctx, arg_rrr_cf *a) +static bool trans_uxor(DisasContext *ctx, arg_rrr_cf_d *a) { TCGv_reg tcg_r1, tcg_r2; =20 @@ -2760,11 +2759,11 @@ static bool trans_uxor(DisasContext *ctx, arg_rrr_c= f *a) } tcg_r1 =3D load_gpr(ctx, a->r1); tcg_r2 =3D load_gpr(ctx, a->r2); - do_unit(ctx, a->t, tcg_r1, tcg_r2, a->cf, false, tcg_gen_xor_reg); + do_unit(ctx, a->t, tcg_r1, tcg_r2, a->cf, a->d, false, tcg_gen_xor_reg= ); return nullify_end(ctx); } =20 -static bool do_uaddcm(DisasContext *ctx, arg_rrr_cf *a, bool is_tc) +static bool do_uaddcm(DisasContext *ctx, arg_rrr_cf_d *a, bool is_tc) { TCGv_reg tcg_r1, tcg_r2, tmp; =20 @@ -2775,21 +2774,21 @@ static bool do_uaddcm(DisasContext *ctx, arg_rrr_cf= *a, bool is_tc) tcg_r2 =3D load_gpr(ctx, a->r2); tmp =3D tcg_temp_new(); tcg_gen_not_reg(tmp, tcg_r2); - do_unit(ctx, a->t, tcg_r1, tmp, a->cf, is_tc, tcg_gen_add_reg); + do_unit(ctx, a->t, tcg_r1, tmp, a->cf, a->d, is_tc, tcg_gen_add_reg); return nullify_end(ctx); } =20 -static bool trans_uaddcm(DisasContext *ctx, arg_rrr_cf *a) +static bool trans_uaddcm(DisasContext *ctx, arg_rrr_cf_d *a) { return do_uaddcm(ctx, a, false); } =20 -static bool trans_uaddcm_tc(DisasContext *ctx, arg_rrr_cf *a) +static bool trans_uaddcm_tc(DisasContext *ctx, arg_rrr_cf_d *a) { return do_uaddcm(ctx, a, true); } =20 -static bool do_dcor(DisasContext *ctx, arg_rr_cf *a, bool is_i) +static bool do_dcor(DisasContext *ctx, arg_rr_cf_d *a, bool is_i) { TCGv_reg tmp; =20 @@ -2800,19 +2799,19 @@ static bool do_dcor(DisasContext *ctx, arg_rr_cf *a= , bool is_i) if (!is_i) { tcg_gen_not_reg(tmp, tmp); } - tcg_gen_andi_reg(tmp, tmp, 0x11111111); + tcg_gen_andi_reg(tmp, tmp, (target_ureg)0x1111111111111111ull); tcg_gen_muli_reg(tmp, tmp, 6); - do_unit(ctx, a->t, load_gpr(ctx, a->r), tmp, a->cf, false, + do_unit(ctx, a->t, load_gpr(ctx, a->r), tmp, a->cf, a->d, false, is_i ? tcg_gen_add_reg : tcg_gen_sub_reg); return nullify_end(ctx); } =20 -static bool trans_dcor(DisasContext *ctx, arg_rr_cf *a) +static bool trans_dcor(DisasContext *ctx, arg_rr_cf_d *a) { return do_dcor(ctx, a, false); } =20 -static bool trans_dcor_i(DisasContext *ctx, arg_rr_cf *a) +static bool trans_dcor_i(DisasContext *ctx, arg_rr_cf_d *a) { return do_dcor(ctx, a, true); } --=20 2.34.1 From nobody Wed Nov 27 18:51:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1697666323; cv=none; d=zohomail.com; s=zohoarc; b=Vc4bLtPsBay8Adx2z1BAtGAacARE4Vkwh+6nkzwN9Vwm8ozcNMDzmuA4vJrripmXoCZgj4JW0s3TE/9vBkWgwsDJReHrbzGWt4OLaB3jjy3UzZovmP2cRXTjvpd1wY4zrubiqxFTHGkSkipZLJjK8W+T+M/kKXULpnEsyNEcKpQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::233; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x233.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697666324080100005 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/hppa/insns.decode | 6 ++++-- target/hppa/translate.c | 11 +++++------ 2 files changed, 9 insertions(+), 8 deletions(-) diff --git a/target/hppa/insns.decode b/target/hppa/insns.decode index 03b1a11cac..d4a03b0299 100644 --- a/target/hppa/insns.decode +++ b/target/hppa/insns.decode @@ -64,6 +64,7 @@ &rrr_cf_d t r1 r2 cf d &rrr_cf_sh t r1 r2 cf sh &rri_cf t r i cf +&rri_cf_d t r i cf d =20 &rrb_c_f disp n c f r1 r2 &rib_c_f disp n c f r i @@ -78,6 +79,7 @@ @rrr_cf_sh ...... r2:5 r1:5 cf:4 .... sh:2 . t:5 &rrr_cf_sh @rrr_cf_sh0 ...... r2:5 r1:5 cf:4 ....... t:5 &rrr_cf_sh sh=3D0 @rri_cf ...... r:5 t:5 cf:4 . ........... &rri_cf i=3D%lowsi= gn_11 +@rri_cf_d ...... r:5 t:5 cf:4 d:1 ........... &rri_cf_d i=3D%low= sign_11 =20 @rrb_cf ...... r2:5 r1:5 c:3 ........... n:1 . \ &rrb_c_f disp=3D%assemble_12 @@ -158,7 +160,7 @@ or 000010 ..... ..... .... 001001 . ..... = @rrr_cf_d xor 000010 ..... ..... .... 001010 . ..... @rrr_cf_d uxor 000010 ..... ..... .... 001110 . ..... @rrr_cf_d ds 000010 ..... ..... .... 010001 0 ..... @rrr_cf -cmpclr 000010 ..... ..... .... 100010 0 ..... @rrr_cf +cmpclr 000010 ..... ..... .... 100010 . ..... @rrr_cf_d uaddcm 000010 ..... ..... .... 100110 . ..... @rrr_cf_d uaddcm_tc 000010 ..... ..... .... 100111 . ..... @rrr_cf_d dcor 000010 ..... 00000 .... 101110 . ..... @rr_cf_d @@ -189,7 +191,7 @@ addi_tc_tsv 101100 ..... ..... .... 1 ........... = @rri_cf subi 100101 ..... ..... .... 0 ........... @rri_cf subi_tsv 100101 ..... ..... .... 1 ........... @rri_cf =20 -cmpiclr 100100 ..... ..... .... 0 ........... @rri_cf +cmpiclr 100100 ..... ..... .... . ........... @rri_cf_d =20 #### # Index Mem diff --git a/target/hppa/translate.c b/target/hppa/translate.c index ed00b58fbc..58d69cb748 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -1364,11 +1364,10 @@ static bool do_sub_imm(DisasContext *ctx, arg_rri_c= f *a, bool is_tsv) } =20 static void do_cmpclr(DisasContext *ctx, unsigned rt, TCGv_reg in1, - TCGv_reg in2, unsigned cf) + TCGv_reg in2, unsigned cf, bool d) { TCGv_reg dest, sv; DisasCond cond; - bool d =3D false; =20 dest =3D tcg_temp_new(); tcg_gen_sub_reg(dest, in1, in2); @@ -2737,7 +2736,7 @@ static bool trans_xor(DisasContext *ctx, arg_rrr_cf_d= *a) return do_log_reg(ctx, a, tcg_gen_xor_reg); } =20 -static bool trans_cmpclr(DisasContext *ctx, arg_rrr_cf *a) +static bool trans_cmpclr(DisasContext *ctx, arg_rrr_cf_d *a) { TCGv_reg tcg_r1, tcg_r2; =20 @@ -2746,7 +2745,7 @@ static bool trans_cmpclr(DisasContext *ctx, arg_rrr_c= f *a) } tcg_r1 =3D load_gpr(ctx, a->r1); tcg_r2 =3D load_gpr(ctx, a->r2); - do_cmpclr(ctx, a->t, tcg_r1, tcg_r2, a->cf); + do_cmpclr(ctx, a->t, tcg_r1, tcg_r2, a->cf, a->d); return nullify_end(ctx); } =20 @@ -2904,7 +2903,7 @@ static bool trans_subi_tsv(DisasContext *ctx, arg_rri= _cf *a) return do_sub_imm(ctx, a, true); } =20 -static bool trans_cmpiclr(DisasContext *ctx, arg_rri_cf *a) +static bool trans_cmpiclr(DisasContext *ctx, arg_rri_cf_d *a) { TCGv_reg tcg_im, tcg_r2; =20 @@ -2914,7 +2913,7 @@ static bool trans_cmpiclr(DisasContext *ctx, arg_rri_= cf *a) =20 tcg_im =3D tcg_constant_reg(a->i); tcg_r2 =3D load_gpr(ctx, a->r); - do_cmpclr(ctx, a->t, tcg_im, tcg_r2, a->cf); + do_cmpclr(ctx, a->t, tcg_im, tcg_r2, a->cf, a->d); =20 return nullify_end(ctx); } --=20 2.34.1 From nobody Wed Nov 27 18:51:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1697666459; cv=none; d=zohomail.com; s=zohoarc; b=AIzmMLnl5jQNJ4cdOrLtcjlOiFisINU4QsZCJEJtUjoF45bFjywkFSjIIQtX0nYGBrv6a6J2dlcTBEcUPCZNO8pcLDgQ+a8jYAsRGB5Pi+FHy17wjj4o/D5Z82EL6aAKH4HdHko3j0drmQOtMsHg/PaPRpxZQzKbYIg5LZP2JjI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1697666459; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::132; envelope-from=richard.henderson@linaro.org; helo=mail-il1-x132.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697666460763100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/hppa/insns.decode | 16 ++++++++-------- target/hppa/translate.c | 21 +++++++++++---------- 2 files changed, 19 insertions(+), 18 deletions(-) diff --git a/target/hppa/insns.decode b/target/hppa/insns.decode index d4a03b0299..0f29869949 100644 --- a/target/hppa/insns.decode +++ b/target/hppa/insns.decode @@ -62,7 +62,7 @@ &rr_cf_d t r cf d &rrr_cf t r1 r2 cf &rrr_cf_d t r1 r2 cf d -&rrr_cf_sh t r1 r2 cf sh +&rrr_cf_d_sh t r1 r2 cf d sh &rri_cf t r i cf &rri_cf_d t r i cf d =20 @@ -76,8 +76,8 @@ @rr_cf_d ...... r:5 ..... cf:4 ...... d:1 t:5 &rr_cf_d @rrr_cf ...... r2:5 r1:5 cf:4 ....... t:5 &rrr_cf @rrr_cf_d ...... r2:5 r1:5 cf:4 ...... d:1 t:5 &rrr_cf_d -@rrr_cf_sh ...... r2:5 r1:5 cf:4 .... sh:2 . t:5 &rrr_cf_sh -@rrr_cf_sh0 ...... r2:5 r1:5 cf:4 ....... t:5 &rrr_cf_sh sh=3D0 +@rrr_cf_d_sh ...... r2:5 r1:5 cf:4 .... sh:2 d:1 t:5 &rrr_cf_d_sh +@rrr_cf_d_sh0 ...... r2:5 r1:5 cf:4 ...... d:1 t:5 &rrr_cf_d_sh sh=3D0 @rri_cf ...... r:5 t:5 cf:4 . ........... &rri_cf i=3D%lowsi= gn_11 @rri_cf_d ...... r:5 t:5 cf:4 d:1 ........... &rri_cf_d i=3D%low= sign_11 =20 @@ -166,11 +166,11 @@ uaddcm_tc 000010 ..... ..... .... 100111 . ....= . @rrr_cf_d dcor 000010 ..... 00000 .... 101110 . ..... @rr_cf_d dcor_i 000010 ..... 00000 .... 101111 . ..... @rr_cf_d =20 -add 000010 ..... ..... .... 0110.. - ..... @rrr_cf_sh -add_l 000010 ..... ..... .... 1010.. 0 ..... @rrr_cf_sh -add_tsv 000010 ..... ..... .... 1110.. 0 ..... @rrr_cf_sh -add_c 000010 ..... ..... .... 011100 0 ..... @rrr_cf_sh0 -add_c_tsv 000010 ..... ..... .... 111100 0 ..... @rrr_cf_sh0 +add 000010 ..... ..... .... 0110.. . ..... @rrr_cf_d_sh +add_l 000010 ..... ..... .... 1010.. . ..... @rrr_cf_d_sh +add_tsv 000010 ..... ..... .... 1110.. . ..... @rrr_cf_d_sh +add_c 000010 ..... ..... .... 011100 . ..... @rrr_cf_d_sh0 +add_c_tsv 000010 ..... ..... .... 111100 . ..... @rrr_cf_d_sh0 =20 sub 000010 ..... ..... .... 010000 - ..... @rrr_cf sub_tsv 000010 ..... ..... .... 110000 0 ..... @rrr_cf diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 58d69cb748..1bf61628d1 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -1173,12 +1173,11 @@ static TCGv_reg do_sub_sv(DisasContext *ctx, TCGv_r= eg res, =20 static void do_add(DisasContext *ctx, unsigned rt, TCGv_reg in1, TCGv_reg in2, unsigned shift, bool is_l, - bool is_tsv, bool is_tc, bool is_c, unsigned cf) + bool is_tsv, bool is_tc, bool is_c, unsigned cf, bool d) { TCGv_reg dest, cb, cb_msb, cb_cond, sv, tmp; unsigned c =3D cf >> 1; DisasCond cond; - bool d =3D false; =20 dest =3D tcg_temp_new(); cb =3D NULL; @@ -1243,7 +1242,7 @@ static void do_add(DisasContext *ctx, unsigned rt, TC= Gv_reg in1, ctx->null_cond =3D cond; } =20 -static bool do_add_reg(DisasContext *ctx, arg_rrr_cf_sh *a, +static bool do_add_reg(DisasContext *ctx, arg_rrr_cf_d_sh *a, bool is_l, bool is_tsv, bool is_tc, bool is_c) { TCGv_reg tcg_r1, tcg_r2; @@ -1253,7 +1252,8 @@ static bool do_add_reg(DisasContext *ctx, arg_rrr_cf_= sh *a, } tcg_r1 =3D load_gpr(ctx, a->r1); tcg_r2 =3D load_gpr(ctx, a->r2); - do_add(ctx, a->t, tcg_r1, tcg_r2, a->sh, is_l, is_tsv, is_tc, is_c, a-= >cf); + do_add(ctx, a->t, tcg_r1, tcg_r2, a->sh, is_l, + is_tsv, is_tc, is_c, a->cf, a->d); return nullify_end(ctx); } =20 @@ -1267,7 +1267,8 @@ static bool do_add_imm(DisasContext *ctx, arg_rri_cf = *a, } tcg_im =3D tcg_constant_reg(a->i); tcg_r2 =3D load_gpr(ctx, a->r); - do_add(ctx, a->t, tcg_im, tcg_r2, 0, 0, is_tsv, is_tc, 0, a->cf); + /* All ADDI conditions are 32-bit. */ + do_add(ctx, a->t, tcg_im, tcg_r2, 0, 0, is_tsv, is_tc, 0, a->cf, false= ); return nullify_end(ctx); } =20 @@ -2614,27 +2615,27 @@ static bool trans_lci(DisasContext *ctx, arg_lci *a) return true; } =20 -static bool trans_add(DisasContext *ctx, arg_rrr_cf_sh *a) +static bool trans_add(DisasContext *ctx, arg_rrr_cf_d_sh *a) { return do_add_reg(ctx, a, false, false, false, false); } =20 -static bool trans_add_l(DisasContext *ctx, arg_rrr_cf_sh *a) +static bool trans_add_l(DisasContext *ctx, arg_rrr_cf_d_sh *a) { return do_add_reg(ctx, a, true, false, false, false); } =20 -static bool trans_add_tsv(DisasContext *ctx, arg_rrr_cf_sh *a) +static bool trans_add_tsv(DisasContext *ctx, arg_rrr_cf_d_sh *a) { return do_add_reg(ctx, a, false, true, false, false); } =20 -static bool trans_add_c(DisasContext *ctx, arg_rrr_cf_sh *a) +static bool trans_add_c(DisasContext *ctx, arg_rrr_cf_d_sh *a) { return do_add_reg(ctx, a, false, false, false, true); } =20 -static bool trans_add_c_tsv(DisasContext *ctx, arg_rrr_cf_sh *a) +static bool trans_add_c_tsv(DisasContext *ctx, arg_rrr_cf_d_sh *a) { return do_add_reg(ctx, a, false, true, false, true); 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::c2d; envelope-from=richard.henderson@linaro.org; helo=mail-oo1-xc2d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697666556971100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/hppa/insns.decode | 12 ++++++------ target/hppa/translate.c | 22 +++++++++++----------- 2 files changed, 17 insertions(+), 17 deletions(-) diff --git a/target/hppa/insns.decode b/target/hppa/insns.decode index 0f29869949..ad454adcbb 100644 --- a/target/hppa/insns.decode +++ b/target/hppa/insns.decode @@ -172,12 +172,12 @@ add_tsv 000010 ..... ..... .... 1110.. . ....= . @rrr_cf_d_sh add_c 000010 ..... ..... .... 011100 . ..... @rrr_cf_d_sh0 add_c_tsv 000010 ..... ..... .... 111100 . ..... @rrr_cf_d_sh0 =20 -sub 000010 ..... ..... .... 010000 - ..... @rrr_cf -sub_tsv 000010 ..... ..... .... 110000 0 ..... @rrr_cf -sub_tc 000010 ..... ..... .... 010011 0 ..... @rrr_cf -sub_tsv_tc 000010 ..... ..... .... 110011 0 ..... @rrr_cf -sub_b 000010 ..... ..... .... 010100 0 ..... @rrr_cf -sub_b_tsv 000010 ..... ..... .... 110100 0 ..... @rrr_cf +sub 000010 ..... ..... .... 010000 . ..... @rrr_cf_d +sub_tsv 000010 ..... ..... .... 110000 . ..... @rrr_cf_d +sub_tc 000010 ..... ..... .... 010011 . ..... @rrr_cf_d +sub_tsv_tc 000010 ..... ..... .... 110011 . ..... @rrr_cf_d +sub_b 000010 ..... ..... .... 010100 . ..... @rrr_cf_d +sub_b_tsv 000010 ..... ..... .... 110100 . ..... @rrr_cf_d =20 ldil 001000 t:5 ..................... i=3D%assemble_21 addil 001010 r:5 ..................... i=3D%assemble_21 diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 1bf61628d1..e21a206466 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -1274,12 +1274,11 @@ static bool do_add_imm(DisasContext *ctx, arg_rri_c= f *a, =20 static void do_sub(DisasContext *ctx, unsigned rt, TCGv_reg in1, TCGv_reg in2, bool is_tsv, bool is_b, - bool is_tc, unsigned cf) + bool is_tc, unsigned cf, bool d) { TCGv_reg dest, sv, cb, cb_msb, zero, tmp; unsigned c =3D cf >> 1; DisasCond cond; - bool d =3D false; =20 dest =3D tcg_temp_new(); cb =3D tcg_temp_new(); @@ -1337,7 +1336,7 @@ static void do_sub(DisasContext *ctx, unsigned rt, TC= Gv_reg in1, ctx->null_cond =3D cond; } =20 -static bool do_sub_reg(DisasContext *ctx, arg_rrr_cf *a, +static bool do_sub_reg(DisasContext *ctx, arg_rrr_cf_d *a, bool is_tsv, bool is_b, bool is_tc) { TCGv_reg tcg_r1, tcg_r2; @@ -1347,7 +1346,7 @@ static bool do_sub_reg(DisasContext *ctx, arg_rrr_cf = *a, } tcg_r1 =3D load_gpr(ctx, a->r1); tcg_r2 =3D load_gpr(ctx, a->r2); - do_sub(ctx, a->t, tcg_r1, tcg_r2, is_tsv, is_b, is_tc, a->cf); + do_sub(ctx, a->t, tcg_r1, tcg_r2, is_tsv, is_b, is_tc, a->cf, a->d); return nullify_end(ctx); } =20 @@ -1360,7 +1359,8 @@ static bool do_sub_imm(DisasContext *ctx, arg_rri_cf = *a, bool is_tsv) } tcg_im =3D tcg_constant_reg(a->i); tcg_r2 =3D load_gpr(ctx, a->r); - do_sub(ctx, a->t, tcg_im, tcg_r2, is_tsv, 0, 0, a->cf); + /* All SUBI conditions are 32-bit. */ + do_sub(ctx, a->t, tcg_im, tcg_r2, is_tsv, 0, 0, a->cf, false); return nullify_end(ctx); } =20 @@ -2640,32 +2640,32 @@ static bool trans_add_c_tsv(DisasContext *ctx, arg_= rrr_cf_d_sh *a) return do_add_reg(ctx, a, false, true, false, true); } =20 -static bool trans_sub(DisasContext *ctx, arg_rrr_cf *a) +static bool trans_sub(DisasContext *ctx, arg_rrr_cf_d *a) { return do_sub_reg(ctx, a, false, false, false); } =20 -static bool trans_sub_tsv(DisasContext *ctx, arg_rrr_cf *a) +static bool trans_sub_tsv(DisasContext *ctx, arg_rrr_cf_d *a) { return do_sub_reg(ctx, a, true, false, false); } =20 -static bool trans_sub_tc(DisasContext *ctx, arg_rrr_cf *a) +static bool trans_sub_tc(DisasContext *ctx, arg_rrr_cf_d *a) { return do_sub_reg(ctx, a, false, false, true); } =20 -static bool trans_sub_tsv_tc(DisasContext *ctx, arg_rrr_cf *a) +static bool trans_sub_tsv_tc(DisasContext *ctx, arg_rrr_cf_d *a) { return do_sub_reg(ctx, a, true, false, true); } =20 -static bool trans_sub_b(DisasContext *ctx, arg_rrr_cf *a) +static bool trans_sub_b(DisasContext *ctx, arg_rrr_cf_d *a) { return do_sub_reg(ctx, a, false, true, false); } =20 -static bool trans_sub_b_tsv(DisasContext *ctx, arg_rrr_cf *a) +static bool trans_sub_b_tsv(DisasContext *ctx, arg_rrr_cf_d *a) { return do_sub_reg(ctx, a, true, true, false); } --=20 2.34.1 From nobody Wed Nov 27 18:51:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1697666743; cv=none; d=zohomail.com; s=zohoarc; b=ZA7aEV7JY9gfglf4SeVJyYg/oOYT1ZLriDD+PCwg3QmBS9UXJ/Z8gDDZ5XeSFof56Alvc9pnWPTOb9MUpe6IZ1JNxtdoSnpLYAnKs7qhb1uIhZ5acFXiW5kCJ8CGK3lIwPryPevrVsSEtsiLfb03jJHw5u5NY+h9tVr4TWx7rvw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1697666743; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id w17-20020a63f511000000b005b61a024ec7sm2176380pgh.74.2023.10.18.14.52.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Oct 2023 14:52:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1697665926; x=1698270726; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Q6n7GVKKY6z8LBEya5tH0c0VXc67EOQvAcHfVl9Ri+0=; b=iL8rtsQOtwHTiulIopu522qZPTVu79DyJsy1UTpX7XSeR3JuUVNpsqmP10bxsRJEuh g2tA5SY4Dqu9B1GoGe1fxELhVGby4VLRHRZtQwpFOu2ECrA4Qsg47t/I3PSQ/0Zp4McF Bz7hwxmK0AzBXWGeqPY0M5ownq0Rv4fuQt/brtNNZp6BCFmDvbT3iXfGCkBbiy4HizPz uqXesec1pyyOTET0dtY460mHNmHfCKd2bd1QueEUFPBK+IVb2ruy+HOTxKnqQlKfynQI A5zoMKdNm/EoWMFEDewykhpdfMyJwm0W4hpDNBBDy7PiWnj6GHzwyxon6+9PobdanC/i WH9Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697665926; x=1698270726; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Q6n7GVKKY6z8LBEya5tH0c0VXc67EOQvAcHfVl9Ri+0=; b=liUZus9Mz548CZ57qXintR1PgiU9Y6wjVRPkc8Fiko7OyVuA2ky/3SH8yXM1X1WJys PoUtRKYvCFK76Ix6dm8cumDcLK6ubm+X2CkZlrVWlYT4Pvl9AmeKtWXD6yKYy1b9Lmnx RjHOiT+ejFKvVcBD9gWAqlIfuVpRgNqrnILqcZq5pZ05VuTyqE1g6d2HY4W7F4iptsM0 TbVfpNPWP6eXkekYporCs/JreSEse9asGbCssMMvdUG6XZ/BAaXJ27JuHi+yVhanAy9b 2nSSZ9V4IPYI3sJGB+10Mbl8FXQmi1nrat2NtlyNYf1hr9bND0pgpd1jDcMe4AAaV5kV Zqvg== X-Gm-Message-State: AOJu0Yx99OLAw+b8bDZbue5aalXvDJPeH4aGvn7Hsymvu5GZUMOX79X9 /PcoeC7pjPgkIv9H8/PCKB1qepSEk9y6OcS+yO8= X-Google-Smtp-Source: AGHT+IHkHSvxNT+6XrrN85o41UfZfbh2uNkNK6wzjI/BvUsiMwemfwq5uKTqrkn6CwU9HdjR+d8Cyg== X-Received: by 2002:a05:6a20:3d8b:b0:158:1387:6a95 with SMTP id s11-20020a056a203d8b00b0015813876a95mr454354pzi.19.1697665925737; Wed, 18 Oct 2023 14:52:05 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH 35/61] target/hppa: Decode d for bb instructions Date: Wed, 18 Oct 2023 14:51:09 -0700 Message-Id: <20231018215135.1561375-36-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231018215135.1561375-1-richard.henderson@linaro.org> References: <20231018215135.1561375-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::429; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697666743715100001 Content-Type: text/plain; charset="utf-8" Manipulate the shift count so that the bit to be tested is always placed at the MSB. Signed-off-by: Richard Henderson --- target/hppa/insns.decode | 4 ++-- target/hppa/translate.c | 6 ++---- 2 files changed, 4 insertions(+), 6 deletions(-) diff --git a/target/hppa/insns.decode b/target/hppa/insns.decode index ad454adcbb..b185523021 100644 --- a/target/hppa/insns.decode +++ b/target/hppa/insns.decode @@ -290,8 +290,8 @@ fmpysub_d 100110 ..... ..... ..... ..... 1 ..... = @mpyadd # Conditional Branches #### =20 -bb_sar 110000 00000 r:5 c:1 10 ........... n:1 . disp=3D%assembl= e_12 -bb_imm 110001 p:5 r:5 c:1 10 ........... n:1 . disp=3D%assembl= e_12 +bb_sar 110000 00000 r:5 c:1 1 d:1 ........... n:1 . disp=3D%assem= ble_12 +bb_imm 110001 p:5 r:5 c:1 1 d:1 ........... n:1 . disp=3D%assem= ble_12 =20 movb 110010 ..... ..... ... ........... . . @rrb_cf f=3D0 movbi 110011 ..... ..... ... ........... . . @rib_cf f=3D0 diff --git a/target/hppa/translate.c b/target/hppa/translate.c index e21a206466..33da82b7c8 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -3151,13 +3151,12 @@ static bool trans_bb_sar(DisasContext *ctx, arg_bb_= sar *a) { TCGv_reg tmp, tcg_r; DisasCond cond; - bool d =3D false; =20 nullify_over(ctx); =20 tmp =3D tcg_temp_new(); tcg_r =3D load_gpr(ctx, a->r); - if (cond_need_ext(ctx, d)) { + if (cond_need_ext(ctx, a->d)) { /* Force shift into [32,63] */ tcg_gen_ori_reg(tmp, cpu_sar, 32); tcg_gen_shl_reg(tmp, tcg_r, tmp); @@ -3173,14 +3172,13 @@ static bool trans_bb_imm(DisasContext *ctx, arg_bb_= imm *a) { TCGv_reg tmp, tcg_r; DisasCond cond; - bool d =3D false; int p; =20 nullify_over(ctx); =20 tmp =3D tcg_temp_new(); tcg_r =3D load_gpr(ctx, a->r); - p =3D a->p | (cond_need_ext(ctx, d) ? 32 : 0); + p =3D a->p | (cond_need_ext(ctx, a->d) ? 32 : 0); tcg_gen_shli_reg(tmp, tcg_r, p); =20 cond =3D cond_make_0(a->c ? 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::330; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697666378210100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/hppa/insns.decode | 9 +++++++-- target/hppa/translate.c | 12 ++++++++---- 2 files changed, 15 insertions(+), 6 deletions(-) diff --git a/target/hppa/insns.decode b/target/hppa/insns.decode index b185523021..fc327e2bb3 100644 --- a/target/hppa/insns.decode +++ b/target/hppa/insns.decode @@ -67,6 +67,7 @@ &rri_cf_d t r i cf d =20 &rrb_c_f disp n c f r1 r2 +&rrb_c_d_f disp n c d f r1 r2 &rib_c_f disp n c f r i =20 #### @@ -83,6 +84,8 @@ =20 @rrb_cf ...... r2:5 r1:5 c:3 ........... n:1 . \ &rrb_c_f disp=3D%assemble_12 +@rrb_cdf ...... r2:5 r1:5 c:3 ........... n:1 . \ + &rrb_c_d_f disp=3D%assemble_12 @rib_cf ...... r:5 ..... c:3 ........... n:1 . \ &rib_c_f disp=3D%assemble_12 i=3D%im5_16 =20 @@ -296,8 +299,10 @@ bb_imm 110001 p:5 r:5 c:1 1 d:1 ...........= n:1 . disp=3D%assemble_12 movb 110010 ..... ..... ... ........... . . @rrb_cf f=3D0 movbi 110011 ..... ..... ... ........... . . @rib_cf f=3D0 =20 -cmpb 100000 ..... ..... ... ........... . . @rrb_cf f=3D0 -cmpb 100010 ..... ..... ... ........... . . @rrb_cf f=3D1 +cmpb 100000 ..... ..... ... ........... . . @rrb_cdf d=3D0 f= =3D0 +cmpb 100010 ..... ..... ... ........... . . @rrb_cdf d=3D0 f= =3D1 +cmpb 100111 ..... ..... ... ........... . . @rrb_cdf d=3D1 f= =3D0 +cmpb 101111 ..... ..... ... ........... . . @rrb_cdf d=3D1 f= =3D1 cmpbi 100001 ..... ..... ... ........... . . @rib_cf f=3D0 cmpbi 100011 ..... ..... ... ........... . . @rib_cf f=3D1 =20 diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 33da82b7c8..681c955125 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -3070,11 +3070,10 @@ static bool trans_ldo(DisasContext *ctx, arg_ldo *a) } =20 static bool do_cmpb(DisasContext *ctx, unsigned r, TCGv_reg in1, - unsigned c, unsigned f, unsigned n, int disp) + unsigned c, unsigned f, bool d, unsigned n, int disp) { TCGv_reg dest, in2, sv; DisasCond cond; - bool d =3D false; =20 in2 =3D load_gpr(ctx, r); dest =3D tcg_temp_new(); @@ -3092,14 +3091,19 @@ static bool do_cmpb(DisasContext *ctx, unsigned r, = TCGv_reg in1, =20 static bool trans_cmpb(DisasContext *ctx, arg_cmpb *a) { + if (!ctx->is_pa20 && a->d) { + return false; + } nullify_over(ctx); - return do_cmpb(ctx, a->r2, load_gpr(ctx, a->r1), a->c, a->f, a->n, a->= disp); + return do_cmpb(ctx, a->r2, load_gpr(ctx, a->r1), + a->c, a->f, a->d, a->n, a->disp); } =20 static bool trans_cmpbi(DisasContext *ctx, arg_cmpbi *a) { nullify_over(ctx); - return do_cmpb(ctx, a->r, tcg_constant_reg(a->i), a->c, a->f, a->n, a-= >disp); + return do_cmpb(ctx, a->r, tcg_constant_reg(a->i), + a->c, a->f, false, a->n, a->disp); } =20 static bool do_addb(DisasContext *ctx, unsigned r, TCGv_reg in1, --=20 2.34.1 From nobody Wed Nov 27 18:51:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:4860:4864:20::2a; envelope-from=richard.henderson@linaro.org; helo=mail-oa1-x2a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697666022430100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/hppa/insns.decode | 10 ++++++++-- target/hppa/translate.c | 11 ++++++++++- 2 files changed, 18 insertions(+), 3 deletions(-) diff --git a/target/hppa/insns.decode b/target/hppa/insns.decode index fc327e2bb3..48f09c9b06 100644 --- a/target/hppa/insns.decode +++ b/target/hppa/insns.decode @@ -51,6 +51,7 @@ %pos_to_m 0:1 !function=3Dpos_to_m %neg_to_m 0:1 !function=3Dneg_to_m %a_to_m 2:1 !function=3Dneg_to_m +%cmpbid_c 13:2 !function=3Dcmpbid_c =20 #### # Argument set definitions @@ -69,6 +70,7 @@ &rrb_c_f disp n c f r1 r2 &rrb_c_d_f disp n c d f r1 r2 &rib_c_f disp n c f r i +&rib_c_d_f disp n c d f r i =20 #### # Format definitions @@ -88,6 +90,8 @@ &rrb_c_d_f disp=3D%assemble_12 @rib_cf ...... r:5 ..... c:3 ........... n:1 . \ &rib_c_f disp=3D%assemble_12 i=3D%im5_16 +@rib_cdf ...... r:5 ..... c:3 ........... n:1 . \ + &rib_c_d_f disp=3D%assemble_12 i=3D%im5_16 =20 #### # System @@ -303,8 +307,10 @@ cmpb 100000 ..... ..... ... ........... . .= @rrb_cdf d=3D0 f=3D0 cmpb 100010 ..... ..... ... ........... . . @rrb_cdf d=3D0 f= =3D1 cmpb 100111 ..... ..... ... ........... . . @rrb_cdf d=3D1 f= =3D0 cmpb 101111 ..... ..... ... ........... . . @rrb_cdf d=3D1 f= =3D1 -cmpbi 100001 ..... ..... ... ........... . . @rib_cf f=3D0 -cmpbi 100011 ..... ..... ... ........... . . @rib_cf f=3D1 +cmpbi 100001 ..... ..... ... ........... . . @rib_cdf d=3D0 f= =3D0 +cmpbi 100011 ..... ..... ... ........... . . @rib_cdf d=3D0 f= =3D1 +cmpbi 111011 r:5 ..... f:1 .. ........... n:1 . \ + &rib_c_d_f d=3D1 disp=3D%assemble_12 c=3D%cmpbid_c i=3D%im= 5_16 =20 addb 101000 ..... ..... ... ........... . . @rrb_cf f=3D0 addb 101010 ..... ..... ... ........... . . @rrb_cf f=3D1 diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 681c955125..753748082b 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -329,6 +329,12 @@ static int expand_shl11(DisasContext *ctx, int val) return val << 11; } =20 +/* Translate CMPI doubleword conditions to standard. */ +static int cmpbid_c(DisasContext *ctx, int val) +{ + return val ? val : 4; /* 0 =3D=3D "*<<" */ +} + =20 /* Include the auto-generated decoder. */ #include "decode-insns.c.inc" @@ -3101,9 +3107,12 @@ static bool trans_cmpb(DisasContext *ctx, arg_cmpb *= a) =20 static bool trans_cmpbi(DisasContext *ctx, arg_cmpbi *a) { + if (!ctx->is_pa20 && a->d) { + return false; + } nullify_over(ctx); return do_cmpb(ctx, a->r, tcg_constant_reg(a->i), - a->c, a->f, false, a->n, a->disp); + a->c, a->f, a->d, a->n, a->disp); } =20 static bool do_addb(DisasContext *ctx, unsigned r, TCGv_reg in1, --=20 2.34.1 From nobody Wed Nov 27 18:51:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::336; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697666332053100005 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/hppa/translate.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 753748082b..7e723dcd24 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -3122,6 +3122,17 @@ static bool do_addb(DisasContext *ctx, unsigned r, T= CGv_reg in1, DisasCond cond; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::432; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697666346166100003 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/hppa/insns.decode | 15 +++++++++++---- target/hppa/translate.c | 4 ++++ 2 files changed, 15 insertions(+), 4 deletions(-) diff --git a/target/hppa/insns.decode b/target/hppa/insns.decode index 48f09c9b06..33eec3f4c3 100644 --- a/target/hppa/insns.decode +++ b/target/hppa/insns.decode @@ -215,9 +215,14 @@ ld 000011 ..... ..... .. . 0 -- 00 size:2= ...... @ldstx st 000011 ..... ..... .. . 1 -- 10 size:2 ...... @stim5 ldc 000011 ..... ..... .. . 1 -- 0111 ...... @ldim5 siz= e=3D2 ldc 000011 ..... ..... .. . 0 -- 0111 ...... @ldstx siz= e=3D2 +ldc 000011 ..... ..... .. . 1 -- 0101 ...... @ldim5 siz= e=3D3 +ldc 000011 ..... ..... .. . 0 -- 0101 ...... @ldstx siz= e=3D3 lda 000011 ..... ..... .. . 1 -- 0110 ...... @ldim5 siz= e=3D2 lda 000011 ..... ..... .. . 0 -- 0110 ...... @ldstx siz= e=3D2 +lda 000011 ..... ..... .. . 1 -- 0100 ...... @ldim5 siz= e=3D3 +lda 000011 ..... ..... .. . 0 -- 0100 ...... @ldstx siz= e=3D3 sta 000011 ..... ..... .. . 1 -- 1110 ...... @stim5 siz= e=3D2 +sta 000011 ..... ..... .. . 1 -- 1111 ...... @stim5 siz= e=3D3 stby 000011 b:5 r:5 sp:2 a:1 1 -- 1100 m:1 ..... disp=3D%im= 5_0 =20 @fldstwx ...... b:5 x:5 sp:2 scale:1 ....... m:1 ..... \ @@ -244,6 +249,8 @@ fstd 001011 ..... ..... .. . 1 -- 100 0 . ..= ... @fldstdi # Offset Mem #### =20 +@ldstim11 ...... b:5 t:5 sp:2 .............. \ + &ldst disp=3D%assemble_11a m=3D%ma2_to_m x=3D0 scale=3D0 s= ize=3D3 @ldstim14 ...... b:5 t:5 sp:2 .............. \ &ldst disp=3D%lowsign_14 x=3D0 scale=3D0 m=3D0 @ldstim14m ...... b:5 t:5 sp:2 .............. \ @@ -275,11 +282,11 @@ fstw 011110 b:5 ..... sp:2 .............. = \ fstw 011111 b:5 ..... sp:2 ...........0.. \ &ldst disp=3D%assemble_12a t=3D%rm64 m=3D0 x=3D0 scale=3D0= size=3D2 =20 -fldd 010100 b:5 t:5 sp:2 .......... .. 1 . \ - &ldst disp=3D%assemble_11a m=3D%ma2_to_m x=3D0 scale=3D0 s= ize=3D3 +ld 010100 ..... ..... .. ............0. @ldstim11 +fldd 010100 ..... ..... .. ............1. @ldstim11 =20 -fstd 011100 b:5 t:5 sp:2 .......... .. 1 . \ - &ldst disp=3D%assemble_11a m=3D%ma2_to_m x=3D0 scale=3D0 s= ize=3D3 +st 011100 ..... ..... .. ............0. @ldstim11 +fstd 011100 ..... ..... .. ............1. @ldstim11 =20 #### # Floating-point Multiply Add diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 7e723dcd24..308b8dd263 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -2951,6 +2951,10 @@ static bool trans_ldc(DisasContext *ctx, arg_ldst *a) TCGv_reg zero, dest, ofs; TCGv_tl addr; =20 + if (unlikely(TARGET_REGISTER_BITS =3D=3D 32 && a->size > MO_32)) { + return gen_illegal(ctx); + } + nullify_over(ctx); =20 if (a->m) { --=20 2.34.1 From nobody Wed Nov 27 18:51:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1697666513; cv=none; d=zohomail.com; s=zohoarc; b=DsQ6yXiJ/lx6ojEAo9rqi9jHq8uwfHtkU77Aoze7FnKSKlK0D7I8jq26wTmRLpMUI+b/IDrryHKAz7OQSNd5CmvQUpvwuyUyfFkJd6201oVn8cGvsKn2GgNS4WJyhNWUnyhU64R0JvTJ0iz8AQupWBXEynbqsHvMvT2UTgrzXKM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1697666513; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::c2c; envelope-from=richard.henderson@linaro.org; helo=mail-oo1-xc2c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697666514889100010 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/hppa/insns.decode | 19 ++++++++-- target/hppa/translate.c | 80 +++++++++++++++++++++++++++------------- 2 files changed, 69 insertions(+), 30 deletions(-) diff --git a/target/hppa/insns.decode b/target/hppa/insns.decode index 33eec3f4c3..12684b590e 100644 --- a/target/hppa/insns.decode +++ b/target/hppa/insns.decode @@ -46,6 +46,10 @@ =20 %im5_0 0:s1 1:4 %im5_16 16:s1 17:4 +%len5 0:5 !function=3Dassemble_6 +%len6_8 8:1 0:5 !function=3Dassemble_6 +%len6_12 12:1 0:5 !function=3Dassemble_6 +%cpos6_11 11:1 5:5 %ma_to_m 5:1 13:1 !function=3Dma_to_m %ma2_to_m 2:2 !function=3Dma_to_m %pos_to_m 0:1 !function=3Dpos_to_m @@ -334,10 +338,17 @@ shrpw_imm 110100 r2:5 r1:5 c:3 01 0 cpos:5 t= :5 extrw_sar 110100 r:5 t:5 c:3 10 se:1 00000 clen:5 extrw_imm 110100 r:5 t:5 c:3 11 se:1 pos:5 clen:5 =20 -depw_sar 110101 t:5 r:5 c:3 00 nz:1 00000 clen:5 -depw_imm 110101 t:5 r:5 c:3 01 nz:1 cpos:5 clen:5 -depwi_sar 110101 t:5 ..... c:3 10 nz:1 00000 clen:5 i=3D%im5_16 -depwi_imm 110101 t:5 ..... c:3 11 nz:1 cpos:5 clen:5 i=3D%im5_16 +dep_sar 110101 t:5 r:5 c:3 00 nz:1 00 000 ..... d=3D0 len=3D= %len5 +dep_sar 110101 t:5 r:5 c:3 00 nz:1 1. 000 ..... d=3D1 len=3D= %len6_8 +dep_imm 110101 t:5 r:5 c:3 01 nz:1 cpos:5 ..... d=3D0 len=3D= %len5 +dep_imm 111100 t:5 r:5 c:3 .. nz:1 ..... ..... \ + d=3D1 len=3D%len6_12 cpos=3D%cpos6_11 +depi_sar 110101 t:5 ..... c:3 10 nz:1 d:1 . 000 ..... \ + i=3D%im5_16 len=3D%len6_8 +depi_imm 110101 t:5 ..... c:3 11 nz:1 cpos:5 ..... \ + d=3D0 i=3D%im5_16 len=3D%len5 +depi_imm 111101 t:5 ..... c:3 .. nz:1 ..... ..... \ + d=3D1 i=3D%im5_16 len=3D%len6_12 cpos=3D%cpos6_11 =20 #### # Branch External diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 308b8dd263..b3d3506f94 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -329,6 +329,17 @@ static int expand_shl11(DisasContext *ctx, int val) return val << 11; } =20 +static int assemble_6(DisasContext *ctx, int val) +{ + /* + * Officially, 32 * x + 32 - y. + * Here, x is already in bit 5, and y is [4:0]. + * Since -y =3D ~y + 1, in 5 bits 32 - y =3D> y ^ 31 + 1, + * with the overflow from bit 4 summing with x. + */ + return (val ^ 31) + 1; +} + /* Translate CMPI doubleword conditions to standard. */ static int cmpbid_c(DisasContext *ctx, int val) { @@ -3383,17 +3394,23 @@ static bool trans_extrw_imm(DisasContext *ctx, arg_= extrw_imm *a) return nullify_end(ctx); } =20 -static bool trans_depwi_imm(DisasContext *ctx, arg_depwi_imm *a) +static bool trans_depi_imm(DisasContext *ctx, arg_depi_imm *a) { - unsigned len =3D 32 - a->clen; + unsigned len, width; target_sreg mask0, mask1; TCGv_reg dest; =20 + if (!ctx->is_pa20 && a->d) { + return false; + } if (a->c) { nullify_over(ctx); } - if (a->cpos + len > 32) { - len =3D 32 - a->cpos; + + len =3D a->len; + width =3D a->d ? 64 : 32; + if (a->cpos + len > width) { + len =3D width - a->cpos; } =20 dest =3D dest_gpr(ctx, a->t); @@ -3402,11 +3419,8 @@ static bool trans_depwi_imm(DisasContext *ctx, arg_d= epwi_imm *a) =20 if (a->nz) { TCGv_reg src =3D load_gpr(ctx, a->t); - if (mask1 !=3D -1) { - tcg_gen_andi_reg(dest, src, mask1); - src =3D dest; - } - tcg_gen_ori_reg(dest, src, mask0); + tcg_gen_andi_reg(dest, src, mask1); + tcg_gen_ori_reg(dest, dest, mask0); } else { tcg_gen_movi_reg(dest, mask0); } @@ -3415,22 +3429,28 @@ static bool trans_depwi_imm(DisasContext *ctx, arg_= depwi_imm *a) /* Install the new nullification. */ cond_free(&ctx->null_cond); if (a->c) { - ctx->null_cond =3D do_sed_cond(ctx, a->c, false, dest); + ctx->null_cond =3D do_sed_cond(ctx, a->c, a->d, dest); } return nullify_end(ctx); } =20 -static bool trans_depw_imm(DisasContext *ctx, arg_depw_imm *a) +static bool trans_dep_imm(DisasContext *ctx, arg_dep_imm *a) { unsigned rs =3D a->nz ? a->t : 0; - unsigned len =3D 32 - a->clen; + unsigned len, width; TCGv_reg dest, val; =20 + if (!ctx->is_pa20 && a->d) { + return false; + } if (a->c) { nullify_over(ctx); } - if (a->cpos + len > 32) { - len =3D 32 - a->cpos; + + len =3D a->len; + width =3D a->d ? 64 : 32; + if (a->cpos + len > width) { + len =3D width - a->cpos; } =20 dest =3D dest_gpr(ctx, a->t); @@ -3445,26 +3465,26 @@ static bool trans_depw_imm(DisasContext *ctx, arg_d= epw_imm *a) /* Install the new nullification. */ cond_free(&ctx->null_cond); if (a->c) { - ctx->null_cond =3D do_sed_cond(ctx, a->c, false, dest); + ctx->null_cond =3D do_sed_cond(ctx, a->c, a->d, dest); } return nullify_end(ctx); } =20 -static bool do_depw_sar(DisasContext *ctx, unsigned rt, unsigned c, - unsigned nz, unsigned clen, TCGv_reg val) +static bool do_dep_sar(DisasContext *ctx, unsigned rt, unsigned c, + bool d, bool nz, unsigned len, TCGv_reg val) { unsigned rs =3D nz ? rt : 0; - unsigned len =3D 32 - clen; + unsigned widthm1 =3D d ? 63 : 31; TCGv_reg mask, tmp, shift, dest; - unsigned msb =3D 1U << (len - 1); + target_ureg msb =3D 1ULL << (len - 1); =20 dest =3D dest_gpr(ctx, rt); shift =3D tcg_temp_new(); tmp =3D tcg_temp_new(); =20 /* Convert big-endian bit numbering in SAR to left-shift. */ - tcg_gen_andi_reg(shift, cpu_sar, 31); - tcg_gen_xori_reg(shift, shift, 31); + tcg_gen_andi_reg(shift, cpu_sar, widthm1); + tcg_gen_xori_reg(shift, shift, widthm1); =20 mask =3D tcg_temp_new(); tcg_gen_movi_reg(mask, msb + (msb - 1)); @@ -3482,25 +3502,33 @@ static bool do_depw_sar(DisasContext *ctx, unsigned= rt, unsigned c, /* Install the new nullification. */ cond_free(&ctx->null_cond); if (c) { - ctx->null_cond =3D do_sed_cond(ctx, c, false, dest); + ctx->null_cond =3D do_sed_cond(ctx, c, d, dest); } return nullify_end(ctx); } =20 -static bool trans_depw_sar(DisasContext *ctx, arg_depw_sar *a) +static bool trans_dep_sar(DisasContext *ctx, arg_dep_sar *a) { + if (!ctx->is_pa20 && a->d) { + return false; + } if (a->c) { nullify_over(ctx); } - return do_depw_sar(ctx, a->t, a->c, a->nz, a->clen, load_gpr(ctx, a->r= )); + return do_dep_sar(ctx, a->t, a->c, a->d, a->nz, a->len, + load_gpr(ctx, a->r)); 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::c34; envelope-from=richard.henderson@linaro.org; helo=mail-oo1-xc34.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697666468638100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/hppa/insns.decode | 7 +++++-- target/hppa/translate.c | 34 +++++++++++++++++++++++----------- 2 files changed, 28 insertions(+), 13 deletions(-) diff --git a/target/hppa/insns.decode b/target/hppa/insns.decode index 12684b590e..7b51f39b9e 100644 --- a/target/hppa/insns.decode +++ b/target/hppa/insns.decode @@ -335,8 +335,11 @@ addbi 101011 ..... ..... ... ........... . .= @rib_cf f=3D1 shrpw_sar 110100 r2:5 r1:5 c:3 00 0 00000 t:5 shrpw_imm 110100 r2:5 r1:5 c:3 01 0 cpos:5 t:5 =20 -extrw_sar 110100 r:5 t:5 c:3 10 se:1 00000 clen:5 -extrw_imm 110100 r:5 t:5 c:3 11 se:1 pos:5 clen:5 +extr_sar 110100 r:5 t:5 c:3 10 se:1 00 000 ..... d=3D0 len=3D= %len5 +extr_sar 110100 r:5 t:5 c:3 10 se:1 1. 000 ..... d=3D1 len=3D= %len6_8 +extr_imm 110100 r:5 t:5 c:3 11 se:1 pos:5 ..... d=3D0 len=3D= %len5 +extr_imm 110110 r:5 t:5 c:3 .. se:1 ..... ..... \ + d=3D1 len=3D%len6_12 pos=3D%cpos6_11 =20 dep_sar 110101 t:5 r:5 c:3 00 nz:1 00 000 ..... d=3D0 len=3D= %len5 dep_sar 110101 t:5 r:5 c:3 00 nz:1 1. 000 ..... d=3D1 len=3D= %len6_8 diff --git a/target/hppa/translate.c b/target/hppa/translate.c index b3d3506f94..974ed558d7 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -3333,11 +3333,14 @@ static bool trans_shrpw_imm(DisasContext *ctx, arg_= shrpw_imm *a) return nullify_end(ctx); } =20 -static bool trans_extrw_sar(DisasContext *ctx, arg_extrw_sar *a) +static bool trans_extr_sar(DisasContext *ctx, arg_extr_sar *a) { - unsigned len =3D 32 - a->clen; + unsigned widthm1 =3D a->d ? 63 : 31; TCGv_reg dest, src, tmp; =20 + if (!ctx->is_pa20 && a->d) { + return false; + } if (a->c) { nullify_over(ctx); } @@ -3347,36 +3350,45 @@ static bool trans_extrw_sar(DisasContext *ctx, arg_= extrw_sar *a) tmp =3D tcg_temp_new(); =20 /* Recall that SAR is using big-endian bit numbering. */ - tcg_gen_andi_reg(tmp, cpu_sar, 31); - tcg_gen_xori_reg(tmp, tmp, 31); + tcg_gen_andi_reg(tmp, cpu_sar, widthm1); + tcg_gen_xori_reg(tmp, tmp, widthm1); =20 if (a->se) { tcg_gen_sar_reg(dest, src, tmp); - tcg_gen_sextract_reg(dest, dest, 0, len); + tcg_gen_sextract_reg(dest, dest, 0, a->len); } else { tcg_gen_shr_reg(dest, src, tmp); - tcg_gen_extract_reg(dest, dest, 0, len); + tcg_gen_extract_reg(dest, dest, 0, a->len); } save_gpr(ctx, a->t, dest); =20 /* Install the new nullification. */ cond_free(&ctx->null_cond); if (a->c) { - ctx->null_cond =3D do_sed_cond(ctx, a->c, false, dest); + ctx->null_cond =3D do_sed_cond(ctx, a->c, a->d, dest); } return nullify_end(ctx); } =20 -static bool trans_extrw_imm(DisasContext *ctx, arg_extrw_imm *a) +static bool trans_extr_imm(DisasContext *ctx, arg_extr_imm *a) { - unsigned len =3D 32 - a->clen; - unsigned cpos =3D 31 - a->pos; + unsigned len, cpos, width; TCGv_reg dest, src; =20 + if (!ctx->is_pa20 && a->d) { + return false; + } if (a->c) { nullify_over(ctx); } =20 + len =3D a->len; + width =3D a->d ? 64 : 32; + cpos =3D width - 1 - a->pos; + if (cpos + len > width) { + len =3D width - cpos; + } + dest =3D dest_gpr(ctx, a->t); src =3D load_gpr(ctx, a->r); if (a->se) { @@ -3389,7 +3401,7 @@ static bool trans_extrw_imm(DisasContext *ctx, arg_ex= trw_imm *a) /* Install the new nullification. */ cond_free(&ctx->null_cond); if (a->c) { - ctx->null_cond =3D do_sed_cond(ctx, a->c, false, dest); + ctx->null_cond =3D do_sed_cond(ctx, a->c, a->d, dest); } return nullify_end(ctx); } --=20 2.34.1 From nobody Wed Nov 27 18:51:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1697666773; cv=none; d=zohomail.com; s=zohoarc; b=myhmbjdsvecxA5a8c1QHXiOUdDgnA80PrrULh3CDsdbvkhCsBIZQTbGmOHBCv5MIUalnDZuZ9E3XWOccniS4xAfeFsjXl5gjcVBGb+LXVhBVhMKkZKgibIl9A4j/uo98SR2ZF4AVJGrjxMk4iToevgAPhKFIR/g9gAg6D1WB7WU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1697666773; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=DqhTZ/67UqvsjENOJGo2HAt1BkeJsPyDRGA2t98wGsU=; b=LYxgWITsxGW7GGnTvgkTGksxkmZWKkteKxKKZd1IcqFTJYuGO7tO+xXIABCsjbL7zbQ7vmNa0CTQVP+Ky/37mZoDuxEWRjFvUilVUaGd4975MydPPphu2E6mE9oV/Pq5+QmR/5EtlgGxRGd851o7HeiYsy2xbDu1i+mPlDB1Ztw= ARC-Authentication-Results: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::430; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697666775782100003 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/hppa/insns.decode | 6 ++- target/hppa/translate.c | 79 ++++++++++++++++++++++++++++------------ 2 files changed, 60 insertions(+), 25 deletions(-) diff --git a/target/hppa/insns.decode b/target/hppa/insns.decode index 7b51f39b9e..6f0c3f6ea5 100644 --- a/target/hppa/insns.decode +++ b/target/hppa/insns.decode @@ -332,8 +332,10 @@ addbi 101011 ..... ..... ... ........... . .= @rib_cf f=3D1 # Shift, Extract, Deposit #### =20 -shrpw_sar 110100 r2:5 r1:5 c:3 00 0 00000 t:5 -shrpw_imm 110100 r2:5 r1:5 c:3 01 0 cpos:5 t:5 +shrp_sar 110100 r2:5 r1:5 c:3 00 0 d:1 0000 t:5 +shrp_imm 110100 r2:5 r1:5 c:3 01 0 cpos:5 t:5 d=3D0 +shrp_imm 110100 r2:5 r1:5 c:3 0. 1 ..... t:5 \ + d=3D1 cpos=3D%cpos6_11 =20 extr_sar 110100 r:5 t:5 c:3 10 se:1 00 000 ..... d=3D0 len=3D= %len5 extr_sar 110100 r:5 t:5 c:3 10 se:1 1. 000 ..... d=3D1 len=3D= %len6_8 diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 974ed558d7..a23c44e3d6 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -3258,32 +3258,56 @@ static bool trans_movbi(DisasContext *ctx, arg_movb= i *a) return do_cbranch(ctx, a->disp, a->n, &cond); } =20 -static bool trans_shrpw_sar(DisasContext *ctx, arg_shrpw_sar *a) +static bool trans_shrp_sar(DisasContext *ctx, arg_shrp_sar *a) { - TCGv_reg dest; + TCGv_reg dest, tmp; =20 + if (!ctx->is_pa20 && a->d) { + return false; + } if (a->c) { nullify_over(ctx); } =20 dest =3D dest_gpr(ctx, a->t); if (a->r1 =3D=3D 0) { - tcg_gen_ext32u_reg(dest, load_gpr(ctx, a->r2)); - tcg_gen_shr_reg(dest, dest, cpu_sar); + if (a->d) { + tcg_gen_shr_reg(dest, dest, cpu_sar); + } else { + tcg_gen_ext32u_reg(dest, load_gpr(ctx, a->r2)); + tmp =3D tcg_temp_new(); + tcg_gen_andi_reg(tmp, cpu_sar, 31); + tcg_gen_shr_reg(dest, dest, tmp); + } } else if (a->r1 =3D=3D a->r2) { - TCGv_i32 t32 =3D tcg_temp_new_i32(); - TCGv_i32 s32 =3D tcg_temp_new_i32(); + if (a->d) { + tcg_gen_rotr_reg(dest, load_gpr(ctx, a->r2), cpu_sar); + } else { + TCGv_i32 t32 =3D tcg_temp_new_i32(); + TCGv_i32 s32 =3D tcg_temp_new_i32(); =20 - tcg_gen_trunc_reg_i32(t32, load_gpr(ctx, a->r2)); - tcg_gen_trunc_reg_i32(s32, cpu_sar); - tcg_gen_rotr_i32(t32, t32, s32); - tcg_gen_extu_i32_reg(dest, t32); + tcg_gen_trunc_reg_i32(t32, load_gpr(ctx, a->r2)); + tcg_gen_trunc_reg_i32(s32, cpu_sar); + tcg_gen_andi_i32(s32, s32, 31); + tcg_gen_rotr_i32(t32, t32, s32); + tcg_gen_extu_i32_reg(dest, t32); + } + } else if (a->d) { + TCGv_reg t =3D tcg_temp_new(); + TCGv_reg n =3D tcg_temp_new(); + + tcg_gen_xori_reg(n, cpu_sar, 63); + tcg_gen_shl_reg(t, load_gpr(ctx, a->r2), n); + tcg_gen_shli_reg(t, t, 1); + tcg_gen_shr_reg(dest, load_gpr(ctx, a->r1), cpu_sar); + tcg_gen_or_reg(dest, dest, t); } else { TCGv_i64 t =3D tcg_temp_new_i64(); TCGv_i64 s =3D tcg_temp_new_i64(); =20 tcg_gen_concat_reg_i64(t, load_gpr(ctx, a->r2), load_gpr(ctx, a->r= 1)); tcg_gen_extu_reg_i64(s, cpu_sar); + tcg_gen_andi_i64(s, s, 31); tcg_gen_shr_i64(t, t, s); tcg_gen_trunc_i64_reg(dest, t); } @@ -3297,31 +3321,40 @@ static bool trans_shrpw_sar(DisasContext *ctx, arg_= shrpw_sar *a) return nullify_end(ctx); } =20 -static bool trans_shrpw_imm(DisasContext *ctx, arg_shrpw_imm *a) +static bool trans_shrp_imm(DisasContext *ctx, arg_shrp_imm *a) { - unsigned sa =3D 31 - a->cpos; + unsigned width, sa; TCGv_reg dest, t2; =20 + if (!ctx->is_pa20 && a->d) { + return false; + } if (a->c) { nullify_over(ctx); } =20 + width =3D a->d ? 64 : 32; + sa =3D width - 1 - a->cpos; + dest =3D dest_gpr(ctx, a->t); t2 =3D load_gpr(ctx, a->r2); if (a->r1 =3D=3D 0) { - tcg_gen_extract_reg(dest, t2, sa, 32 - sa); - } else if (TARGET_REGISTER_BITS =3D=3D 32) { + tcg_gen_extract_reg(dest, t2, sa, width - sa); + } else if (width =3D=3D TARGET_REGISTER_BITS) { tcg_gen_extract2_reg(dest, t2, cpu_gr[a->r1], sa); - } else if (a->r1 =3D=3D a->r2) { - TCGv_i32 t32 =3D tcg_temp_new_i32(); - tcg_gen_trunc_reg_i32(t32, t2); - tcg_gen_rotri_i32(t32, t32, sa); - tcg_gen_extu_i32_reg(dest, t32); } else { - TCGv_i64 t64 =3D tcg_temp_new_i64(); - tcg_gen_concat_reg_i64(t64, t2, cpu_gr[a->r1]); - tcg_gen_shri_i64(t64, t64, sa); - tcg_gen_trunc_i64_reg(dest, t64); + assert(!a->d); + if (a->r1 =3D=3D a->r2) { + TCGv_i32 t32 =3D tcg_temp_new_i32(); + tcg_gen_trunc_reg_i32(t32, t2); + tcg_gen_rotri_i32(t32, t32, sa); + tcg_gen_extu_i32_reg(dest, t32); + } else { + TCGv_i64 t64 =3D tcg_temp_new_i64(); + tcg_gen_concat_reg_i64(t64, t2, cpu_gr[a->r1]); + tcg_gen_shri_i64(t64, t64, sa); + tcg_gen_trunc_i64_reg(dest, t64); + } } save_gpr(ctx, a->t, dest); =20 --=20 2.34.1 From nobody Wed Nov 27 18:51:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1697666502; cv=none; d=zohomail.com; s=zohoarc; b=bOEacZ0r3sLg1DRf/h6c4Sj0T61woKNe9IHkwH+XOE6DJqXjHKqespSIbDQPNF6rTaGXqKbAWWcyADjLIuJZ9YSyLpGisNxSqh6HXuI5I8hu54PhRY2tsqvHAUjc/KJCC3fR6EZ8vRrq6tJ6+O4AUBK12W2iBtelh9SjDS58onQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1697666502; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::434; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697666502736100005 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/hppa/insns.decode | 2 ++ target/hppa/translate.c | 6 ++++++ 2 files changed, 8 insertions(+) diff --git a/target/hppa/insns.decode b/target/hppa/insns.decode index 6f0c3f6ea5..ba7731b517 100644 --- a/target/hppa/insns.decode +++ b/target/hppa/insns.decode @@ -381,6 +381,8 @@ bl 111010 ..... ..... 101 ........... n:1 = . &BL l=3D2 \ disp=3D%assemble_22 b_gate 111010 ..... ..... 001 ........... . . @bl blr 111010 l:5 x:5 010 00000000000 n:1 0 +nopbts 111010 00000 00000 010 0---------1 0 1 # clrbts/popbts +nopbts 111010 00000 ----- 010 00000000000 0 1 # pushbts/push= nom bv 111010 b:5 x:5 110 00000000000 n:1 0 bve 111010 b:5 00000 110 10000000000 n:1 - l=3D0 bve 111010 b:5 00000 111 10000000000 n:1 - l=3D2 diff --git a/target/hppa/translate.c b/target/hppa/translate.c index a23c44e3d6..56c0a4fea1 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -3746,6 +3746,12 @@ static bool trans_bve(DisasContext *ctx, arg_bve *a) #endif } =20 +static bool trans_nopbts(DisasContext *ctx, arg_nopbts *a) +{ + /* All branch target stack instructions implement as nop. */ + return ctx->is_pa20; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::32e; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697666482657100003 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/hppa/helper.h | 5 ++ target/hppa/insns.decode | 1 + target/hppa/op_helper.c | 178 +++++++++++++++++++++++++++++++++++++-- target/hppa/translate.c | 31 +++++++ 4 files changed, 210 insertions(+), 5 deletions(-) diff --git a/target/hppa/helper.h b/target/hppa/helper.h index 647f043c85..9920d38ded 100644 --- a/target/hppa/helper.h +++ b/target/hppa/helper.h @@ -16,6 +16,11 @@ DEF_HELPER_FLAGS_3(stby_b_parallel, TCG_CALL_NO_WG, void= , env, tl, tr) DEF_HELPER_FLAGS_3(stby_e, TCG_CALL_NO_WG, void, env, tl, tr) DEF_HELPER_FLAGS_3(stby_e_parallel, TCG_CALL_NO_WG, void, env, tl, tr) =20 +DEF_HELPER_FLAGS_3(stdby_b, TCG_CALL_NO_WG, void, env, tl, tr) +DEF_HELPER_FLAGS_3(stdby_b_parallel, TCG_CALL_NO_WG, void, env, tl, tr) +DEF_HELPER_FLAGS_3(stdby_e, TCG_CALL_NO_WG, void, env, tl, tr) +DEF_HELPER_FLAGS_3(stdby_e_parallel, TCG_CALL_NO_WG, void, env, tl, tr) + DEF_HELPER_FLAGS_1(ldc_check, TCG_CALL_NO_RWG, void, tl) =20 DEF_HELPER_FLAGS_4(probe, TCG_CALL_NO_WG, tr, env, tl, i32, i32) diff --git a/target/hppa/insns.decode b/target/hppa/insns.decode index ba7731b517..9d8c6a1a16 100644 --- a/target/hppa/insns.decode +++ b/target/hppa/insns.decode @@ -228,6 +228,7 @@ lda 000011 ..... ..... .. . 0 -- 0100 = ...... @ldstx size=3D3 sta 000011 ..... ..... .. . 1 -- 1110 ...... @stim5 siz= e=3D2 sta 000011 ..... ..... .. . 1 -- 1111 ...... @stim5 siz= e=3D3 stby 000011 b:5 r:5 sp:2 a:1 1 -- 1100 m:1 ..... disp=3D%im= 5_0 +stdby 000011 b:5 r:5 sp:2 a:1 1 -- 1101 m:1 ..... disp=3D%im= 5_0 =20 @fldstwx ...... b:5 x:5 sp:2 scale:1 ....... m:1 ..... \ &ldst t=3D%rt64 disp=3D0 size=3D2 diff --git a/target/hppa/op_helper.c b/target/hppa/op_helper.c index 837e2b3117..94c9ca5858 100644 --- a/target/hppa/op_helper.c +++ b/target/hppa/op_helper.c @@ -56,11 +56,11 @@ void HELPER(tcond)(CPUHPPAState *env, target_ureg cond) } } =20 -static void atomic_store_3(CPUHPPAState *env, target_ulong addr, - uint32_t val, uintptr_t ra) +static void atomic_store_mask32(CPUHPPAState *env, target_ulong addr, + uint32_t val, uint32_t mask, uintptr_t ra) { int mmu_idx =3D cpu_mmu_index(env, 0); - uint32_t old, new, cmp, mask, *haddr; + uint32_t old, new, cmp, *haddr; void *vaddr; =20 vaddr =3D probe_access(env, addr, 3, MMU_DATA_STORE, mmu_idx, ra); @@ -81,6 +81,35 @@ static void atomic_store_3(CPUHPPAState *env, target_ulo= ng addr, } } =20 +static void atomic_store_mask64(CPUHPPAState *env, target_ulong addr, + uint64_t val, uint64_t mask, + int size, uintptr_t ra) +{ +#ifdef CONFIG_ATOMIC64 + int mmu_idx =3D cpu_mmu_index(env, 0); + uint64_t old, new, cmp, *haddr; + void *vaddr; + + vaddr =3D probe_access(env, addr, size, MMU_DATA_STORE, mmu_idx, ra); + if (vaddr =3D=3D NULL) { + cpu_loop_exit_atomic(env_cpu(env), ra); + } + haddr =3D (uint64_t *)((uintptr_t)vaddr & -8); + + old =3D *haddr; + while (1) { + new =3D be32_to_cpu((cpu_to_be32(old) & ~mask) | (val & mask)); + cmp =3D qatomic_cmpxchg__nocheck(haddr, old, new); + if (cmp =3D=3D old) { + return; + } + old =3D cmp; + } +#else + cpu_loop_exit_atomic(env_cpu(env), ra); +#endif +} + static void do_stby_b(CPUHPPAState *env, target_ulong addr, target_ureg va= l, bool parallel, uintptr_t ra) { @@ -94,7 +123,7 @@ static void do_stby_b(CPUHPPAState *env, target_ulong ad= dr, target_ureg val, case 1: /* The 3 byte store must appear atomic. */ if (parallel) { - atomic_store_3(env, addr, val, ra); + atomic_store_mask32(env, addr, val, 0x00ffffffu, ra); } else { cpu_stb_data_ra(env, addr, val >> 16, ra); cpu_stw_data_ra(env, addr + 1, val, ra); @@ -106,6 +135,62 @@ static void do_stby_b(CPUHPPAState *env, target_ulong = addr, target_ureg val, } } =20 +static void do_stdby_b(CPUHPPAState *env, target_ulong addr, uint64_t val, + bool parallel, uintptr_t ra) +{ + switch (addr & 7) { + case 7: + cpu_stb_data_ra(env, addr, val, ra); + break; + case 6: + cpu_stw_data_ra(env, addr, val, ra); + break; + case 5: + /* The 3 byte store must appear atomic. */ + if (parallel) { + atomic_store_mask32(env, addr, val, 0x00ffffffu, ra); + } else { + cpu_stb_data_ra(env, addr, val >> 16, ra); + cpu_stw_data_ra(env, addr + 1, val, ra); + } + break; + case 4: + cpu_stl_data_ra(env, addr, val, ra); + break; + case 3: + /* The 5 byte store must appear atomic. */ + if (parallel) { + atomic_store_mask64(env, addr, val, 0x000000ffffffffffull, 5, = ra); + } else { + cpu_stb_data_ra(env, addr, val >> 32, ra); + cpu_stl_data_ra(env, addr + 1, val, ra); + } + break; + case 2: + /* The 6 byte store must appear atomic. */ + if (parallel) { + atomic_store_mask64(env, addr, val, 0x0000ffffffffffffull, 6, = ra); + } else { + cpu_stw_data_ra(env, addr, val >> 32, ra); + cpu_stl_data_ra(env, addr + 2, val, ra); + } + break; + case 1: + /* The 7 byte store must appear atomic. */ + if (parallel) { + atomic_store_mask64(env, addr, val, 0x00ffffffffffffffull, 7, = ra); + } else { + cpu_stb_data_ra(env, addr, val >> 48, ra); + cpu_stw_data_ra(env, addr + 1, val >> 32, ra); + cpu_stl_data_ra(env, addr + 3, val, ra); + } + break; + default: + cpu_stl_data_ra(env, addr, val, ra); + break; + } +} + void HELPER(stby_b)(CPUHPPAState *env, target_ulong addr, target_ureg val) { do_stby_b(env, addr, val, false, GETPC()); @@ -117,6 +202,17 @@ void HELPER(stby_b_parallel)(CPUHPPAState *env, target= _ulong addr, do_stby_b(env, addr, val, true, GETPC()); } =20 +void HELPER(stdby_b)(CPUHPPAState *env, target_ulong addr, target_ureg val) +{ + do_stdby_b(env, addr, val, false, GETPC()); +} + +void HELPER(stdby_b_parallel)(CPUHPPAState *env, target_ulong addr, + target_ureg val) +{ + do_stdby_b(env, addr, val, true, GETPC()); +} + static void do_stby_e(CPUHPPAState *env, target_ulong addr, target_ureg va= l, bool parallel, uintptr_t ra) { @@ -124,7 +220,68 @@ static void do_stby_e(CPUHPPAState *env, target_ulong = addr, target_ureg val, case 3: /* The 3 byte store must appear atomic. */ if (parallel) { - atomic_store_3(env, addr - 3, val, ra); + atomic_store_mask32(env, addr - 3, val, 0xffffff00u, ra); + } else { + cpu_stw_data_ra(env, addr - 3, val >> 16, ra); + cpu_stb_data_ra(env, addr - 1, val >> 8, ra); + } + break; + case 2: + cpu_stw_data_ra(env, addr - 2, val >> 16, ra); + break; + case 1: + cpu_stb_data_ra(env, addr - 1, val >> 24, ra); + break; + default: + /* Nothing is stored, but protection is checked and the + cacheline is marked dirty. */ + probe_write(env, addr, 0, cpu_mmu_index(env, 0), ra); + break; + } +} + +static void do_stdby_e(CPUHPPAState *env, target_ulong addr, uint64_t val, + bool parallel, uintptr_t ra) +{ + switch (addr & 7) { + case 7: + /* The 7 byte store must appear atomic. */ + if (parallel) { + atomic_store_mask64(env, addr - 7, val, + 0xffffffffffffff00ull, 7, ra); + } else { + cpu_stl_data_ra(env, addr - 7, val >> 32, ra); + cpu_stw_data_ra(env, addr - 3, val >> 16, ra); + cpu_stb_data_ra(env, addr - 1, val >> 8, ra); + } + break; + case 6: + /* The 6 byte store must appear atomic. */ + if (parallel) { + atomic_store_mask64(env, addr - 6, val, + 0xffffffffffff0000ull, 6, ra); + } else { + cpu_stl_data_ra(env, addr - 6, val >> 32, ra); + cpu_stw_data_ra(env, addr - 2, val >> 16, ra); + } + break; + case 5: + /* The 5 byte store must appear atomic. */ + if (parallel) { + atomic_store_mask64(env, addr - 5, val, + 0xffffffffff000000ull, 5, ra); + } else { + cpu_stl_data_ra(env, addr - 5, val >> 32, ra); + cpu_stb_data_ra(env, addr - 1, val >> 24, ra); + } + break; + case 4: + cpu_stl_data_ra(env, addr - 4, val >> 32, ra); + break; + case 3: + /* The 3 byte store must appear atomic. */ + if (parallel) { + atomic_store_mask32(env, addr - 3, val, 0xffffff00u, ra); } else { cpu_stw_data_ra(env, addr - 3, val >> 16, ra); cpu_stb_data_ra(env, addr - 1, val >> 8, ra); @@ -155,6 +312,17 @@ void HELPER(stby_e_parallel)(CPUHPPAState *env, target= _ulong addr, do_stby_e(env, addr, val, true, GETPC()); } =20 +void HELPER(stdby_e)(CPUHPPAState *env, target_ulong addr, target_ureg val) +{ + do_stdby_e(env, addr, val, false, GETPC()); +} + +void HELPER(stdby_e_parallel)(CPUHPPAState *env, target_ulong addr, + target_ureg val) +{ + do_stdby_e(env, addr, val, true, GETPC()); +} + void HELPER(ldc_check)(target_ulong addr) { if (unlikely(addr & 0xf)) { diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 56c0a4fea1..4a0ae5a772 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -3031,6 +3031,37 @@ static bool trans_stby(DisasContext *ctx, arg_stby *= a) return nullify_end(ctx); } =20 +static bool trans_stdby(DisasContext *ctx, arg_stby *a) +{ + TCGv_reg ofs, val; + TCGv_tl addr; + + nullify_over(ctx); + + form_gva(ctx, &addr, &ofs, a->b, 0, 0, a->disp, a->sp, a->m, + ctx->mmu_idx =3D=3D MMU_PHYS_IDX); + val =3D load_gpr(ctx, a->r); + if (a->a) { + if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { + gen_helper_stdby_e_parallel(tcg_env, addr, val); + } else { + gen_helper_stdby_e(tcg_env, addr, val); + } + } else { + if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { + gen_helper_stdby_b_parallel(tcg_env, addr, val); + } else { + gen_helper_stdby_b(tcg_env, addr, val); + } + } + if (a->m) { + tcg_gen_andi_reg(ofs, ofs, ~7); + save_gpr(ctx, a->b, ofs); + } + + return nullify_end(ctx); +} + static bool trans_lda(DisasContext *ctx, arg_ldst *a) { int hold_mmu_idx =3D ctx->mmu_idx; --=20 2.34.1 From nobody Wed Nov 27 18:51:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1697666754; cv=none; d=zohomail.com; s=zohoarc; b=VWfaKOMz8FvaovepGlpPHMotuhYUf3g8fDsktb9H+025ZKwq1tHgcd4+QCTqvHyXvcLCiHcQQZQVTI0KUTi2A5D1lWRQ1sWUqd3/3zqiB7vJXQ+XJrtBfxFvaQe+9WKLgC9JZKxKxCbhCWOGwL7RuSu3t+MogG4GW7Zk3fmV2wE= ARC-Message-Signature: i=1; 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Implement a combined i/d tlb for pa2.0. Still missing is the new 'P' tlb bit. Signed-off-by: Richard Henderson --- target/hppa/helper.h | 5 ++-- target/hppa/insns.decode | 4 +++ target/hppa/mem_helper.c | 63 +++++++++++++++++++++++++++++++++------- target/hppa/translate.c | 35 ++++++++++++++++++---- 4 files changed, 89 insertions(+), 18 deletions(-) diff --git a/target/hppa/helper.h b/target/hppa/helper.h index 9920d38ded..58b6754dbe 100644 --- a/target/hppa/helper.h +++ b/target/hppa/helper.h @@ -94,8 +94,9 @@ DEF_HELPER_FLAGS_2(write_interval_timer, TCG_CALL_NO_RWG,= void, env, tr) DEF_HELPER_FLAGS_2(write_eirr, TCG_CALL_NO_RWG, void, env, tr) DEF_HELPER_FLAGS_2(write_eiem, TCG_CALL_NO_RWG, void, env, tr) DEF_HELPER_FLAGS_2(swap_system_mask, TCG_CALL_NO_RWG, tr, env, tr) -DEF_HELPER_FLAGS_3(itlba, TCG_CALL_NO_RWG, void, env, tl, tr) -DEF_HELPER_FLAGS_3(itlbp, TCG_CALL_NO_RWG, void, env, tl, tr) +DEF_HELPER_FLAGS_3(itlba_pa11, TCG_CALL_NO_RWG, void, env, tl, tr) +DEF_HELPER_FLAGS_3(itlbp_pa11, TCG_CALL_NO_RWG, void, env, tl, tr) +DEF_HELPER_FLAGS_3(itlbt_pa20, TCG_CALL_NO_RWG, void, env, tr, tr) DEF_HELPER_FLAGS_2(ptlb, TCG_CALL_NO_RWG, void, env, tl) DEF_HELPER_FLAGS_1(ptlbe, TCG_CALL_NO_RWG, void, env) DEF_HELPER_FLAGS_2(lpa, TCG_CALL_NO_WG, tr, env, tl) diff --git a/target/hppa/insns.decode b/target/hppa/insns.decode index 9d8c6a1a16..db1b9f750f 100644 --- a/target/hppa/insns.decode +++ b/target/hppa/insns.decode @@ -152,6 +152,10 @@ ixtlbx 000001 b:5 r:5 ... 000000 addr:1 0 000= 00 \ # pcxl and pcxl2 Fast TLB Insert instructions ixtlbxf 000001 00000 r:5 00 0 data:1 01000 addr:1 0 00000 =20 +# pa2.0 tlb insert instructions +ixtlbt 000001 r2:5 r1:5 000 1100000 0 00000 # idtlbt +ixtlbt 000001 r2:5 r1:5 000 0100000 0 00000 # iitlbt + pxtlbx 000001 b:5 x:5 sp:2 0100100 local:1 m:1 ----- data=3D1 pxtlbx 000001 b:5 x:5 ... 000100 local:1 m:1 ----- \ sp=3D%assemble_sr3x data=3D0 diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c index 169e878479..d6f46b18e9 100644 --- a/target/hppa/mem_helper.c +++ b/target/hppa/mem_helper.c @@ -312,7 +312,7 @@ bool hppa_cpu_tlb_fill(CPUState *cs, vaddr addr, int si= ze, } =20 /* Insert (Insn/Data) TLB Address. Note this is PA 1.1 only. */ -void HELPER(itlba)(CPUHPPAState *env, target_ulong addr, target_ureg reg) +void HELPER(itlba_pa11)(CPUHPPAState *env, target_ulong addr, target_ureg = reg) { hppa_tlb_entry *empty =3D NULL; int i; @@ -338,15 +338,12 @@ void HELPER(itlba)(CPUHPPAState *env, target_ulong ad= dr, target_ureg reg) /* Note that empty->entry_valid =3D=3D 0 already. */ empty->va_b =3D addr & TARGET_PAGE_MASK; empty->va_e =3D empty->va_b + TARGET_PAGE_SIZE - 1; - /* - * FIXME: This is wrong, as this is a pa1.1 function. - * But for the moment translate abs address for pa2.0. - */ - empty->pa =3D hppa_abs_to_phys(env, extract32(reg, 5, 20) << TARGET_PA= GE_BITS); + empty->pa =3D extract32(reg, 5, 20) << TARGET_PAGE_BITS; trace_hppa_tlb_itlba(env, empty, empty->va_b, empty->va_e, empty->pa); } =20 -static void set_access_bits(CPUHPPAState *env, hppa_tlb_entry *ent, target= _ureg reg) +static void set_access_bits_pa11(CPUHPPAState *env, hppa_tlb_entry *ent, + target_ureg reg) { ent->access_id =3D extract32(reg, 1, 18); ent->u =3D extract32(reg, 19, 1); @@ -362,7 +359,7 @@ static void set_access_bits(CPUHPPAState *env, hppa_tlb= _entry *ent, target_ureg } =20 /* Insert (Insn/Data) TLB Protection. Note this is PA 1.1 only. */ -void HELPER(itlbp)(CPUHPPAState *env, target_ulong addr, target_ureg reg) +void HELPER(itlbp_pa11)(CPUHPPAState *env, target_ulong addr, target_ureg = reg) { hppa_tlb_entry *ent =3D hppa_find_tlb(env, addr); =20 @@ -370,8 +367,54 @@ void HELPER(itlbp)(CPUHPPAState *env, target_ulong add= r, target_ureg reg) qemu_log_mask(LOG_GUEST_ERROR, "ITLBP not following ITLBA\n"); return; } + set_access_bits_pa11(env, ent, reg); +} =20 - set_access_bits(env, ent, reg); +void HELPER(itlbt_pa20)(CPUHPPAState *env, target_ureg r1, target_ureg r2) +{ + hppa_tlb_entry *ent, *empty =3D NULL; + vaddr va_b, va_e; + uint64_t page_size; + + va_b =3D deposit64(env->cr[CR_IIAOQ], 32, 32, env->cr[CR_IIASQ]); + va_b &=3D TARGET_PAGE_MASK; + page_size =3D TARGET_PAGE_SIZE << (2 * (r1 & 0xf)); + va_e =3D va_b + page_size - 1; + + for (int i =3D 0; i < ARRAY_SIZE(env->tlb); ++i) { + ent =3D &env->tlb[i]; + if (ent->entry_valid) { + if (ent->va_b <=3D va_e && va_b <=3D ent->va_e) { + hppa_flush_tlb_ent(env, ent, false); + empty =3D ent; + } + } else { + empty =3D ent; + } + } + + /* If we didn't see an empty entry, evict one. */ + ent =3D empty ? empty : hppa_alloc_tlb_ent(env); + + ent->va_b =3D va_b; + ent->va_e =3D va_e; + ent->pa =3D (r1 << 7) & TARGET_PAGE_MASK; + ent->t =3D extract64(r2, 61, 1); + ent->d =3D extract64(r2, 60, 1); + ent->b =3D extract64(r2, 59, 1); + ent->ar_type =3D extract64(r2, 56, 3); + ent->ar_pl1 =3D extract64(r2, 54, 2); + ent->ar_pl2 =3D extract64(r2, 52, 2); + ent->u =3D extract64(r2, 51, 1); + /* o =3D bit 50 */ + /* p =3D bit 49 */ + ent->access_id =3D extract64(r2, 1, 31); + ent->entry_valid =3D 1; + + trace_hppa_tlb_itlba(env, ent, ent->va_b, ent->va_e, ent->pa); + trace_hppa_tlb_itlbp(env, ent, ent->access_id, ent->u, + ent->ar_pl2, ent->ar_pl1, ent->ar_type, + ent->b, ent->d, ent->t); } =20 /* Purge (Insn/Data) TLB. This is explicitly page-based, and is @@ -520,7 +563,7 @@ void HELPER(diag_btlb)(CPUHPPAState *env) btlb->va_b =3D virt_page << TARGET_PAGE_BITS; btlb->va_e =3D btlb->va_b + len * TARGET_PAGE_SIZE - 1; btlb->pa =3D phys_page << TARGET_PAGE_BITS; - set_access_bits(env, btlb, env->gr[20]); + set_access_bits_pa11(env, btlb, env->gr[20]); btlb->t =3D 0; btlb->d =3D 1; } else { diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 4a0ae5a772..44dcf310b6 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -2493,6 +2493,9 @@ static bool trans_probe(DisasContext *ctx, arg_probe = *a) =20 static bool trans_ixtlbx(DisasContext *ctx, arg_ixtlbx *a) { + if (ctx->is_pa20) { + return false; + } CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); #ifndef CONFIG_USER_ONLY TCGv_tl addr; @@ -2503,9 +2506,9 @@ static bool trans_ixtlbx(DisasContext *ctx, arg_ixtlb= x *a) form_gva(ctx, &addr, &ofs, a->b, 0, 0, 0, a->sp, 0, false); reg =3D load_gpr(ctx, a->r); if (a->addr) { - gen_helper_itlba(tcg_env, addr, reg); + gen_helper_itlba_pa11(tcg_env, addr, reg); } else { - gen_helper_itlbp(tcg_env, addr, reg); + gen_helper_itlbp_pa11(tcg_env, addr, reg); } =20 /* Exit TB for TLB change if mmu is enabled. */ @@ -2551,6 +2554,9 @@ static bool trans_pxtlbx(DisasContext *ctx, arg_pxtlb= x *a) */ static bool trans_ixtlbxf(DisasContext *ctx, arg_ixtlbxf *a) { + if (ctx->is_pa20) { + return false; + } CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); #ifndef CONFIG_USER_ONLY TCGv_tl addr, atl, stl; @@ -2562,8 +2568,6 @@ static bool trans_ixtlbxf(DisasContext *ctx, arg_ixtl= bxf *a) * FIXME: * if (not (pcxl or pcxl2)) * return gen_illegal(ctx); - * - * Note for future: these are 32-bit systems; no hppa64. */ =20 atl =3D tcg_temp_new_tl(); @@ -2581,9 +2585,9 @@ static bool trans_ixtlbxf(DisasContext *ctx, arg_ixtl= bxf *a) =20 reg =3D load_gpr(ctx, a->r); if (a->addr) { - gen_helper_itlba(tcg_env, addr, reg); + gen_helper_itlba_pa11(tcg_env, addr, reg); } else { - gen_helper_itlbp(tcg_env, addr, reg); + gen_helper_itlbp_pa11(tcg_env, addr, reg); } =20 /* Exit TB for TLB change if mmu is enabled. */ @@ -2594,6 +2598,25 @@ static bool trans_ixtlbxf(DisasContext *ctx, arg_ixt= lbxf *a) #endif } =20 +static bool trans_ixtlbt(DisasContext *ctx, arg_ixtlbt *a) +{ + if (!ctx->is_pa20) { + return false; + } + CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); +#ifndef CONFIG_USER_ONLY + nullify_over(ctx); + + gen_helper_itlbt_pa20(tcg_env, load_gpr(ctx, a->r1), load_gpr(ctx, a->= r2)); + + /* Exit TB for TLB change if mmu is enabled. */ + if (ctx->tb_flags & PSW_C) { + ctx->base.is_jmp =3D DISAS_IAQ_N_STALE; + } + return nullify_end(ctx); +#endif +} + static bool trans_lpa(DisasContext *ctx, arg_ldst *a) { CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); --=20 2.34.1 From nobody Wed Nov 27 18:51:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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Signed-off-by: Richard Henderson --- target/hppa/cpu-param.h | 1 - target/hppa/cpu.h | 50 ++++------- target/hppa/helper.h | 49 +++++------ target/hppa/cpu.c | 2 +- target/hppa/helper.c | 34 +++----- target/hppa/int_helper.c | 17 ++-- target/hppa/machine.c | 9 -- target/hppa/mem_helper.c | 10 +-- target/hppa/op_helper.c | 30 +++---- target/hppa/sys_helper.c | 4 +- target/hppa/translate.c | 184 ++++++++------------------------------- 11 files changed, 119 insertions(+), 271 deletions(-) diff --git a/target/hppa/cpu-param.h b/target/hppa/cpu-param.h index 2fb8e7924b..6746869a3b 100644 --- a/target/hppa/cpu-param.h +++ b/target/hppa/cpu-param.h @@ -9,7 +9,6 @@ #define HPPA_CPU_PARAM_H =20 #define TARGET_LONG_BITS 64 -#define TARGET_REGISTER_BITS 64 =20 #if defined(CONFIG_USER_ONLY) && defined(TARGET_ABI32) # define TARGET_PHYS_ADDR_SPACE_BITS 32 diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 251f85444a..5ce05046c0 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -141,22 +141,10 @@ #define CR_IPSW 22 #define CR_EIRR 23 =20 -#if TARGET_REGISTER_BITS =3D=3D 32 -typedef uint32_t target_ureg; -typedef int32_t target_sreg; -#define TREG_FMT_lx "%08"PRIx32 -#define TREG_FMT_ld "%"PRId32 -#else -typedef uint64_t target_ureg; -typedef int64_t target_sreg; -#define TREG_FMT_lx "%016"PRIx64 -#define TREG_FMT_ld "%"PRId64 -#endif - typedef struct { uint64_t va_b; uint64_t va_e; - target_ureg pa; + target_ulong pa; unsigned u : 1; unsigned t : 1; unsigned d : 1; @@ -170,16 +158,16 @@ typedef struct { } hppa_tlb_entry; =20 typedef struct CPUArchState { - target_ureg iaoq_f; /* front */ - target_ureg iaoq_b; /* back, aka next instruction */ + target_ulong iaoq_f; /* front */ + target_ulong iaoq_b; /* back, aka next instruction */ =20 - target_ureg gr[32]; + target_ulong gr[32]; uint64_t fr[32]; uint64_t sr[8]; /* stored shifted into place for gva */ =20 - target_ureg psw; /* All psw bits except the following: */ - target_ureg psw_n; /* boolean */ - target_sreg psw_v; /* in most significant bit */ + target_ulong psw; /* All psw bits except the following: */ + target_ulong psw_n; /* boolean */ + target_long psw_v; /* in most significant bit */ =20 /* Splitting the carry-borrow field into the MSB and "the rest", allows * for "the rest" to be deleted when it is unused, but the MSB is in u= se. @@ -188,8 +176,8 @@ typedef struct CPUArchState { * host has the appropriate add-with-carry insn to compute the msb). * Therefore the carry bits are stored as: cb_msb : cb & 0x11111110. */ - target_ureg psw_cb; /* in least significant bit of next nibble */ - target_ureg psw_cb_msb; /* boolean */ + target_ulong psw_cb; /* in least significant bit of next nibble */ + target_ulong psw_cb_msb; /* boolean */ =20 uint64_t iasq_f; uint64_t iasq_b; @@ -197,9 +185,9 @@ typedef struct CPUArchState { uint32_t fr0_shadow; /* flags, c, ca/cq, rm, d, enables */ float_status fp_status; =20 - target_ureg cr[32]; /* control registers */ - target_ureg cr_back[2]; /* back of cr17/cr18 */ - target_ureg shadow[7]; /* shadow registers */ + target_ulong cr[32]; /* control registers */ + target_ulong cr_back[2]; /* back of cr17/cr18 */ + target_ulong shadow[7]; /* shadow registers */ =20 /* * ??? The number of entries isn't specified by the architecture. @@ -257,8 +245,8 @@ void hppa_translate_init(void); =20 #define CPU_RESOLVING_TYPE TYPE_HPPA_CPU =20 -static inline target_ulong hppa_form_gva_psw(target_ureg psw, uint64_t spc, - target_ureg off) +static inline target_ulong hppa_form_gva_psw(target_ulong psw, uint64_t sp= c, + target_ulong off) { #ifdef CONFIG_USER_ONLY return off; @@ -269,7 +257,7 @@ static inline target_ulong hppa_form_gva_psw(target_ure= g psw, uint64_t spc, } =20 static inline target_ulong hppa_form_gva(CPUHPPAState *env, uint64_t spc, - target_ureg off) + target_ulong off) { return hppa_form_gva_psw(env->psw, spc, off); } @@ -313,8 +301,8 @@ static inline void cpu_get_tb_cpu_state(CPUHPPAState *e= nv, vaddr *pc, which is the primary case we care about -- using goto_tb within a p= age. Failure is indicated by a zero difference. */ if (env->iasq_f =3D=3D env->iasq_b) { - target_sreg diff =3D env->iaoq_b - env->iaoq_f; - if (TARGET_REGISTER_BITS =3D=3D 32 || diff =3D=3D (int32_t)diff) { + target_long diff =3D env->iaoq_b - env->iaoq_f; + if (diff =3D=3D (int32_t)diff) { *cs_base |=3D (uint32_t)diff; } } @@ -328,8 +316,8 @@ static inline void cpu_get_tb_cpu_state(CPUHPPAState *e= nv, vaddr *pc, *pflags =3D flags; } =20 -target_ureg cpu_hppa_get_psw(CPUHPPAState *env); -void cpu_hppa_put_psw(CPUHPPAState *env, target_ureg); +target_ulong cpu_hppa_get_psw(CPUHPPAState *env); +void cpu_hppa_put_psw(CPUHPPAState *env, target_ulong); void cpu_hppa_loaded_fr0(CPUHPPAState *env); =20 #ifdef CONFIG_USER_ONLY diff --git a/target/hppa/helper.h b/target/hppa/helper.h index 58b6754dbe..4b2c66316f 100644 --- a/target/hppa/helper.h +++ b/target/hppa/helper.h @@ -1,29 +1,20 @@ -#if TARGET_REGISTER_BITS =3D=3D 64 -# define dh_alias_tr i64 -# define dh_typecode_tr dh_typecode_i64 -#else -# define dh_alias_tr i32 -# define dh_typecode_tr dh_typecode_i32 -#endif -#define dh_ctype_tr target_ureg - DEF_HELPER_2(excp, noreturn, env, int) -DEF_HELPER_FLAGS_2(tsv, TCG_CALL_NO_WG, void, env, tr) -DEF_HELPER_FLAGS_2(tcond, TCG_CALL_NO_WG, void, env, tr) +DEF_HELPER_FLAGS_2(tsv, TCG_CALL_NO_WG, void, env, tl) +DEF_HELPER_FLAGS_2(tcond, TCG_CALL_NO_WG, void, env, tl) =20 -DEF_HELPER_FLAGS_3(stby_b, TCG_CALL_NO_WG, void, env, tl, tr) -DEF_HELPER_FLAGS_3(stby_b_parallel, TCG_CALL_NO_WG, void, env, tl, tr) -DEF_HELPER_FLAGS_3(stby_e, TCG_CALL_NO_WG, void, env, tl, tr) -DEF_HELPER_FLAGS_3(stby_e_parallel, TCG_CALL_NO_WG, void, env, tl, tr) +DEF_HELPER_FLAGS_3(stby_b, TCG_CALL_NO_WG, void, env, tl, tl) +DEF_HELPER_FLAGS_3(stby_b_parallel, TCG_CALL_NO_WG, void, env, tl, tl) +DEF_HELPER_FLAGS_3(stby_e, TCG_CALL_NO_WG, void, env, tl, tl) +DEF_HELPER_FLAGS_3(stby_e_parallel, TCG_CALL_NO_WG, void, env, tl, tl) =20 -DEF_HELPER_FLAGS_3(stdby_b, TCG_CALL_NO_WG, void, env, tl, tr) -DEF_HELPER_FLAGS_3(stdby_b_parallel, TCG_CALL_NO_WG, void, env, tl, tr) -DEF_HELPER_FLAGS_3(stdby_e, TCG_CALL_NO_WG, void, env, tl, tr) -DEF_HELPER_FLAGS_3(stdby_e_parallel, TCG_CALL_NO_WG, void, env, tl, tr) +DEF_HELPER_FLAGS_3(stdby_b, TCG_CALL_NO_WG, void, env, tl, tl) +DEF_HELPER_FLAGS_3(stdby_b_parallel, TCG_CALL_NO_WG, void, env, tl, tl) +DEF_HELPER_FLAGS_3(stdby_e, TCG_CALL_NO_WG, void, env, tl, tl) +DEF_HELPER_FLAGS_3(stdby_e_parallel, TCG_CALL_NO_WG, void, env, tl, tl) =20 DEF_HELPER_FLAGS_1(ldc_check, TCG_CALL_NO_RWG, void, tl) =20 -DEF_HELPER_FLAGS_4(probe, TCG_CALL_NO_WG, tr, env, tl, i32, i32) +DEF_HELPER_FLAGS_4(probe, TCG_CALL_NO_WG, tl, env, tl, i32, i32) =20 DEF_HELPER_FLAGS_1(loaded_fr0, TCG_CALL_NO_RWG, void, env) =20 @@ -82,7 +73,7 @@ DEF_HELPER_FLAGS_4(fmpynfadd_s, TCG_CALL_NO_RWG, i32, env= , i32, i32, i32) DEF_HELPER_FLAGS_4(fmpyfadd_d, TCG_CALL_NO_RWG, i64, env, i64, i64, i64) DEF_HELPER_FLAGS_4(fmpynfadd_d, TCG_CALL_NO_RWG, i64, env, i64, i64, i64) =20 -DEF_HELPER_FLAGS_0(read_interval_timer, TCG_CALL_NO_RWG, tr) +DEF_HELPER_FLAGS_0(read_interval_timer, TCG_CALL_NO_RWG, tl) =20 #ifndef CONFIG_USER_ONLY DEF_HELPER_1(halt, noreturn, env) @@ -90,16 +81,16 @@ DEF_HELPER_1(reset, noreturn, env) DEF_HELPER_1(getshadowregs, void, env) DEF_HELPER_1(rfi, void, env) DEF_HELPER_1(rfi_r, void, env) -DEF_HELPER_FLAGS_2(write_interval_timer, TCG_CALL_NO_RWG, void, env, tr) -DEF_HELPER_FLAGS_2(write_eirr, TCG_CALL_NO_RWG, void, env, tr) -DEF_HELPER_FLAGS_2(write_eiem, TCG_CALL_NO_RWG, void, env, tr) -DEF_HELPER_FLAGS_2(swap_system_mask, TCG_CALL_NO_RWG, tr, env, tr) -DEF_HELPER_FLAGS_3(itlba_pa11, TCG_CALL_NO_RWG, void, env, tl, tr) -DEF_HELPER_FLAGS_3(itlbp_pa11, TCG_CALL_NO_RWG, void, env, tl, tr) -DEF_HELPER_FLAGS_3(itlbt_pa20, TCG_CALL_NO_RWG, void, env, tr, tr) +DEF_HELPER_FLAGS_2(write_interval_timer, TCG_CALL_NO_RWG, void, env, tl) +DEF_HELPER_FLAGS_2(write_eirr, TCG_CALL_NO_RWG, void, env, tl) +DEF_HELPER_FLAGS_2(write_eiem, TCG_CALL_NO_RWG, void, env, tl) +DEF_HELPER_FLAGS_2(swap_system_mask, TCG_CALL_NO_RWG, tl, env, tl) +DEF_HELPER_FLAGS_3(itlba_pa11, TCG_CALL_NO_RWG, void, env, tl, tl) +DEF_HELPER_FLAGS_3(itlbp_pa11, TCG_CALL_NO_RWG, void, env, tl, tl) +DEF_HELPER_FLAGS_3(itlbt_pa20, TCG_CALL_NO_RWG, void, env, tl, tl) DEF_HELPER_FLAGS_2(ptlb, TCG_CALL_NO_RWG, void, env, tl) DEF_HELPER_FLAGS_1(ptlbe, TCG_CALL_NO_RWG, void, env) -DEF_HELPER_FLAGS_2(lpa, TCG_CALL_NO_WG, tr, env, tl) +DEF_HELPER_FLAGS_2(lpa, TCG_CALL_NO_WG, tl, env, tl) DEF_HELPER_FLAGS_1(change_prot_id, TCG_CALL_NO_RWG, void, env) DEF_HELPER_1(diag_btlb, void, env) #endif diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index bbb6080e2d..5654061a69 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -77,7 +77,7 @@ static void hppa_restore_state_to_opc(CPUState *cs, HPPACPU *cpu =3D HPPA_CPU(cs); =20 cpu->env.iaoq_f =3D data[0]; - if (data[1] !=3D (target_ureg)-1) { + if (data[1] !=3D (target_ulong)-1) { cpu->env.iaoq_b =3D data[1]; } /* diff --git a/target/hppa/helper.c b/target/hppa/helper.c index 04cdbafe9d..f112648764 100644 --- a/target/hppa/helper.c +++ b/target/hppa/helper.c @@ -25,31 +25,25 @@ #include "exec/helper-proto.h" #include "qemu/qemu-print.h" =20 -target_ureg cpu_hppa_get_psw(CPUHPPAState *env) +target_ulong cpu_hppa_get_psw(CPUHPPAState *env) { - target_ureg psw; - target_ureg mask1 =3D (target_ureg)-1 / 0xf; - target_ureg maskf =3D (target_ureg)-1 / 0xffff * 0xf; + target_ulong psw; + target_ulong mask1 =3D (target_ulong)-1 / 0xf; + target_ulong maskf =3D (target_ulong)-1 / 0xffff * 0xf; =20 /* Fold carry bits down to 8 consecutive bits. */ /* ^^^b^^^c^^^d^^^e^^^f^^^g^^^h^^^i^^^j^^^k^^^l^^^m^^^n^^^o^^^p^^^^ */ - /* ^^^b^^^c^^^d^^^e^^^f^^^g^^^h^^^^ */ psw =3D (env->psw_cb >> 4) & mask1; /* .......b...c...d...e...f...g...h...i...j...k...l...m...n...o...p */ - /* .......b...c...d...e...f...g...h */ psw |=3D psw >> 3; /* .......b..bc..cd..de..ef..fg..gh..hi..ij..jk..kl..lm..mn..no..op */ - /* .......b..bc..cd..de..ef..fg..gh */ psw |=3D psw >> 6; psw &=3D maskf; /* .............bcd............efgh............ijkl............mnop */ - /* .............bcd............efgh */ psw |=3D psw >> 12; /* .............bcd.........bcdefgh........efghijkl........ijklmnop */ - /* .............bcd.........bcdefgh */ - psw |=3D env->psw_cb_msb << (TARGET_REGISTER_BITS =3D=3D 64 ? 39 : 7); + psw |=3D env->psw_cb_msb << 39; /* .............bcd........abcdefgh........efghijkl........ijklmnop */ - /* .............bcd........abcdefgh */ =20 /* For hppa64, the two 8-bit fields are discontiguous. */ if (env_archcpu(env)->is_pa20) { @@ -65,11 +59,11 @@ target_ureg cpu_hppa_get_psw(CPUHPPAState *env) return psw; } =20 -void cpu_hppa_put_psw(CPUHPPAState *env, target_ureg psw) +void cpu_hppa_put_psw(CPUHPPAState *env, target_ulong psw) { uint64_t reserved; - target_ureg old_psw =3D env->psw; - target_ureg cb =3D 0; + target_ulong old_psw =3D env->psw; + target_ulong cb =3D 0; =20 /* Do not allow reserved bits to be set. */ if (env_archcpu(env)->is_pa20) { @@ -87,9 +81,6 @@ void cpu_hppa_put_psw(CPUHPPAState *env, target_ureg psw) env->psw_n =3D (psw / PSW_N) & 1; env->psw_v =3D -((psw / PSW_V) & 1); =20 -#if TARGET_REGISTER_BITS =3D=3D 32 - env->psw_cb_msb =3D (psw >> 15) & 1; -#else env->psw_cb_msb =3D (psw >> 39) & 1; cb |=3D ((psw >> 38) & 1) << 60; cb |=3D ((psw >> 37) & 1) << 56; @@ -99,7 +90,6 @@ void cpu_hppa_put_psw(CPUHPPAState *env, target_ureg psw) cb |=3D ((psw >> 33) & 1) << 40; cb |=3D ((psw >> 32) & 1) << 36; cb |=3D ((psw >> 15) & 1) << 32; -#endif cb |=3D ((psw >> 14) & 1) << 28; cb |=3D ((psw >> 13) & 1) << 24; cb |=3D ((psw >> 12) & 1) << 20; @@ -121,8 +111,8 @@ void hppa_cpu_dump_state(CPUState *cs, FILE *f, int fla= gs) { HPPACPU *cpu =3D HPPA_CPU(cs); CPUHPPAState *env =3D &cpu->env; - target_ureg psw =3D cpu_hppa_get_psw(env); - target_ureg psw_cb; + target_ulong psw =3D cpu_hppa_get_psw(env); + target_ulong psw_cb; char psw_c[20]; int i, w; uint64_t m; @@ -155,8 +145,8 @@ void hppa_cpu_dump_state(CPUState *cs, FILE *f, int fla= gs) psw_c[16] =3D (psw & PSW_D ? 'D' : '-'); psw_c[17] =3D (psw & PSW_I ? 'I' : '-'); psw_c[18] =3D '\0'; - psw_cb =3D ((env->psw_cb >> 4) & ((target_ureg)-1 / 0xf)) - | (env->psw_cb_msb << (TARGET_REGISTER_BITS - 4)); + psw_cb =3D ((env->psw_cb >> 4) & 0x1111111111111111ull) + | (env->psw_cb_msb << 60); =20 qemu_fprintf(f, "PSW %0*" PRIx64 " CB %0*" PRIx64 " %s\n", w, m & psw, w, m & psw_cb, psw_c); diff --git a/target/hppa/int_helper.c b/target/hppa/int_helper.c index 3ab9934a1d..f355c4c76b 100644 --- a/target/hppa/int_helper.c +++ b/target/hppa/int_helper.c @@ -52,9 +52,9 @@ static void io_eir_write(void *opaque, hwaddr addr, uint64_t data, unsigned size) { HPPACPU *cpu =3D opaque; - int le_bit =3D ~data & (TARGET_REGISTER_BITS - 1); + int le_bit =3D ~data & 31; =20 - cpu->env.cr[CR_EIRR] |=3D (target_ureg)1 << le_bit; + cpu->env.cr[CR_EIRR] |=3D (target_ulong)1 << le_bit; eval_interrupt(cpu); } =20 @@ -73,7 +73,7 @@ void hppa_cpu_alarm_timer(void *opaque) io_eir_write(opaque, 0, 0, 4); } =20 -void HELPER(write_eirr)(CPUHPPAState *env, target_ureg val) +void HELPER(write_eirr)(CPUHPPAState *env, target_ulong val) { env->cr[CR_EIRR] &=3D ~val; qemu_mutex_lock_iothread(); @@ -81,7 +81,7 @@ void HELPER(write_eirr)(CPUHPPAState *env, target_ureg va= l) qemu_mutex_unlock_iothread(); } =20 -void HELPER(write_eiem)(CPUHPPAState *env, target_ureg val) +void HELPER(write_eiem)(CPUHPPAState *env, target_ulong val) { env->cr[CR_EIEM] =3D val; qemu_mutex_lock_iothread(); @@ -94,12 +94,11 @@ void hppa_cpu_do_interrupt(CPUState *cs) HPPACPU *cpu =3D HPPA_CPU(cs); CPUHPPAState *env =3D &cpu->env; int i =3D cs->exception_index; - target_ureg iaoq_f =3D env->iaoq_f; - target_ureg iaoq_b =3D env->iaoq_b; + target_ulong iaoq_f =3D env->iaoq_f; + target_ulong iaoq_b =3D env->iaoq_b; uint64_t iasq_f =3D env->iasq_f; uint64_t iasq_b =3D env->iasq_b; - - target_ureg old_psw; + target_ulong old_psw; =20 /* As documented in pa2.0 -- interruption handling. */ /* step 1 */ @@ -240,7 +239,7 @@ void hppa_cpu_do_interrupt(CPUState *cs) name =3D unknown; } qemu_log("INT %6d: %s @ " TARGET_FMT_lx "," TARGET_FMT_lx - " -> " TREG_FMT_lx " " TARGET_FMT_lx "\n", + " -> " TARGET_FMT_lx " " TARGET_FMT_lx "\n", ++count, name, hppa_form_gva(env, iasq_f, iaoq_f), hppa_form_gva(env, iasq_b, iaoq_b), diff --git a/target/hppa/machine.c b/target/hppa/machine.c index 0c0bba68c0..ab34b72910 100644 --- a/target/hppa/machine.c +++ b/target/hppa/machine.c @@ -21,21 +21,12 @@ #include "cpu.h" #include "migration/cpu.h" =20 -#if TARGET_REGISTER_BITS =3D=3D 64 #define qemu_put_betr qemu_put_be64 #define qemu_get_betr qemu_get_be64 #define VMSTATE_UINTTR_V(_f, _s, _v) \ VMSTATE_UINT64_V(_f, _s, _v) #define VMSTATE_UINTTR_ARRAY_V(_f, _s, _n, _v) \ VMSTATE_UINT64_ARRAY_V(_f, _s, _n, _v) -#else -#define qemu_put_betr qemu_put_be32 -#define qemu_get_betr qemu_get_be32 -#define VMSTATE_UINTTR_V(_f, _s, _v) \ - VMSTATE_UINT32_V(_f, _s, _v) -#define VMSTATE_UINTTR_ARRAY_V(_f, _s, _n, _v) \ - VMSTATE_UINT32_ARRAY_V(_f, _s, _n, _v) -#endif =20 #define VMSTATE_UINTTR(_f, _s) \ VMSTATE_UINTTR_V(_f, _s, 0) diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c index d6f46b18e9..96fc3103f8 100644 --- a/target/hppa/mem_helper.c +++ b/target/hppa/mem_helper.c @@ -312,7 +312,7 @@ bool hppa_cpu_tlb_fill(CPUState *cs, vaddr addr, int si= ze, } =20 /* Insert (Insn/Data) TLB Address. Note this is PA 1.1 only. */ -void HELPER(itlba_pa11)(CPUHPPAState *env, target_ulong addr, target_ureg = reg) +void HELPER(itlba_pa11)(CPUHPPAState *env, target_ulong addr, target_ulong= reg) { hppa_tlb_entry *empty =3D NULL; int i; @@ -343,7 +343,7 @@ void HELPER(itlba_pa11)(CPUHPPAState *env, target_ulong= addr, target_ureg reg) } =20 static void set_access_bits_pa11(CPUHPPAState *env, hppa_tlb_entry *ent, - target_ureg reg) + target_ulong reg) { ent->access_id =3D extract32(reg, 1, 18); ent->u =3D extract32(reg, 19, 1); @@ -359,7 +359,7 @@ static void set_access_bits_pa11(CPUHPPAState *env, hpp= a_tlb_entry *ent, } =20 /* Insert (Insn/Data) TLB Protection. Note this is PA 1.1 only. */ -void HELPER(itlbp_pa11)(CPUHPPAState *env, target_ulong addr, target_ureg = reg) +void HELPER(itlbp_pa11)(CPUHPPAState *env, target_ulong addr, target_ulong= reg) { hppa_tlb_entry *ent =3D hppa_find_tlb(env, addr); =20 @@ -370,7 +370,7 @@ void HELPER(itlbp_pa11)(CPUHPPAState *env, target_ulong= addr, target_ureg reg) set_access_bits_pa11(env, ent, reg); } =20 -void HELPER(itlbt_pa20)(CPUHPPAState *env, target_ureg r1, target_ureg r2) +void HELPER(itlbt_pa20)(CPUHPPAState *env, target_ulong r1, target_ulong r= 2) { hppa_tlb_entry *ent, *empty =3D NULL; vaddr va_b, va_e; @@ -471,7 +471,7 @@ void HELPER(change_prot_id)(CPUHPPAState *env) cpu_hppa_change_prot_id(env); } =20 -target_ureg HELPER(lpa)(CPUHPPAState *env, target_ulong addr) +target_ulong HELPER(lpa)(CPUHPPAState *env, target_ulong addr) { hwaddr phys; int prot, excp; diff --git a/target/hppa/op_helper.c b/target/hppa/op_helper.c index 94c9ca5858..0bccca1e11 100644 --- a/target/hppa/op_helper.c +++ b/target/hppa/op_helper.c @@ -42,14 +42,14 @@ G_NORETURN void hppa_dynamic_excp(CPUHPPAState *env, in= t excp, uintptr_t ra) cpu_loop_exit_restore(cs, ra); } =20 -void HELPER(tsv)(CPUHPPAState *env, target_ureg cond) +void HELPER(tsv)(CPUHPPAState *env, target_ulong cond) { - if (unlikely((target_sreg)cond < 0)) { + if (unlikely((target_long)cond < 0)) { hppa_dynamic_excp(env, EXCP_OVERFLOW, GETPC()); } } =20 -void HELPER(tcond)(CPUHPPAState *env, target_ureg cond) +void HELPER(tcond)(CPUHPPAState *env, target_ulong cond) { if (unlikely(cond)) { hppa_dynamic_excp(env, EXCP_COND, GETPC()); @@ -110,7 +110,7 @@ static void atomic_store_mask64(CPUHPPAState *env, targ= et_ulong addr, #endif } =20 -static void do_stby_b(CPUHPPAState *env, target_ulong addr, target_ureg va= l, +static void do_stby_b(CPUHPPAState *env, target_ulong addr, target_ulong v= al, bool parallel, uintptr_t ra) { switch (addr & 3) { @@ -191,29 +191,29 @@ static void do_stdby_b(CPUHPPAState *env, target_ulon= g addr, uint64_t val, } } =20 -void HELPER(stby_b)(CPUHPPAState *env, target_ulong addr, target_ureg val) +void HELPER(stby_b)(CPUHPPAState *env, target_ulong addr, target_ulong val) { do_stby_b(env, addr, val, false, GETPC()); } =20 void HELPER(stby_b_parallel)(CPUHPPAState *env, target_ulong addr, - target_ureg val) + target_ulong val) { do_stby_b(env, addr, val, true, GETPC()); } =20 -void HELPER(stdby_b)(CPUHPPAState *env, target_ulong addr, target_ureg val) +void HELPER(stdby_b)(CPUHPPAState *env, target_ulong addr, target_ulong va= l) { do_stdby_b(env, addr, val, false, GETPC()); } =20 void HELPER(stdby_b_parallel)(CPUHPPAState *env, target_ulong addr, - target_ureg val) + target_ulong val) { do_stdby_b(env, addr, val, true, GETPC()); } =20 -static void do_stby_e(CPUHPPAState *env, target_ulong addr, target_ureg va= l, +static void do_stby_e(CPUHPPAState *env, target_ulong addr, target_ulong v= al, bool parallel, uintptr_t ra) { switch (addr & 3) { @@ -301,24 +301,24 @@ static void do_stdby_e(CPUHPPAState *env, target_ulon= g addr, uint64_t val, } } =20 -void HELPER(stby_e)(CPUHPPAState *env, target_ulong addr, target_ureg val) +void HELPER(stby_e)(CPUHPPAState *env, target_ulong addr, target_ulong val) { do_stby_e(env, addr, val, false, GETPC()); } =20 void HELPER(stby_e_parallel)(CPUHPPAState *env, target_ulong addr, - target_ureg val) + target_ulong val) { do_stby_e(env, addr, val, true, GETPC()); } =20 -void HELPER(stdby_e)(CPUHPPAState *env, target_ulong addr, target_ureg val) +void HELPER(stdby_e)(CPUHPPAState *env, target_ulong addr, target_ulong va= l) { do_stdby_e(env, addr, val, false, GETPC()); } =20 void HELPER(stdby_e_parallel)(CPUHPPAState *env, target_ulong addr, - target_ureg val) + target_ulong val) { do_stdby_e(env, addr, val, true, GETPC()); } @@ -332,7 +332,7 @@ void HELPER(ldc_check)(target_ulong addr) } } =20 -target_ureg HELPER(probe)(CPUHPPAState *env, target_ulong addr, +target_ulong HELPER(probe)(CPUHPPAState *env, target_ulong addr, uint32_t level, uint32_t want) { #ifdef CONFIG_USER_ONLY @@ -364,7 +364,7 @@ target_ureg HELPER(probe)(CPUHPPAState *env, target_ulo= ng addr, #endif } =20 -target_ureg HELPER(read_interval_timer)(void) +target_ulong HELPER(read_interval_timer)(void) { #ifdef CONFIG_USER_ONLY /* In user-mode, QEMU_CLOCK_VIRTUAL doesn't exist. diff --git a/target/hppa/sys_helper.c b/target/hppa/sys_helper.c index f0dd5a08e7..bb57413199 100644 --- a/target/hppa/sys_helper.c +++ b/target/hppa/sys_helper.c @@ -24,7 +24,7 @@ #include "qemu/timer.h" #include "sysemu/runstate.h" =20 -void HELPER(write_interval_timer)(CPUHPPAState *env, target_ureg val) +void HELPER(write_interval_timer)(CPUHPPAState *env, target_ulong val) { HPPACPU *cpu =3D env_archcpu(env); uint64_t current =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); @@ -58,7 +58,7 @@ void HELPER(reset)(CPUHPPAState *env) helper_excp(env, EXCP_HLT); } =20 -target_ureg HELPER(swap_system_mask)(CPUHPPAState *env, target_ureg nsm) +target_ulong HELPER(swap_system_mask)(CPUHPPAState *env, target_ulong nsm) { target_ulong psw =3D env->psw; /* diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 44dcf310b6..46a9e83508 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -40,21 +40,10 @@ #undef tcg_temp_new #undef tcg_global_mem_new =20 -#if TARGET_LONG_BITS =3D=3D 64 #define TCGv_tl TCGv_i64 #define tcg_temp_new_tl tcg_temp_new_i64 -#if TARGET_REGISTER_BITS =3D=3D 64 #define tcg_gen_extu_reg_tl tcg_gen_mov_i64 -#else -#define tcg_gen_extu_reg_tl tcg_gen_extu_i32_i64 -#endif -#else -#define TCGv_tl TCGv_i32 -#define tcg_temp_new_tl tcg_temp_new_i32 -#define tcg_gen_extu_reg_tl tcg_gen_mov_i32 -#endif =20 -#if TARGET_REGISTER_BITS =3D=3D 64 #define TCGv_reg TCGv_i64 =20 #define tcg_temp_new tcg_temp_new_i64 @@ -147,98 +136,6 @@ #define tcg_gen_qemu_st_reg tcg_gen_qemu_st_i64 #define tcg_gen_atomic_xchg_reg tcg_gen_atomic_xchg_i64 #define tcg_gen_trunc_reg_ptr tcg_gen_trunc_i64_ptr -#else -#define TCGv_reg TCGv_i32 -#define tcg_temp_new tcg_temp_new_i32 -#define tcg_global_mem_new tcg_global_mem_new_i32 - -#define tcg_gen_movi_reg tcg_gen_movi_i32 -#define tcg_gen_mov_reg tcg_gen_mov_i32 -#define tcg_gen_ld8u_reg tcg_gen_ld8u_i32 -#define tcg_gen_ld8s_reg tcg_gen_ld8s_i32 -#define tcg_gen_ld16u_reg tcg_gen_ld16u_i32 -#define tcg_gen_ld16s_reg tcg_gen_ld16s_i32 -#define tcg_gen_ld32u_reg tcg_gen_ld_i32 -#define tcg_gen_ld32s_reg tcg_gen_ld_i32 -#define tcg_gen_ld_reg tcg_gen_ld_i32 -#define tcg_gen_st8_reg tcg_gen_st8_i32 -#define tcg_gen_st16_reg tcg_gen_st16_i32 -#define tcg_gen_st32_reg tcg_gen_st32_i32 -#define tcg_gen_st_reg tcg_gen_st_i32 -#define tcg_gen_add_reg tcg_gen_add_i32 -#define tcg_gen_addi_reg tcg_gen_addi_i32 -#define tcg_gen_sub_reg tcg_gen_sub_i32 -#define tcg_gen_neg_reg tcg_gen_neg_i32 -#define tcg_gen_subfi_reg tcg_gen_subfi_i32 -#define tcg_gen_subi_reg tcg_gen_subi_i32 -#define tcg_gen_and_reg tcg_gen_and_i32 -#define tcg_gen_andi_reg tcg_gen_andi_i32 -#define tcg_gen_or_reg tcg_gen_or_i32 -#define tcg_gen_ori_reg tcg_gen_ori_i32 -#define tcg_gen_xor_reg tcg_gen_xor_i32 -#define tcg_gen_xori_reg tcg_gen_xori_i32 -#define tcg_gen_not_reg tcg_gen_not_i32 -#define tcg_gen_shl_reg tcg_gen_shl_i32 -#define tcg_gen_shli_reg tcg_gen_shli_i32 -#define tcg_gen_shr_reg tcg_gen_shr_i32 -#define tcg_gen_shri_reg tcg_gen_shri_i32 -#define tcg_gen_sar_reg tcg_gen_sar_i32 -#define tcg_gen_sari_reg tcg_gen_sari_i32 -#define tcg_gen_brcond_reg tcg_gen_brcond_i32 -#define tcg_gen_brcondi_reg tcg_gen_brcondi_i32 -#define tcg_gen_setcond_reg tcg_gen_setcond_i32 -#define tcg_gen_setcondi_reg tcg_gen_setcondi_i32 -#define tcg_gen_mul_reg tcg_gen_mul_i32 -#define tcg_gen_muli_reg tcg_gen_muli_i32 -#define tcg_gen_div_reg tcg_gen_div_i32 -#define tcg_gen_rem_reg tcg_gen_rem_i32 -#define tcg_gen_divu_reg tcg_gen_divu_i32 -#define tcg_gen_remu_reg tcg_gen_remu_i32 -#define tcg_gen_discard_reg tcg_gen_discard_i32 -#define tcg_gen_trunc_reg_i32 tcg_gen_mov_i32 -#define tcg_gen_trunc_i64_reg tcg_gen_extrl_i64_i32 -#define tcg_gen_extu_i32_reg tcg_gen_mov_i32 -#define tcg_gen_ext_i32_reg tcg_gen_mov_i32 -#define tcg_gen_extu_reg_i64 tcg_gen_extu_i32_i64 -#define tcg_gen_ext_reg_i64 tcg_gen_ext_i32_i64 -#define tcg_gen_ext8u_reg tcg_gen_ext8u_i32 -#define tcg_gen_ext8s_reg tcg_gen_ext8s_i32 -#define tcg_gen_ext16u_reg tcg_gen_ext16u_i32 -#define tcg_gen_ext16s_reg tcg_gen_ext16s_i32 -#define tcg_gen_ext32u_reg tcg_gen_mov_i32 -#define tcg_gen_ext32s_reg tcg_gen_mov_i32 -#define tcg_gen_bswap16_reg tcg_gen_bswap16_i32 -#define tcg_gen_bswap32_reg tcg_gen_bswap32_i32 -#define tcg_gen_concat_reg_i64 tcg_gen_concat_i32_i64 -#define tcg_gen_andc_reg tcg_gen_andc_i32 -#define tcg_gen_eqv_reg tcg_gen_eqv_i32 -#define tcg_gen_nand_reg tcg_gen_nand_i32 -#define tcg_gen_nor_reg tcg_gen_nor_i32 -#define tcg_gen_orc_reg tcg_gen_orc_i32 -#define tcg_gen_clz_reg tcg_gen_clz_i32 -#define tcg_gen_ctz_reg tcg_gen_ctz_i32 -#define tcg_gen_clzi_reg tcg_gen_clzi_i32 -#define tcg_gen_ctzi_reg tcg_gen_ctzi_i32 -#define tcg_gen_clrsb_reg tcg_gen_clrsb_i32 -#define tcg_gen_ctpop_reg tcg_gen_ctpop_i32 -#define tcg_gen_rotl_reg tcg_gen_rotl_i32 -#define tcg_gen_rotli_reg tcg_gen_rotli_i32 -#define tcg_gen_rotr_reg tcg_gen_rotr_i32 -#define tcg_gen_rotri_reg tcg_gen_rotri_i32 -#define tcg_gen_deposit_reg tcg_gen_deposit_i32 -#define tcg_gen_deposit_z_reg tcg_gen_deposit_z_i32 -#define tcg_gen_extract_reg tcg_gen_extract_i32 -#define tcg_gen_sextract_reg tcg_gen_sextract_i32 -#define tcg_gen_extract2_reg tcg_gen_extract2_i32 -#define tcg_constant_reg tcg_constant_i32 -#define tcg_gen_movcond_reg tcg_gen_movcond_i32 -#define tcg_gen_add2_reg tcg_gen_add2_i32 -#define tcg_gen_sub2_reg tcg_gen_sub2_i32 -#define tcg_gen_qemu_ld_reg tcg_gen_qemu_ld_i32 -#define tcg_gen_qemu_st_reg tcg_gen_qemu_st_i32 -#define tcg_gen_atomic_xchg_reg tcg_gen_atomic_xchg_i32 -#define tcg_gen_trunc_reg_ptr tcg_gen_ext_i32_ptr -#endif /* TARGET_REGISTER_BITS */ =20 typedef struct DisasCond { TCGCond c; @@ -249,9 +146,9 @@ typedef struct DisasContext { DisasContextBase base; CPUState *cs; =20 - target_ureg iaoq_f; - target_ureg iaoq_b; - target_ureg iaoq_n; + uint64_t iaoq_f; + uint64_t iaoq_b; + uint64_t iaoq_n; TCGv_reg iaoq_n_var; =20 DisasCond null_cond; @@ -727,7 +624,7 @@ static bool nullify_end(DisasContext *ctx) return true; } =20 -static void copy_iaoq_entry(TCGv_reg dest, target_ureg ival, TCGv_reg vval) +static void copy_iaoq_entry(TCGv_reg dest, uint64_t ival, TCGv_reg vval) { if (unlikely(ival =3D=3D -1)) { tcg_gen_mov_reg(dest, vval); @@ -736,7 +633,7 @@ static void copy_iaoq_entry(TCGv_reg dest, target_ureg = ival, TCGv_reg vval) } } =20 -static inline target_ureg iaoq_dest(DisasContext *ctx, target_sreg disp) +static inline uint64_t iaoq_dest(DisasContext *ctx, int64_t disp) { return ctx->iaoq_f + disp + 8; } @@ -781,14 +678,14 @@ static bool gen_illegal(DisasContext *ctx) } while (0) #endif =20 -static target_ureg gva_offset_mask(DisasContext *ctx) +static uint64_t gva_offset_mask(DisasContext *ctx) { return (ctx->tb_flags & PSW_W ? MAKE_64BIT_MASK(0, 62) : MAKE_64BIT_MASK(0, 32)); } =20 -static bool use_goto_tb(DisasContext *ctx, target_ureg dest) +static bool use_goto_tb(DisasContext *ctx, uint64_t dest) { return translator_use_goto_tb(&ctx->base, dest); } @@ -804,7 +701,7 @@ static bool use_nullify_skip(DisasContext *ctx) } =20 static void gen_goto_tb(DisasContext *ctx, int which, - target_ureg f, target_ureg b) + uint64_t f, uint64_t b) { if (f !=3D -1 && b !=3D -1 && use_goto_tb(ctx, f)) { tcg_gen_goto_tb(which); @@ -831,7 +728,7 @@ static bool cond_need_cb(int c) /* Need extensions from TCGv_i32 to TCGv_reg. */ static bool cond_need_ext(DisasContext *ctx, bool d) { - return TARGET_REGISTER_BITS =3D=3D 64 && !(ctx->is_pa20 && d); + return !(ctx->is_pa20 && d); } =20 /* @@ -882,7 +779,7 @@ static DisasCond do_cond(DisasContext *ctx, unsigned cf= , bool d, tcg_gen_and_reg(tmp, tmp, res); tcg_gen_ext32u_reg(tmp, tmp); } else { - tcg_gen_sari_reg(tmp, tmp, TARGET_REGISTER_BITS - 1); + tcg_gen_sari_reg(tmp, tmp, 63); tcg_gen_and_reg(tmp, tmp, res); } cond =3D cond_make_0_tmp(TCG_COND_EQ, tmp); @@ -1078,7 +975,7 @@ static DisasCond do_unit_cond(unsigned cf, bool d, TCG= v_reg res, { DisasCond cond; TCGv_reg tmp, cb =3D NULL; - target_ureg d_repl =3D d ? 0x0000000100000001ull : 1; + uint64_t d_repl =3D d ? 0x0000000100000001ull : 1; =20 if (cf & 8) { /* Since we want to test lots of carry-out bits all at once, do not @@ -1509,7 +1406,7 @@ static TCGv_i64 space_select(DisasContext *ctx, int s= p, TCGv_reg base) #endif =20 static void form_gva(DisasContext *ctx, TCGv_tl *pgva, TCGv_reg *pofs, - unsigned rb, unsigned rx, int scale, target_sreg disp, + unsigned rb, unsigned rx, int scale, int64_t disp, unsigned sp, int modify, bool is_phys) { TCGv_reg base =3D load_gpr(ctx, rb); @@ -1545,7 +1442,7 @@ static void form_gva(DisasContext *ctx, TCGv_tl *pgva= , TCGv_reg *pofs, * =3D 0 for no base register update. */ static void do_load_32(DisasContext *ctx, TCGv_i32 dest, unsigned rb, - unsigned rx, int scale, target_sreg disp, + unsigned rx, int scale, int64_t disp, unsigned sp, int modify, MemOp mop) { TCGv_reg ofs; @@ -1563,7 +1460,7 @@ static void do_load_32(DisasContext *ctx, TCGv_i32 de= st, unsigned rb, } =20 static void do_load_64(DisasContext *ctx, TCGv_i64 dest, unsigned rb, - unsigned rx, int scale, target_sreg disp, + unsigned rx, int scale, int64_t disp, unsigned sp, int modify, MemOp mop) { TCGv_reg ofs; @@ -1581,7 +1478,7 @@ static void do_load_64(DisasContext *ctx, TCGv_i64 de= st, unsigned rb, } =20 static void do_store_32(DisasContext *ctx, TCGv_i32 src, unsigned rb, - unsigned rx, int scale, target_sreg disp, + unsigned rx, int scale, int64_t disp, unsigned sp, int modify, MemOp mop) { TCGv_reg ofs; @@ -1599,7 +1496,7 @@ static void do_store_32(DisasContext *ctx, TCGv_i32 s= rc, unsigned rb, } =20 static void do_store_64(DisasContext *ctx, TCGv_i64 src, unsigned rb, - unsigned rx, int scale, target_sreg disp, + unsigned rx, int scale, int64_t disp, unsigned sp, int modify, MemOp mop) { TCGv_reg ofs; @@ -1616,16 +1513,11 @@ static void do_store_64(DisasContext *ctx, TCGv_i64= src, unsigned rb, } } =20 -#if TARGET_REGISTER_BITS =3D=3D 64 #define do_load_reg do_load_64 #define do_store_reg do_store_64 -#else -#define do_load_reg do_load_32 -#define do_store_reg do_store_32 -#endif =20 static bool do_load(DisasContext *ctx, unsigned rt, unsigned rb, - unsigned rx, int scale, target_sreg disp, + unsigned rx, int scale, int64_t disp, unsigned sp, int modify, MemOp mop) { TCGv_reg dest; @@ -1646,7 +1538,7 @@ static bool do_load(DisasContext *ctx, unsigned rt, u= nsigned rb, } =20 static bool do_floadw(DisasContext *ctx, unsigned rt, unsigned rb, - unsigned rx, int scale, target_sreg disp, + unsigned rx, int scale, int64_t disp, unsigned sp, int modify) { TCGv_i32 tmp; @@ -1671,7 +1563,7 @@ static bool trans_fldw(DisasContext *ctx, arg_ldst *a) } =20 static bool do_floadd(DisasContext *ctx, unsigned rt, unsigned rb, - unsigned rx, int scale, target_sreg disp, + unsigned rx, int scale, int64_t disp, unsigned sp, int modify) { TCGv_i64 tmp; @@ -1696,7 +1588,7 @@ static bool trans_fldd(DisasContext *ctx, arg_ldst *a) } =20 static bool do_store(DisasContext *ctx, unsigned rt, unsigned rb, - target_sreg disp, unsigned sp, + int64_t disp, unsigned sp, int modify, MemOp mop) { nullify_over(ctx); @@ -1705,7 +1597,7 @@ static bool do_store(DisasContext *ctx, unsigned rt, = unsigned rb, } =20 static bool do_fstorew(DisasContext *ctx, unsigned rt, unsigned rb, - unsigned rx, int scale, target_sreg disp, + unsigned rx, int scale, int64_t disp, unsigned sp, int modify) { TCGv_i32 tmp; @@ -1725,7 +1617,7 @@ static bool trans_fstw(DisasContext *ctx, arg_ldst *a) } =20 static bool do_fstored(DisasContext *ctx, unsigned rt, unsigned rb, - unsigned rx, int scale, target_sreg disp, + unsigned rx, int scale, int64_t disp, unsigned sp, int modify) { TCGv_i64 tmp; @@ -1838,7 +1730,7 @@ static bool do_fop_dedd(DisasContext *ctx, unsigned r= t, =20 /* Emit an unconditional branch to a direct target, which may or may not have already had nullification handled. */ -static bool do_dbranch(DisasContext *ctx, target_ureg dest, +static bool do_dbranch(DisasContext *ctx, uint64_t dest, unsigned link, bool is_n) { if (ctx->null_cond.c =3D=3D TCG_COND_NEVER && ctx->null_lab =3D=3D NUL= L) { @@ -1875,10 +1767,10 @@ static bool do_dbranch(DisasContext *ctx, target_ur= eg dest, =20 /* Emit a conditional branch to a direct target. If the branch itself is nullified, we should have already used nullify_over. */ -static bool do_cbranch(DisasContext *ctx, target_sreg disp, bool is_n, +static bool do_cbranch(DisasContext *ctx, int64_t disp, bool is_n, DisasCond *cond) { - target_ureg dest =3D iaoq_dest(ctx, disp); + uint64_t dest =3D iaoq_dest(ctx, disp); TCGLabel *taken =3D NULL; TCGCond c =3D cond->c; bool n; @@ -2839,7 +2731,7 @@ static bool do_dcor(DisasContext *ctx, arg_rr_cf_d *a= , bool is_i) if (!is_i) { tcg_gen_not_reg(tmp, tmp); } - tcg_gen_andi_reg(tmp, tmp, (target_ureg)0x1111111111111111ull); + tcg_gen_andi_reg(tmp, tmp, (uint64_t)0x1111111111111111ull); tcg_gen_muli_reg(tmp, tmp, 6); do_unit(ctx, a->t, load_gpr(ctx, a->r), tmp, a->cf, a->d, false, is_i ? tcg_gen_add_reg : tcg_gen_sub_reg); @@ -2961,22 +2853,20 @@ static bool trans_cmpiclr(DisasContext *ctx, arg_rr= i_cf_d *a) =20 static bool trans_ld(DisasContext *ctx, arg_ldst *a) { - if (unlikely(TARGET_REGISTER_BITS =3D=3D 32 && a->size > MO_32)) { + if (!ctx->is_pa20 && a->size > MO_32) { return gen_illegal(ctx); - } else { - return do_load(ctx, a->t, a->b, a->x, a->scale ? a->size : 0, - a->disp, a->sp, a->m, a->size | MO_TE); } + return do_load(ctx, a->t, a->b, a->x, a->scale ? a->size : 0, + a->disp, a->sp, a->m, a->size | MO_TE); } =20 static bool trans_st(DisasContext *ctx, arg_ldst *a) { assert(a->x =3D=3D 0 && a->scale =3D=3D 0); - if (unlikely(TARGET_REGISTER_BITS =3D=3D 32 && a->size > MO_32)) { + if (!ctx->is_pa20 && a->size > MO_32) { return gen_illegal(ctx); - } else { - return do_store(ctx, a->t, a->b, a->disp, a->sp, a->m, a->size | M= O_TE); } + return do_store(ctx, a->t, a->b, a->disp, a->sp, a->m, a->size | MO_TE= ); } =20 static bool trans_ldc(DisasContext *ctx, arg_ldst *a) @@ -2985,7 +2875,7 @@ static bool trans_ldc(DisasContext *ctx, arg_ldst *a) TCGv_reg zero, dest, ofs; TCGv_tl addr; =20 - if (unlikely(TARGET_REGISTER_BITS =3D=3D 32 && a->size > MO_32)) { + if (!ctx->is_pa20 && a->size > MO_32) { return gen_illegal(ctx); } =20 @@ -3394,7 +3284,7 @@ static bool trans_shrp_imm(DisasContext *ctx, arg_shr= p_imm *a) t2 =3D load_gpr(ctx, a->r2); if (a->r1 =3D=3D 0) { tcg_gen_extract_reg(dest, t2, sa, width - sa); - } else if (width =3D=3D TARGET_REGISTER_BITS) { + } else if (width =3D=3D TARGET_LONG_BITS) { tcg_gen_extract2_reg(dest, t2, cpu_gr[a->r1], sa); } else { assert(!a->d); @@ -3496,7 +3386,7 @@ static bool trans_extr_imm(DisasContext *ctx, arg_ext= r_imm *a) static bool trans_depi_imm(DisasContext *ctx, arg_depi_imm *a) { unsigned len, width; - target_sreg mask0, mask1; + uint64_t mask0, mask1; TCGv_reg dest; =20 if (!ctx->is_pa20 && a->d) { @@ -3575,7 +3465,7 @@ static bool do_dep_sar(DisasContext *ctx, unsigned rt= , unsigned c, unsigned rs =3D nz ? rt : 0; unsigned widthm1 =3D d ? 63 : 31; TCGv_reg mask, tmp, shift, dest; - target_ureg msb =3D 1ULL << (len - 1); + uint64_t msb =3D 1ULL << (len - 1); =20 dest =3D dest_gpr(ctx, rt); shift =3D tcg_temp_new(); @@ -3691,7 +3581,7 @@ static bool trans_bl(DisasContext *ctx, arg_bl *a) =20 static bool trans_b_gate(DisasContext *ctx, arg_b_gate *a) { - target_ureg dest =3D iaoq_dest(ctx, a->disp); + uint64_t dest =3D iaoq_dest(ctx, a->disp); =20 nullify_over(ctx); =20 @@ -3819,7 +3709,7 @@ static bool trans_fid_f(DisasContext *ctx, arg_fid_f = *a) { uint64_t ret; =20 - if (TARGET_REGISTER_BITS =3D=3D 64) { + if (ctx->is_pa20) { ret =3D 0x13080000000000ULL; /* PA8700 (PCX-W2) */ } else { ret =3D 0x0f080000000000ULL; /* PA7300LC (PCX-L2) */ --=20 2.34.1 From nobody Wed Nov 27 18:51:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1697666352; cv=none; d=zohomail.com; s=zohoarc; b=eEtnjBAR8uES8kUu2PXbs2eTvkBIomqaPw7SHyLpKdwYgVLVjUR/SRbI10GYE4G22CVwtgM/0l4TtIBirobbg/jPPXZ0PF9AGylTwDJtGWdwXev3DdqbTfapF8k0RyEYzS2D8m5WJzB4ePIB7QYoss1A+z/2WK4SCT2gmbrWmFk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1697666352; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=q9TNZKzal6yLNupWTK1p/wqsexoknREObFDjNpGRjb0=; b=fCsYPFtuBxCI9ezpvuj74Bgn9iEUm3eGU1dolcgG2vbX5/4umc1yzXKtY1ImbcMR12I4QoN3URoNJOU84ZBWMNXzEV6/JiTgJ1dZTcJcsY9iBlBesg6hDnJLc3h1qQ8gGjaaKyYx3Qrm50JrQUOfuFASqYAs/RDXsNHqvyEXzUY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1697666352668844.5269371113034; Wed, 18 Oct 2023 14:59:12 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qtEVg-0002D5-2w; Wed, 18 Oct 2023 17:55:24 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qtEVe-0002CK-NU for qemu-devel@nongnu.org; Wed, 18 Oct 2023 17:55:22 -0400 Received: from mail-ot1-x32a.google.com ([2607:f8b0:4864:20::32a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qtEVa-00051T-1E for qemu-devel@nongnu.org; Wed, 18 Oct 2023 17:55:22 -0400 Received: by mail-ot1-x32a.google.com with SMTP id 46e09a7af769-6b9e478e122so5074940a34.1 for ; Wed, 18 Oct 2023 14:55:17 -0700 (PDT) Received: from stoup.. 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Signed-off-by: Richard Henderson --- target/hppa/translate.c | 914 ++++++++++++++++++---------------------- 1 file changed, 408 insertions(+), 506 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 46a9e83508..682cb518d6 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -36,110 +36,15 @@ /* Since we have a distinction between register size and address size, we need to redefine all of these. */ =20 -#undef TCGv -#undef tcg_temp_new -#undef tcg_global_mem_new - -#define TCGv_tl TCGv_i64 -#define tcg_temp_new_tl tcg_temp_new_i64 #define tcg_gen_extu_reg_tl tcg_gen_mov_i64 - -#define TCGv_reg TCGv_i64 - -#define tcg_temp_new tcg_temp_new_i64 -#define tcg_global_mem_new tcg_global_mem_new_i64 - -#define tcg_gen_movi_reg tcg_gen_movi_i64 -#define tcg_gen_mov_reg tcg_gen_mov_i64 -#define tcg_gen_ld8u_reg tcg_gen_ld8u_i64 -#define tcg_gen_ld8s_reg tcg_gen_ld8s_i64 -#define tcg_gen_ld16u_reg tcg_gen_ld16u_i64 -#define tcg_gen_ld16s_reg tcg_gen_ld16s_i64 -#define tcg_gen_ld32u_reg tcg_gen_ld32u_i64 -#define tcg_gen_ld32s_reg tcg_gen_ld32s_i64 -#define tcg_gen_ld_reg tcg_gen_ld_i64 -#define tcg_gen_st8_reg tcg_gen_st8_i64 -#define tcg_gen_st16_reg tcg_gen_st16_i64 -#define tcg_gen_st32_reg tcg_gen_st32_i64 -#define tcg_gen_st_reg tcg_gen_st_i64 -#define tcg_gen_add_reg tcg_gen_add_i64 -#define tcg_gen_addi_reg tcg_gen_addi_i64 -#define tcg_gen_sub_reg tcg_gen_sub_i64 -#define tcg_gen_neg_reg tcg_gen_neg_i64 -#define tcg_gen_subfi_reg tcg_gen_subfi_i64 -#define tcg_gen_subi_reg tcg_gen_subi_i64 -#define tcg_gen_and_reg tcg_gen_and_i64 -#define tcg_gen_andi_reg tcg_gen_andi_i64 -#define tcg_gen_or_reg tcg_gen_or_i64 -#define tcg_gen_ori_reg tcg_gen_ori_i64 -#define tcg_gen_xor_reg tcg_gen_xor_i64 -#define tcg_gen_xori_reg tcg_gen_xori_i64 -#define tcg_gen_not_reg tcg_gen_not_i64 -#define tcg_gen_shl_reg tcg_gen_shl_i64 -#define tcg_gen_shli_reg tcg_gen_shli_i64 -#define tcg_gen_shr_reg tcg_gen_shr_i64 -#define tcg_gen_shri_reg tcg_gen_shri_i64 -#define tcg_gen_sar_reg tcg_gen_sar_i64 -#define tcg_gen_sari_reg tcg_gen_sari_i64 -#define tcg_gen_brcond_reg tcg_gen_brcond_i64 -#define tcg_gen_brcondi_reg tcg_gen_brcondi_i64 -#define tcg_gen_setcond_reg tcg_gen_setcond_i64 -#define tcg_gen_setcondi_reg tcg_gen_setcondi_i64 -#define tcg_gen_mul_reg tcg_gen_mul_i64 -#define tcg_gen_muli_reg tcg_gen_muli_i64 -#define tcg_gen_div_reg tcg_gen_div_i64 -#define tcg_gen_rem_reg tcg_gen_rem_i64 -#define tcg_gen_divu_reg tcg_gen_divu_i64 -#define tcg_gen_remu_reg tcg_gen_remu_i64 -#define tcg_gen_discard_reg tcg_gen_discard_i64 -#define tcg_gen_trunc_reg_i32 tcg_gen_extrl_i64_i32 #define tcg_gen_trunc_i64_reg tcg_gen_mov_i64 -#define tcg_gen_extu_i32_reg tcg_gen_extu_i32_i64 -#define tcg_gen_ext_i32_reg tcg_gen_ext_i32_i64 #define tcg_gen_extu_reg_i64 tcg_gen_mov_i64 #define tcg_gen_ext_reg_i64 tcg_gen_mov_i64 -#define tcg_gen_ext8u_reg tcg_gen_ext8u_i64 -#define tcg_gen_ext8s_reg tcg_gen_ext8s_i64 -#define tcg_gen_ext16u_reg tcg_gen_ext16u_i64 -#define tcg_gen_ext16s_reg tcg_gen_ext16s_i64 -#define tcg_gen_ext32u_reg tcg_gen_ext32u_i64 -#define tcg_gen_ext32s_reg tcg_gen_ext32s_i64 -#define tcg_gen_bswap16_reg tcg_gen_bswap16_i64 -#define tcg_gen_bswap32_reg tcg_gen_bswap32_i64 -#define tcg_gen_bswap64_reg tcg_gen_bswap64_i64 -#define tcg_gen_concat_reg_i64 tcg_gen_concat32_i64 -#define tcg_gen_andc_reg tcg_gen_andc_i64 -#define tcg_gen_eqv_reg tcg_gen_eqv_i64 -#define tcg_gen_nand_reg tcg_gen_nand_i64 -#define tcg_gen_nor_reg tcg_gen_nor_i64 -#define tcg_gen_orc_reg tcg_gen_orc_i64 -#define tcg_gen_clz_reg tcg_gen_clz_i64 -#define tcg_gen_ctz_reg tcg_gen_ctz_i64 -#define tcg_gen_clzi_reg tcg_gen_clzi_i64 -#define tcg_gen_ctzi_reg tcg_gen_ctzi_i64 -#define tcg_gen_clrsb_reg tcg_gen_clrsb_i64 -#define tcg_gen_ctpop_reg tcg_gen_ctpop_i64 -#define tcg_gen_rotl_reg tcg_gen_rotl_i64 -#define tcg_gen_rotli_reg tcg_gen_rotli_i64 -#define tcg_gen_rotr_reg tcg_gen_rotr_i64 -#define tcg_gen_rotri_reg tcg_gen_rotri_i64 -#define tcg_gen_deposit_reg tcg_gen_deposit_i64 -#define tcg_gen_deposit_z_reg tcg_gen_deposit_z_i64 -#define tcg_gen_extract_reg tcg_gen_extract_i64 -#define tcg_gen_sextract_reg tcg_gen_sextract_i64 -#define tcg_gen_extract2_reg tcg_gen_extract2_i64 -#define tcg_constant_reg tcg_constant_i64 -#define tcg_gen_movcond_reg tcg_gen_movcond_i64 -#define tcg_gen_add2_reg tcg_gen_add2_i64 -#define tcg_gen_sub2_reg tcg_gen_sub2_i64 -#define tcg_gen_qemu_ld_reg tcg_gen_qemu_ld_i64 -#define tcg_gen_qemu_st_reg tcg_gen_qemu_st_i64 -#define tcg_gen_atomic_xchg_reg tcg_gen_atomic_xchg_i64 -#define tcg_gen_trunc_reg_ptr tcg_gen_trunc_i64_ptr + =20 typedef struct DisasCond { TCGCond c; - TCGv_reg a0, a1; + TCGv_i64 a0, a1; } DisasCond; =20 typedef struct DisasContext { @@ -149,7 +54,7 @@ typedef struct DisasContext { uint64_t iaoq_f; uint64_t iaoq_b; uint64_t iaoq_n; - TCGv_reg iaoq_n_var; + TCGv_i64 iaoq_n_var; =20 DisasCond null_cond; TCGLabel *null_lab; @@ -261,24 +166,24 @@ static int cmpbid_c(DisasContext *ctx, int val) #define DISAS_EXIT DISAS_TARGET_3 =20 /* global register indexes */ -static TCGv_reg cpu_gr[32]; +static TCGv_i64 cpu_gr[32]; static TCGv_i64 cpu_sr[4]; static TCGv_i64 cpu_srH; -static TCGv_reg cpu_iaoq_f; -static TCGv_reg cpu_iaoq_b; +static TCGv_i64 cpu_iaoq_f; +static TCGv_i64 cpu_iaoq_b; static TCGv_i64 cpu_iasq_f; static TCGv_i64 cpu_iasq_b; -static TCGv_reg cpu_sar; -static TCGv_reg cpu_psw_n; -static TCGv_reg cpu_psw_v; -static TCGv_reg cpu_psw_cb; -static TCGv_reg cpu_psw_cb_msb; +static TCGv_i64 cpu_sar; +static TCGv_i64 cpu_psw_n; +static TCGv_i64 cpu_psw_v; +static TCGv_i64 cpu_psw_cb; +static TCGv_i64 cpu_psw_cb_msb; =20 void hppa_translate_init(void) { #define DEF_VAR(V) { &cpu_##V, #V, offsetof(CPUHPPAState, V) } =20 - typedef struct { TCGv_reg *var; const char *name; int ofs; } GlobalVar; + typedef struct { TCGv_i64 *var; const char *name; int ofs; } GlobalVar; static const GlobalVar vars[] =3D { { &cpu_sar, "sar", offsetof(CPUHPPAState, cr[CR_SAR]) }, DEF_VAR(psw_n), @@ -356,35 +261,35 @@ static DisasCond cond_make_n(void) return (DisasCond){ .c =3D TCG_COND_NE, .a0 =3D cpu_psw_n, - .a1 =3D tcg_constant_reg(0) + .a1 =3D tcg_constant_i64(0) }; } =20 -static DisasCond cond_make_tmp(TCGCond c, TCGv_reg a0, TCGv_reg a1) +static DisasCond cond_make_tmp(TCGCond c, TCGv_i64 a0, TCGv_i64 a1) { assert (c !=3D TCG_COND_NEVER && c !=3D TCG_COND_ALWAYS); return (DisasCond){ .c =3D c, .a0 =3D a0, .a1 =3D a1 }; } =20 -static DisasCond cond_make_0_tmp(TCGCond c, TCGv_reg a0) +static DisasCond cond_make_0_tmp(TCGCond c, TCGv_i64 a0) { - return cond_make_tmp(c, a0, tcg_constant_reg(0)); + return cond_make_tmp(c, a0, tcg_constant_i64(0)); } =20 -static DisasCond cond_make_0(TCGCond c, TCGv_reg a0) +static DisasCond cond_make_0(TCGCond c, TCGv_i64 a0) { - TCGv_reg tmp =3D tcg_temp_new(); - tcg_gen_mov_reg(tmp, a0); + TCGv_i64 tmp =3D tcg_temp_new(); + tcg_gen_mov_i64(tmp, a0); return cond_make_0_tmp(c, tmp); } =20 -static DisasCond cond_make(TCGCond c, TCGv_reg a0, TCGv_reg a1) +static DisasCond cond_make(TCGCond c, TCGv_i64 a0, TCGv_i64 a1) { - TCGv_reg t0 =3D tcg_temp_new(); - TCGv_reg t1 =3D tcg_temp_new(); + TCGv_i64 t0 =3D tcg_temp_new(); + TCGv_i64 t1 =3D tcg_temp_new(); =20 - tcg_gen_mov_reg(t0, a0); - tcg_gen_mov_reg(t1, a1); + tcg_gen_mov_i64(t0, a0); + tcg_gen_mov_i64(t1, a1); return cond_make_tmp(c, t0, t1); } =20 @@ -403,18 +308,18 @@ static void cond_free(DisasCond *cond) } } =20 -static TCGv_reg load_gpr(DisasContext *ctx, unsigned reg) +static TCGv_i64 load_gpr(DisasContext *ctx, unsigned reg) { if (reg =3D=3D 0) { - TCGv_reg t =3D tcg_temp_new(); - tcg_gen_movi_reg(t, 0); + TCGv_i64 t =3D tcg_temp_new(); + tcg_gen_movi_i64(t, 0); return t; } else { return cpu_gr[reg]; } } =20 -static TCGv_reg dest_gpr(DisasContext *ctx, unsigned reg) +static TCGv_i64 dest_gpr(DisasContext *ctx, unsigned reg) { if (reg =3D=3D 0 || ctx->null_cond.c !=3D TCG_COND_NEVER) { return tcg_temp_new(); @@ -423,17 +328,17 @@ static TCGv_reg dest_gpr(DisasContext *ctx, unsigned = reg) } } =20 -static void save_or_nullify(DisasContext *ctx, TCGv_reg dest, TCGv_reg t) +static void save_or_nullify(DisasContext *ctx, TCGv_i64 dest, TCGv_i64 t) { if (ctx->null_cond.c !=3D TCG_COND_NEVER) { - tcg_gen_movcond_reg(ctx->null_cond.c, dest, ctx->null_cond.a0, + tcg_gen_movcond_i64(ctx->null_cond.c, dest, ctx->null_cond.a0, ctx->null_cond.a1, dest, t); } else { - tcg_gen_mov_reg(dest, t); + tcg_gen_mov_i64(dest, t); } } =20 -static void save_gpr(DisasContext *ctx, unsigned reg, TCGv_reg t) +static void save_gpr(DisasContext *ctx, unsigned reg, TCGv_i64 t) { if (reg !=3D 0) { save_or_nullify(ctx, cpu_gr[reg], t); @@ -542,17 +447,17 @@ static void nullify_over(DisasContext *ctx) /* If we're using PSW[N], copy it to a temp because... */ if (ctx->null_cond.a0 =3D=3D cpu_psw_n) { ctx->null_cond.a0 =3D tcg_temp_new(); - tcg_gen_mov_reg(ctx->null_cond.a0, cpu_psw_n); + tcg_gen_mov_i64(ctx->null_cond.a0, cpu_psw_n); } /* ... we clear it before branching over the implementation, so that (1) it's clear after nullifying this insn and (2) if this insn nullifies the next, PSW[N] is valid. */ if (ctx->psw_n_nonzero) { ctx->psw_n_nonzero =3D false; - tcg_gen_movi_reg(cpu_psw_n, 0); + tcg_gen_movi_i64(cpu_psw_n, 0); } =20 - tcg_gen_brcond_reg(ctx->null_cond.c, ctx->null_cond.a0, + tcg_gen_brcond_i64(ctx->null_cond.c, ctx->null_cond.a0, ctx->null_cond.a1, ctx->null_lab); cond_free(&ctx->null_cond); } @@ -563,12 +468,12 @@ static void nullify_save(DisasContext *ctx) { if (ctx->null_cond.c =3D=3D TCG_COND_NEVER) { if (ctx->psw_n_nonzero) { - tcg_gen_movi_reg(cpu_psw_n, 0); + tcg_gen_movi_i64(cpu_psw_n, 0); } return; } if (ctx->null_cond.a0 !=3D cpu_psw_n) { - tcg_gen_setcond_reg(ctx->null_cond.c, cpu_psw_n, + tcg_gen_setcond_i64(ctx->null_cond.c, cpu_psw_n, ctx->null_cond.a0, ctx->null_cond.a1); ctx->psw_n_nonzero =3D true; } @@ -581,7 +486,7 @@ static void nullify_save(DisasContext *ctx) static void nullify_set(DisasContext *ctx, bool x) { if (ctx->psw_n_nonzero || x) { - tcg_gen_movi_reg(cpu_psw_n, x); + tcg_gen_movi_i64(cpu_psw_n, x); } } =20 @@ -624,12 +529,12 @@ static bool nullify_end(DisasContext *ctx) return true; } =20 -static void copy_iaoq_entry(TCGv_reg dest, uint64_t ival, TCGv_reg vval) +static void copy_iaoq_entry(TCGv_i64 dest, uint64_t ival, TCGv_i64 vval) { if (unlikely(ival =3D=3D -1)) { - tcg_gen_mov_reg(dest, vval); + tcg_gen_mov_i64(dest, vval); } else { - tcg_gen_movi_reg(dest, ival); + tcg_gen_movi_i64(dest, ival); } } =20 @@ -655,7 +560,7 @@ static void gen_excp(DisasContext *ctx, int exception) static bool gen_excp_iir(DisasContext *ctx, int exc) { nullify_over(ctx); - tcg_gen_st_reg(tcg_constant_reg(ctx->insn), + tcg_gen_st_i64(tcg_constant_i64(ctx->insn), tcg_env, offsetof(CPUHPPAState, cr[CR_IIR])); gen_excp(ctx, exc); return nullify_end(ctx); @@ -705,8 +610,8 @@ static void gen_goto_tb(DisasContext *ctx, int which, { if (f !=3D -1 && b !=3D -1 && use_goto_tb(ctx, f)) { tcg_gen_goto_tb(which); - tcg_gen_movi_reg(cpu_iaoq_f, f); - tcg_gen_movi_reg(cpu_iaoq_b, b); + tcg_gen_movi_i64(cpu_iaoq_f, f); + tcg_gen_movi_i64(cpu_iaoq_b, b); tcg_gen_exit_tb(ctx->base.tb, which); } else { copy_iaoq_entry(cpu_iaoq_f, f, cpu_iaoq_b); @@ -725,7 +630,7 @@ static bool cond_need_cb(int c) return c =3D=3D 4 || c =3D=3D 5; } =20 -/* Need extensions from TCGv_i32 to TCGv_reg. */ +/* Need extensions from TCGv_i32 to TCGv_i64. */ static bool cond_need_ext(DisasContext *ctx, bool d) { return !(ctx->is_pa20 && d); @@ -737,10 +642,10 @@ static bool cond_need_ext(DisasContext *ctx, bool d) */ =20 static DisasCond do_cond(DisasContext *ctx, unsigned cf, bool d, - TCGv_reg res, TCGv_reg cb_msb, TCGv_reg sv) + TCGv_i64 res, TCGv_i64 cb_msb, TCGv_i64 sv) { DisasCond cond; - TCGv_reg tmp; + TCGv_i64 tmp; =20 switch (cf >> 1) { case 0: /* Never / TR (0 / 1) */ @@ -749,16 +654,16 @@ static DisasCond do_cond(DisasContext *ctx, unsigned = cf, bool d, case 1: /* =3D / <> (Z / !Z) */ if (cond_need_ext(ctx, d)) { tmp =3D tcg_temp_new(); - tcg_gen_ext32u_reg(tmp, res); + tcg_gen_ext32u_i64(tmp, res); res =3D tmp; } cond =3D cond_make_0(TCG_COND_EQ, res); break; case 2: /* < / >=3D (N ^ V / !(N ^ V) */ tmp =3D tcg_temp_new(); - tcg_gen_xor_reg(tmp, res, sv); + tcg_gen_xor_i64(tmp, res, sv); if (cond_need_ext(ctx, d)) { - tcg_gen_ext32s_reg(tmp, tmp); + tcg_gen_ext32s_i64(tmp, tmp); } cond =3D cond_make_0_tmp(TCG_COND_LT, tmp); break; @@ -773,14 +678,14 @@ static DisasCond do_cond(DisasContext *ctx, unsigned = cf, bool d, * !(~(res ^ sv) >> 31 & res) */ tmp =3D tcg_temp_new(); - tcg_gen_eqv_reg(tmp, res, sv); + tcg_gen_eqv_i64(tmp, res, sv); if (cond_need_ext(ctx, d)) { - tcg_gen_sextract_reg(tmp, tmp, 31, 1); - tcg_gen_and_reg(tmp, tmp, res); - tcg_gen_ext32u_reg(tmp, tmp); + tcg_gen_sextract_i64(tmp, tmp, 31, 1); + tcg_gen_and_i64(tmp, tmp, res); + tcg_gen_ext32u_i64(tmp, tmp); } else { - tcg_gen_sari_reg(tmp, tmp, 63); - tcg_gen_and_reg(tmp, tmp, res); + tcg_gen_sari_i64(tmp, tmp, 63); + tcg_gen_and_i64(tmp, tmp, res); } cond =3D cond_make_0_tmp(TCG_COND_EQ, tmp); break; @@ -790,24 +695,24 @@ static DisasCond do_cond(DisasContext *ctx, unsigned = cf, bool d, break; case 5: /* ZNV / VNZ (!C | Z / C & !Z) */ tmp =3D tcg_temp_new(); - tcg_gen_neg_reg(tmp, cb_msb); - tcg_gen_and_reg(tmp, tmp, res); + tcg_gen_neg_i64(tmp, cb_msb); + tcg_gen_and_i64(tmp, tmp, res); if (cond_need_ext(ctx, d)) { - tcg_gen_ext32u_reg(tmp, tmp); + tcg_gen_ext32u_i64(tmp, tmp); } cond =3D cond_make_0_tmp(TCG_COND_EQ, tmp); break; case 6: /* SV / NSV (V / !V) */ if (cond_need_ext(ctx, d)) { tmp =3D tcg_temp_new(); - tcg_gen_ext32s_reg(tmp, sv); + tcg_gen_ext32s_i64(tmp, sv); sv =3D tmp; } cond =3D cond_make_0(TCG_COND_LT, sv); break; case 7: /* OD / EV */ tmp =3D tcg_temp_new(); - tcg_gen_andi_reg(tmp, res, 1); + tcg_gen_andi_i64(tmp, res, 1); cond =3D cond_make_0_tmp(TCG_COND_NE, tmp); break; default: @@ -825,8 +730,8 @@ static DisasCond do_cond(DisasContext *ctx, unsigned cf= , bool d, deleted as unused. */ =20 static DisasCond do_sub_cond(DisasContext *ctx, unsigned cf, bool d, - TCGv_reg res, TCGv_reg in1, - TCGv_reg in2, TCGv_reg sv) + TCGv_i64 res, TCGv_i64 in1, + TCGv_i64 in2, TCGv_i64 sv) { TCGCond tc; bool ext_uns; @@ -860,15 +765,15 @@ static DisasCond do_sub_cond(DisasContext *ctx, unsig= ned cf, bool d, tc =3D tcg_invert_cond(tc); } if (cond_need_ext(ctx, d)) { - TCGv_reg t1 =3D tcg_temp_new(); - TCGv_reg t2 =3D tcg_temp_new(); + TCGv_i64 t1 =3D tcg_temp_new(); + TCGv_i64 t2 =3D tcg_temp_new(); =20 if (ext_uns) { - tcg_gen_ext32u_reg(t1, in1); - tcg_gen_ext32u_reg(t2, in2); + tcg_gen_ext32u_i64(t1, in1); + tcg_gen_ext32u_i64(t2, in2); } else { - tcg_gen_ext32s_reg(t1, in1); - tcg_gen_ext32s_reg(t2, in2); + tcg_gen_ext32s_i64(t1, in1); + tcg_gen_ext32s_i64(t2, in2); } return cond_make_tmp(tc, t1, t2); } @@ -885,7 +790,7 @@ static DisasCond do_sub_cond(DisasContext *ctx, unsigne= d cf, bool d, */ =20 static DisasCond do_log_cond(DisasContext *ctx, unsigned cf, bool d, - TCGv_reg res) + TCGv_i64 res) { TCGCond tc; bool ext_uns; @@ -937,12 +842,12 @@ static DisasCond do_log_cond(DisasContext *ctx, unsig= ned cf, bool d, } =20 if (cond_need_ext(ctx, d)) { - TCGv_reg tmp =3D tcg_temp_new(); + TCGv_i64 tmp =3D tcg_temp_new(); =20 if (ext_uns) { - tcg_gen_ext32u_reg(tmp, res); + tcg_gen_ext32u_i64(tmp, res); } else { - tcg_gen_ext32s_reg(tmp, res); + tcg_gen_ext32s_i64(tmp, res); } return cond_make_0_tmp(tc, tmp); } @@ -952,7 +857,7 @@ static DisasCond do_log_cond(DisasContext *ctx, unsigne= d cf, bool d, /* Similar, but for shift/extract/deposit conditions. */ =20 static DisasCond do_sed_cond(DisasContext *ctx, unsigned orig, bool d, - TCGv_reg res) + TCGv_i64 res) { unsigned c, f; =20 @@ -970,11 +875,11 @@ static DisasCond do_sed_cond(DisasContext *ctx, unsig= ned orig, bool d, =20 /* Similar, but for unit conditions. */ =20 -static DisasCond do_unit_cond(unsigned cf, bool d, TCGv_reg res, - TCGv_reg in1, TCGv_reg in2) +static DisasCond do_unit_cond(unsigned cf, bool d, TCGv_i64 res, + TCGv_i64 in1, TCGv_i64 in2) { DisasCond cond; - TCGv_reg tmp, cb =3D NULL; + TCGv_i64 tmp, cb =3D NULL; uint64_t d_repl =3D d ? 0x0000000100000001ull : 1; =20 if (cf & 8) { @@ -984,10 +889,10 @@ static DisasCond do_unit_cond(unsigned cf, bool d, TC= Gv_reg res, */ cb =3D tcg_temp_new(); tmp =3D tcg_temp_new(); - tcg_gen_or_reg(cb, in1, in2); - tcg_gen_and_reg(tmp, in1, in2); - tcg_gen_andc_reg(cb, cb, res); - tcg_gen_or_reg(cb, cb, tmp); + tcg_gen_or_i64(cb, in1, in2); + tcg_gen_and_i64(tmp, in1, in2); + tcg_gen_andc_i64(cb, cb, res); + tcg_gen_or_i64(cb, cb, tmp); } =20 switch (cf >> 1) { @@ -1002,32 +907,32 @@ static DisasCond do_unit_cond(unsigned cf, bool d, T= CGv_reg res, * https://graphics.stanford.edu/~seander/bithacks.html#ZeroInWord */ tmp =3D tcg_temp_new(); - tcg_gen_subi_reg(tmp, res, d_repl * 0x01010101u); - tcg_gen_andc_reg(tmp, tmp, res); - tcg_gen_andi_reg(tmp, tmp, d_repl * 0x80808080u); + tcg_gen_subi_i64(tmp, res, d_repl * 0x01010101u); + tcg_gen_andc_i64(tmp, tmp, res); + tcg_gen_andi_i64(tmp, tmp, d_repl * 0x80808080u); cond =3D cond_make_0(TCG_COND_NE, tmp); break; =20 case 3: /* SHZ / NHZ */ tmp =3D tcg_temp_new(); - tcg_gen_subi_reg(tmp, res, d_repl * 0x00010001u); - tcg_gen_andc_reg(tmp, tmp, res); - tcg_gen_andi_reg(tmp, tmp, d_repl * 0x80008000u); + tcg_gen_subi_i64(tmp, res, d_repl * 0x00010001u); + tcg_gen_andc_i64(tmp, tmp, res); + tcg_gen_andi_i64(tmp, tmp, d_repl * 0x80008000u); cond =3D cond_make_0(TCG_COND_NE, tmp); break; =20 case 4: /* SDC / NDC */ - tcg_gen_andi_reg(cb, cb, d_repl * 0x88888888u); + tcg_gen_andi_i64(cb, cb, d_repl * 0x88888888u); cond =3D cond_make_0(TCG_COND_NE, cb); break; =20 case 6: /* SBC / NBC */ - tcg_gen_andi_reg(cb, cb, d_repl * 0x80808080u); + tcg_gen_andi_i64(cb, cb, d_repl * 0x80808080u); cond =3D cond_make_0(TCG_COND_NE, cb); break; =20 case 7: /* SHC / NHC */ - tcg_gen_andi_reg(cb, cb, d_repl * 0x80008000u); + tcg_gen_andi_i64(cb, cb, d_repl * 0x80008000u); cond =3D cond_make_0(TCG_COND_NE, cb); break; =20 @@ -1041,55 +946,55 @@ static DisasCond do_unit_cond(unsigned cf, bool d, T= CGv_reg res, return cond; } =20 -static TCGv_reg get_carry(DisasContext *ctx, bool d, - TCGv_reg cb, TCGv_reg cb_msb) +static TCGv_i64 get_carry(DisasContext *ctx, bool d, + TCGv_i64 cb, TCGv_i64 cb_msb) { if (cond_need_ext(ctx, d)) { - TCGv_reg t =3D tcg_temp_new(); - tcg_gen_extract_reg(t, cb, 32, 1); + TCGv_i64 t =3D tcg_temp_new(); + tcg_gen_extract_i64(t, cb, 32, 1); return t; } return cb_msb; } =20 -static TCGv_reg get_psw_carry(DisasContext *ctx, bool d) +static TCGv_i64 get_psw_carry(DisasContext *ctx, bool d) { return get_carry(ctx, d, cpu_psw_cb, cpu_psw_cb_msb); } =20 /* Compute signed overflow for addition. */ -static TCGv_reg do_add_sv(DisasContext *ctx, TCGv_reg res, - TCGv_reg in1, TCGv_reg in2) +static TCGv_i64 do_add_sv(DisasContext *ctx, TCGv_i64 res, + TCGv_i64 in1, TCGv_i64 in2) { - TCGv_reg sv =3D tcg_temp_new(); - TCGv_reg tmp =3D tcg_temp_new(); + TCGv_i64 sv =3D tcg_temp_new(); + TCGv_i64 tmp =3D tcg_temp_new(); =20 - tcg_gen_xor_reg(sv, res, in1); - tcg_gen_xor_reg(tmp, in1, in2); - tcg_gen_andc_reg(sv, sv, tmp); + tcg_gen_xor_i64(sv, res, in1); + tcg_gen_xor_i64(tmp, in1, in2); + tcg_gen_andc_i64(sv, sv, tmp); =20 return sv; } =20 /* Compute signed overflow for subtraction. */ -static TCGv_reg do_sub_sv(DisasContext *ctx, TCGv_reg res, - TCGv_reg in1, TCGv_reg in2) +static TCGv_i64 do_sub_sv(DisasContext *ctx, TCGv_i64 res, + TCGv_i64 in1, TCGv_i64 in2) { - TCGv_reg sv =3D tcg_temp_new(); - TCGv_reg tmp =3D tcg_temp_new(); + TCGv_i64 sv =3D tcg_temp_new(); + TCGv_i64 tmp =3D tcg_temp_new(); =20 - tcg_gen_xor_reg(sv, res, in1); - tcg_gen_xor_reg(tmp, in1, in2); - tcg_gen_and_reg(sv, sv, tmp); + tcg_gen_xor_i64(sv, res, in1); + tcg_gen_xor_i64(tmp, in1, in2); + tcg_gen_and_i64(sv, sv, tmp); =20 return sv; } =20 -static void do_add(DisasContext *ctx, unsigned rt, TCGv_reg in1, - TCGv_reg in2, unsigned shift, bool is_l, +static void do_add(DisasContext *ctx, unsigned rt, TCGv_i64 in1, + TCGv_i64 in2, unsigned shift, bool is_l, bool is_tsv, bool is_tc, bool is_c, unsigned cf, bool d) { - TCGv_reg dest, cb, cb_msb, cb_cond, sv, tmp; + TCGv_i64 dest, cb, cb_msb, cb_cond, sv, tmp; unsigned c =3D cf >> 1; DisasCond cond; =20 @@ -1100,29 +1005,29 @@ static void do_add(DisasContext *ctx, unsigned rt, = TCGv_reg in1, =20 if (shift) { tmp =3D tcg_temp_new(); - tcg_gen_shli_reg(tmp, in1, shift); + tcg_gen_shli_i64(tmp, in1, shift); in1 =3D tmp; } =20 if (!is_l || cond_need_cb(c)) { - TCGv_reg zero =3D tcg_constant_reg(0); + TCGv_i64 zero =3D tcg_constant_i64(0); cb_msb =3D tcg_temp_new(); cb =3D tcg_temp_new(); =20 - tcg_gen_add2_reg(dest, cb_msb, in1, zero, in2, zero); + tcg_gen_add2_i64(dest, cb_msb, in1, zero, in2, zero); if (is_c) { - tcg_gen_add2_reg(dest, cb_msb, dest, cb_msb, + tcg_gen_add2_i64(dest, cb_msb, dest, cb_msb, get_psw_carry(ctx, d), zero); } - tcg_gen_xor_reg(cb, in1, in2); - tcg_gen_xor_reg(cb, cb, dest); + tcg_gen_xor_i64(cb, in1, in2); + tcg_gen_xor_i64(cb, cb, dest); if (cond_need_cb(c)) { cb_cond =3D get_carry(ctx, d, cb, cb_msb); } } else { - tcg_gen_add_reg(dest, in1, in2); + tcg_gen_add_i64(dest, in1, in2); if (is_c) { - tcg_gen_add_reg(dest, dest, get_psw_carry(ctx, d)); + tcg_gen_add_i64(dest, dest, get_psw_carry(ctx, d)); } } =20 @@ -1140,7 +1045,7 @@ static void do_add(DisasContext *ctx, unsigned rt, TC= Gv_reg in1, cond =3D do_cond(ctx, cf, d, dest, cb_cond, sv); if (is_tc) { tmp =3D tcg_temp_new(); - tcg_gen_setcond_reg(cond.c, tmp, cond.a0, cond.a1); + tcg_gen_setcond_i64(cond.c, tmp, cond.a0, cond.a1); gen_helper_tcond(tcg_env, tmp); } =20 @@ -1159,7 +1064,7 @@ static void do_add(DisasContext *ctx, unsigned rt, TC= Gv_reg in1, static bool do_add_reg(DisasContext *ctx, arg_rrr_cf_d_sh *a, bool is_l, bool is_tsv, bool is_tc, bool is_c) { - TCGv_reg tcg_r1, tcg_r2; + TCGv_i64 tcg_r1, tcg_r2; =20 if (a->cf) { nullify_over(ctx); @@ -1174,23 +1079,23 @@ static bool do_add_reg(DisasContext *ctx, arg_rrr_c= f_d_sh *a, static bool do_add_imm(DisasContext *ctx, arg_rri_cf *a, bool is_tsv, bool is_tc) { - TCGv_reg tcg_im, tcg_r2; + TCGv_i64 tcg_im, tcg_r2; =20 if (a->cf) { nullify_over(ctx); } - tcg_im =3D tcg_constant_reg(a->i); + tcg_im =3D tcg_constant_i64(a->i); tcg_r2 =3D load_gpr(ctx, a->r); /* All ADDI conditions are 32-bit. */ do_add(ctx, a->t, tcg_im, tcg_r2, 0, 0, is_tsv, is_tc, 0, a->cf, false= ); return nullify_end(ctx); } =20 -static void do_sub(DisasContext *ctx, unsigned rt, TCGv_reg in1, - TCGv_reg in2, bool is_tsv, bool is_b, +static void do_sub(DisasContext *ctx, unsigned rt, TCGv_i64 in1, + TCGv_i64 in2, bool is_tsv, bool is_b, bool is_tc, unsigned cf, bool d) { - TCGv_reg dest, sv, cb, cb_msb, zero, tmp; + TCGv_i64 dest, sv, cb, cb_msb, zero, tmp; unsigned c =3D cf >> 1; DisasCond cond; =20 @@ -1198,23 +1103,23 @@ static void do_sub(DisasContext *ctx, unsigned rt, = TCGv_reg in1, cb =3D tcg_temp_new(); cb_msb =3D tcg_temp_new(); =20 - zero =3D tcg_constant_reg(0); + zero =3D tcg_constant_i64(0); if (is_b) { /* DEST,C =3D IN1 + ~IN2 + C. */ - tcg_gen_not_reg(cb, in2); - tcg_gen_add2_reg(dest, cb_msb, in1, zero, get_psw_carry(ctx, d), z= ero); - tcg_gen_add2_reg(dest, cb_msb, dest, cb_msb, cb, zero); - tcg_gen_xor_reg(cb, cb, in1); - tcg_gen_xor_reg(cb, cb, dest); + tcg_gen_not_i64(cb, in2); + tcg_gen_add2_i64(dest, cb_msb, in1, zero, get_psw_carry(ctx, d), z= ero); + tcg_gen_add2_i64(dest, cb_msb, dest, cb_msb, cb, zero); + tcg_gen_xor_i64(cb, cb, in1); + tcg_gen_xor_i64(cb, cb, dest); } else { /* * DEST,C =3D IN1 + ~IN2 + 1. We can produce the same result in f= ewer * operations by seeding the high word with 1 and subtracting. */ - TCGv_reg one =3D tcg_constant_reg(1); - tcg_gen_sub2_reg(dest, cb_msb, in1, one, in2, zero); - tcg_gen_eqv_reg(cb, in1, in2); - tcg_gen_xor_reg(cb, cb, dest); + TCGv_i64 one =3D tcg_constant_i64(1); + tcg_gen_sub2_i64(dest, cb_msb, in1, one, in2, zero); + tcg_gen_eqv_i64(cb, in1, in2); + tcg_gen_xor_i64(cb, cb, dest); } =20 /* Compute signed overflow if required. */ @@ -1236,7 +1141,7 @@ static void do_sub(DisasContext *ctx, unsigned rt, TC= Gv_reg in1, /* Emit any conditional trap before any writeback. */ if (is_tc) { tmp =3D tcg_temp_new(); - tcg_gen_setcond_reg(cond.c, tmp, cond.a0, cond.a1); + tcg_gen_setcond_i64(cond.c, tmp, cond.a0, cond.a1); gen_helper_tcond(tcg_env, tmp); } =20 @@ -1253,7 +1158,7 @@ static void do_sub(DisasContext *ctx, unsigned rt, TC= Gv_reg in1, static bool do_sub_reg(DisasContext *ctx, arg_rrr_cf_d *a, bool is_tsv, bool is_b, bool is_tc) { - TCGv_reg tcg_r1, tcg_r2; + TCGv_i64 tcg_r1, tcg_r2; =20 if (a->cf) { nullify_over(ctx); @@ -1266,26 +1171,26 @@ static bool do_sub_reg(DisasContext *ctx, arg_rrr_c= f_d *a, =20 static bool do_sub_imm(DisasContext *ctx, arg_rri_cf *a, bool is_tsv) { - TCGv_reg tcg_im, tcg_r2; + TCGv_i64 tcg_im, tcg_r2; =20 if (a->cf) { nullify_over(ctx); } - tcg_im =3D tcg_constant_reg(a->i); + tcg_im =3D tcg_constant_i64(a->i); tcg_r2 =3D load_gpr(ctx, a->r); /* All SUBI conditions are 32-bit. */ do_sub(ctx, a->t, tcg_im, tcg_r2, is_tsv, 0, 0, a->cf, false); return nullify_end(ctx); } =20 -static void do_cmpclr(DisasContext *ctx, unsigned rt, TCGv_reg in1, - TCGv_reg in2, unsigned cf, bool d) +static void do_cmpclr(DisasContext *ctx, unsigned rt, TCGv_i64 in1, + TCGv_i64 in2, unsigned cf, bool d) { - TCGv_reg dest, sv; + TCGv_i64 dest, sv; DisasCond cond; =20 dest =3D tcg_temp_new(); - tcg_gen_sub_reg(dest, in1, in2); + tcg_gen_sub_i64(dest, in1, in2); =20 /* Compute signed overflow if required. */ sv =3D NULL; @@ -1297,7 +1202,7 @@ static void do_cmpclr(DisasContext *ctx, unsigned rt,= TCGv_reg in1, cond =3D do_sub_cond(ctx, cf, d, dest, in1, in2, sv); =20 /* Clear. */ - tcg_gen_movi_reg(dest, 0); + tcg_gen_movi_i64(dest, 0); save_gpr(ctx, rt, dest); =20 /* Install the new nullification. */ @@ -1305,11 +1210,11 @@ static void do_cmpclr(DisasContext *ctx, unsigned r= t, TCGv_reg in1, ctx->null_cond =3D cond; } =20 -static void do_log(DisasContext *ctx, unsigned rt, TCGv_reg in1, - TCGv_reg in2, unsigned cf, bool d, - void (*fn)(TCGv_reg, TCGv_reg, TCGv_reg)) +static void do_log(DisasContext *ctx, unsigned rt, TCGv_i64 in1, + TCGv_i64 in2, unsigned cf, bool d, + void (*fn)(TCGv_i64, TCGv_i64, TCGv_i64)) { - TCGv_reg dest =3D dest_gpr(ctx, rt); + TCGv_i64 dest =3D dest_gpr(ctx, rt); =20 /* Perform the operation, and writeback. */ fn(dest, in1, in2); @@ -1323,9 +1228,9 @@ static void do_log(DisasContext *ctx, unsigned rt, TC= Gv_reg in1, } =20 static bool do_log_reg(DisasContext *ctx, arg_rrr_cf_d *a, - void (*fn)(TCGv_reg, TCGv_reg, TCGv_reg)) + void (*fn)(TCGv_i64, TCGv_i64, TCGv_i64)) { - TCGv_reg tcg_r1, tcg_r2; + TCGv_i64 tcg_r1, tcg_r2; =20 if (a->cf) { nullify_over(ctx); @@ -1336,11 +1241,11 @@ static bool do_log_reg(DisasContext *ctx, arg_rrr_c= f_d *a, return nullify_end(ctx); } =20 -static void do_unit(DisasContext *ctx, unsigned rt, TCGv_reg in1, - TCGv_reg in2, unsigned cf, bool d, bool is_tc, - void (*fn)(TCGv_reg, TCGv_reg, TCGv_reg)) +static void do_unit(DisasContext *ctx, unsigned rt, TCGv_i64 in1, + TCGv_i64 in2, unsigned cf, bool d, bool is_tc, + void (*fn)(TCGv_i64, TCGv_i64, TCGv_i64)) { - TCGv_reg dest; + TCGv_i64 dest; DisasCond cond; =20 if (cf =3D=3D 0) { @@ -1355,8 +1260,8 @@ static void do_unit(DisasContext *ctx, unsigned rt, T= CGv_reg in1, cond =3D do_unit_cond(cf, d, dest, in1, in2); =20 if (is_tc) { - TCGv_reg tmp =3D tcg_temp_new(); - tcg_gen_setcond_reg(cond.c, tmp, cond.a0, cond.a1); + TCGv_i64 tmp =3D tcg_temp_new(); + tcg_gen_setcond_i64(cond.c, tmp, cond.a0, cond.a1); gen_helper_tcond(tcg_env, tmp); } save_gpr(ctx, rt, dest); @@ -1371,17 +1276,17 @@ static void do_unit(DisasContext *ctx, unsigned rt,= TCGv_reg in1, from the top 2 bits of the base register. There are a few system instructions that have a 3-bit space specifier, for which SR0 is not special. To handle this, pass ~SP. */ -static TCGv_i64 space_select(DisasContext *ctx, int sp, TCGv_reg base) +static TCGv_i64 space_select(DisasContext *ctx, int sp, TCGv_i64 base) { TCGv_ptr ptr; - TCGv_reg tmp; + TCGv_i64 tmp; TCGv_i64 spc; =20 if (sp !=3D 0) { if (sp < 0) { sp =3D ~sp; } - spc =3D tcg_temp_new_tl(); + spc =3D tcg_temp_new_i64(); load_spr(ctx, spc, sp); return spc; } @@ -1391,12 +1296,12 @@ static TCGv_i64 space_select(DisasContext *ctx, int= sp, TCGv_reg base) =20 ptr =3D tcg_temp_new_ptr(); tmp =3D tcg_temp_new(); - spc =3D tcg_temp_new_tl(); + spc =3D tcg_temp_new_i64(); =20 /* Extract top 2 bits of the address, shift left 3 for uint64_t index.= */ - tcg_gen_shri_reg(tmp, base, (ctx->tb_flags & PSW_W ? 64 : 32) - 5); - tcg_gen_andi_reg(tmp, tmp, 030); - tcg_gen_trunc_reg_ptr(ptr, tmp); + tcg_gen_shri_i64(tmp, base, (ctx->tb_flags & PSW_W ? 64 : 32) - 5); + tcg_gen_andi_i64(tmp, tmp, 030); + tcg_gen_trunc_i64_ptr(ptr, tmp); =20 tcg_gen_add_ptr(ptr, ptr, tcg_env); tcg_gen_ld_i64(spc, ptr, offsetof(CPUHPPAState, sr[4])); @@ -1405,28 +1310,28 @@ static TCGv_i64 space_select(DisasContext *ctx, int= sp, TCGv_reg base) } #endif =20 -static void form_gva(DisasContext *ctx, TCGv_tl *pgva, TCGv_reg *pofs, +static void form_gva(DisasContext *ctx, TCGv_i64 *pgva, TCGv_i64 *pofs, unsigned rb, unsigned rx, int scale, int64_t disp, unsigned sp, int modify, bool is_phys) { - TCGv_reg base =3D load_gpr(ctx, rb); - TCGv_reg ofs; - TCGv_tl addr; + TCGv_i64 base =3D load_gpr(ctx, rb); + TCGv_i64 ofs; + TCGv_i64 addr; =20 /* Note that RX is mutually exclusive with DISP. */ if (rx) { ofs =3D tcg_temp_new(); - tcg_gen_shli_reg(ofs, cpu_gr[rx], scale); - tcg_gen_add_reg(ofs, ofs, base); + tcg_gen_shli_i64(ofs, cpu_gr[rx], scale); + tcg_gen_add_i64(ofs, ofs, base); } else if (disp || modify) { ofs =3D tcg_temp_new(); - tcg_gen_addi_reg(ofs, base, disp); + tcg_gen_addi_i64(ofs, base, disp); } else { ofs =3D base; } =20 *pofs =3D ofs; - *pgva =3D addr =3D tcg_temp_new_tl(); + *pgva =3D addr =3D tcg_temp_new_i64(); tcg_gen_extu_reg_tl(addr, modify <=3D 0 ? ofs : base); tcg_gen_andi_tl(addr, addr, gva_offset_mask(ctx)); #ifndef CONFIG_USER_ONLY @@ -1445,8 +1350,8 @@ static void do_load_32(DisasContext *ctx, TCGv_i32 de= st, unsigned rb, unsigned rx, int scale, int64_t disp, unsigned sp, int modify, MemOp mop) { - TCGv_reg ofs; - TCGv_tl addr; + TCGv_i64 ofs; + TCGv_i64 addr; =20 /* Caller uses nullify_over/nullify_end. */ assert(ctx->null_cond.c =3D=3D TCG_COND_NEVER); @@ -1463,8 +1368,8 @@ static void do_load_64(DisasContext *ctx, TCGv_i64 de= st, unsigned rb, unsigned rx, int scale, int64_t disp, unsigned sp, int modify, MemOp mop) { - TCGv_reg ofs; - TCGv_tl addr; + TCGv_i64 ofs; + TCGv_i64 addr; =20 /* Caller uses nullify_over/nullify_end. */ assert(ctx->null_cond.c =3D=3D TCG_COND_NEVER); @@ -1481,8 +1386,8 @@ static void do_store_32(DisasContext *ctx, TCGv_i32 s= rc, unsigned rb, unsigned rx, int scale, int64_t disp, unsigned sp, int modify, MemOp mop) { - TCGv_reg ofs; - TCGv_tl addr; + TCGv_i64 ofs; + TCGv_i64 addr; =20 /* Caller uses nullify_over/nullify_end. */ assert(ctx->null_cond.c =3D=3D TCG_COND_NEVER); @@ -1499,8 +1404,8 @@ static void do_store_64(DisasContext *ctx, TCGv_i64 s= rc, unsigned rb, unsigned rx, int scale, int64_t disp, unsigned sp, int modify, MemOp mop) { - TCGv_reg ofs; - TCGv_tl addr; + TCGv_i64 ofs; + TCGv_i64 addr; =20 /* Caller uses nullify_over/nullify_end. */ assert(ctx->null_cond.c =3D=3D TCG_COND_NEVER); @@ -1513,14 +1418,11 @@ static void do_store_64(DisasContext *ctx, TCGv_i64= src, unsigned rb, } } =20 -#define do_load_reg do_load_64 -#define do_store_reg do_store_64 - static bool do_load(DisasContext *ctx, unsigned rt, unsigned rb, unsigned rx, int scale, int64_t disp, unsigned sp, int modify, MemOp mop) { - TCGv_reg dest; + TCGv_i64 dest; =20 nullify_over(ctx); =20 @@ -1531,7 +1433,7 @@ static bool do_load(DisasContext *ctx, unsigned rt, u= nsigned rb, /* Make sure if RT =3D=3D RB, we see the result of the load. */ dest =3D tcg_temp_new(); } - do_load_reg(ctx, dest, rb, rx, scale, disp, sp, modify, mop); + do_load_64(ctx, dest, rb, rx, scale, disp, sp, modify, mop); save_gpr(ctx, rt, dest); =20 return nullify_end(ctx); @@ -1592,7 +1494,7 @@ static bool do_store(DisasContext *ctx, unsigned rt, = unsigned rb, int modify, MemOp mop) { nullify_over(ctx); - do_store_reg(ctx, load_gpr(ctx, rt), rb, 0, 0, disp, sp, modify, mop); + do_store_64(ctx, load_gpr(ctx, rt), rb, 0, 0, disp, sp, modify, mop); return nullify_end(ctx); } =20 @@ -1786,7 +1688,7 @@ static bool do_cbranch(DisasContext *ctx, int64_t dis= p, bool is_n, } =20 taken =3D gen_new_label(); - tcg_gen_brcond_reg(c, cond->a0, cond->a1, taken); + tcg_gen_brcond_i64(c, cond->a0, cond->a1, taken); cond_free(cond); =20 /* Not taken: Condition not satisfied; nullify on backward branches. */ @@ -1803,7 +1705,7 @@ static bool do_cbranch(DisasContext *ctx, int64_t dis= p, bool is_n, if (ctx->iaoq_n =3D=3D -1) { /* The temporary iaoq_n_var died at the branch above. Regenerate it here instead of saving it. */ - tcg_gen_addi_reg(ctx->iaoq_n_var, cpu_iaoq_b, 4); + tcg_gen_addi_i64(ctx->iaoq_n_var, cpu_iaoq_b, 4); } gen_goto_tb(ctx, 0, ctx->iaoq_b, ctx->iaoq_n); } @@ -1833,10 +1735,10 @@ static bool do_cbranch(DisasContext *ctx, int64_t d= isp, bool is_n, =20 /* Emit an unconditional branch to an indirect target. This handles nullification of the branch itself. */ -static bool do_ibranch(DisasContext *ctx, TCGv_reg dest, +static bool do_ibranch(DisasContext *ctx, TCGv_i64 dest, unsigned link, bool is_n) { - TCGv_reg a0, a1, next, tmp; + TCGv_i64 a0, a1, next, tmp; TCGCond c; =20 assert(ctx->null_lab =3D=3D NULL); @@ -1846,11 +1748,11 @@ static bool do_ibranch(DisasContext *ctx, TCGv_reg = dest, copy_iaoq_entry(cpu_gr[link], ctx->iaoq_n, ctx->iaoq_n_var); } next =3D tcg_temp_new(); - tcg_gen_mov_reg(next, dest); + tcg_gen_mov_i64(next, dest); if (is_n) { if (use_nullify_skip(ctx)) { - tcg_gen_mov_reg(cpu_iaoq_f, next); - tcg_gen_addi_reg(cpu_iaoq_b, next, 4); + tcg_gen_mov_i64(cpu_iaoq_f, next); + tcg_gen_addi_i64(cpu_iaoq_b, next, 4); nullify_set(ctx, 0); ctx->base.is_jmp =3D DISAS_IAQ_N_UPDATED; return true; @@ -1872,12 +1774,12 @@ static bool do_ibranch(DisasContext *ctx, TCGv_reg = dest, /* We do have to handle the non-local temporary, DEST, before branching. Since IOAQ_F is not really live at this point, we can simply store DEST optimistically. Similarly with IAOQ_B. = */ - tcg_gen_mov_reg(cpu_iaoq_f, dest); - tcg_gen_addi_reg(cpu_iaoq_b, dest, 4); + tcg_gen_mov_i64(cpu_iaoq_f, dest); + tcg_gen_addi_i64(cpu_iaoq_b, dest, 4); =20 nullify_over(ctx); if (link !=3D 0) { - tcg_gen_movi_reg(cpu_gr[link], ctx->iaoq_n); + tcg_gen_movi_i64(cpu_gr[link], ctx->iaoq_n); } tcg_gen_lookup_and_goto_ptr(); return nullify_end(ctx); @@ -1890,19 +1792,19 @@ static bool do_ibranch(DisasContext *ctx, TCGv_reg = dest, next =3D tcg_temp_new(); =20 copy_iaoq_entry(tmp, ctx->iaoq_n, ctx->iaoq_n_var); - tcg_gen_movcond_reg(c, next, a0, a1, tmp, dest); + tcg_gen_movcond_i64(c, next, a0, a1, tmp, dest); ctx->iaoq_n =3D -1; ctx->iaoq_n_var =3D next; =20 if (link !=3D 0) { - tcg_gen_movcond_reg(c, cpu_gr[link], a0, a1, cpu_gr[link], tmp= ); + tcg_gen_movcond_i64(c, cpu_gr[link], a0, a1, cpu_gr[link], tmp= ); } =20 if (is_n) { /* The branch nullifies the next insn, which means the state o= f N after the branch is the inverse of the state of N that appl= ied to the branch. */ - tcg_gen_setcond_reg(tcg_invert_cond(c), cpu_psw_n, a0, a1); + tcg_gen_setcond_i64(tcg_invert_cond(c), cpu_psw_n, a0, a1); cond_free(&ctx->null_cond); ctx->null_cond =3D cond_make_n(); ctx->psw_n_nonzero =3D true; @@ -1920,9 +1822,9 @@ static bool do_ibranch(DisasContext *ctx, TCGv_reg de= st, * IAOQ_Next{30..31} =E2=86=90 IAOQ_Front{30..31}; * which keeps the privilege level from being increased. */ -static TCGv_reg do_ibranch_priv(DisasContext *ctx, TCGv_reg offset) +static TCGv_i64 do_ibranch_priv(DisasContext *ctx, TCGv_i64 offset) { - TCGv_reg dest; + TCGv_i64 dest; switch (ctx->privilege) { case 0: /* Privilege 0 is maximum and is allowed to decrease. */ @@ -1930,13 +1832,13 @@ static TCGv_reg do_ibranch_priv(DisasContext *ctx, = TCGv_reg offset) case 3: /* Privilege 3 is minimum and is never allowed to increase. */ dest =3D tcg_temp_new(); - tcg_gen_ori_reg(dest, offset, 3); + tcg_gen_ori_i64(dest, offset, 3); break; default: dest =3D tcg_temp_new(); - tcg_gen_andi_reg(dest, offset, -4); - tcg_gen_ori_reg(dest, dest, ctx->privilege); - tcg_gen_movcond_reg(TCG_COND_GTU, dest, dest, offset, dest, offset= ); + tcg_gen_andi_i64(dest, offset, -4); + tcg_gen_ori_i64(dest, dest, ctx->privilege); + tcg_gen_movcond_i64(TCG_COND_GTU, dest, dest, offset, dest, offset= ); break; } return dest; @@ -1959,7 +1861,7 @@ static void do_page_zero(DisasContext *ctx) case TCG_COND_NEVER: break; case TCG_COND_ALWAYS: - tcg_gen_movi_reg(cpu_psw_n, 0); + tcg_gen_movi_i64(cpu_psw_n, 0); goto do_sigill; default: /* Since this is always the first (and only) insn within the @@ -1987,9 +1889,9 @@ static void do_page_zero(DisasContext *ctx) break; =20 case 0xe0: /* SET_THREAD_POINTER */ - tcg_gen_st_reg(cpu_gr[26], tcg_env, offsetof(CPUHPPAState, cr[27])= ); - tcg_gen_ori_reg(cpu_iaoq_f, cpu_gr[31], 3); - tcg_gen_addi_reg(cpu_iaoq_b, cpu_iaoq_f, 4); + tcg_gen_st_i64(cpu_gr[26], tcg_env, offsetof(CPUHPPAState, cr[27])= ); + tcg_gen_ori_i64(cpu_iaoq_f, cpu_gr[31], 3); + tcg_gen_addi_i64(cpu_iaoq_b, cpu_iaoq_f, 4); ctx->base.is_jmp =3D DISAS_IAQ_N_UPDATED; break; =20 @@ -2030,8 +1932,8 @@ static bool trans_sync(DisasContext *ctx, arg_sync *a) static bool trans_mfia(DisasContext *ctx, arg_mfia *a) { unsigned rt =3D a->t; - TCGv_reg tmp =3D dest_gpr(ctx, rt); - tcg_gen_movi_reg(tmp, ctx->iaoq_f); + TCGv_i64 tmp =3D dest_gpr(ctx, rt); + tcg_gen_movi_i64(tmp, ctx->iaoq_f); save_gpr(ctx, rt, tmp); =20 cond_free(&ctx->null_cond); @@ -2043,7 +1945,7 @@ static bool trans_mfsp(DisasContext *ctx, arg_mfsp *a) unsigned rt =3D a->t; unsigned rs =3D a->sp; TCGv_i64 t0 =3D tcg_temp_new_i64(); - TCGv_reg t1 =3D tcg_temp_new(); + TCGv_i64 t1 =3D tcg_temp_new(); =20 load_spr(ctx, t0, rs); tcg_gen_shri_i64(t0, t0, 32); @@ -2059,14 +1961,14 @@ static bool trans_mfctl(DisasContext *ctx, arg_mfct= l *a) { unsigned rt =3D a->t; unsigned ctl =3D a->r; - TCGv_reg tmp; + TCGv_i64 tmp; =20 switch (ctl) { case CR_SAR: if (a->e =3D=3D 0) { /* MFSAR without ,W masks low 5 bits. */ tmp =3D dest_gpr(ctx, rt); - tcg_gen_andi_reg(tmp, cpu_sar, 31); + tcg_gen_andi_i64(tmp, cpu_sar, 31); save_gpr(ctx, rt, tmp); goto done; } @@ -2094,7 +1996,7 @@ static bool trans_mfctl(DisasContext *ctx, arg_mfctl = *a) } =20 tmp =3D tcg_temp_new(); - tcg_gen_ld_reg(tmp, tcg_env, offsetof(CPUHPPAState, cr[ctl])); + tcg_gen_ld_i64(tmp, tcg_env, offsetof(CPUHPPAState, cr[ctl])); save_gpr(ctx, rt, tmp); =20 done: @@ -2130,13 +2032,13 @@ static bool trans_mtsp(DisasContext *ctx, arg_mtsp = *a) static bool trans_mtctl(DisasContext *ctx, arg_mtctl *a) { unsigned ctl =3D a->t; - TCGv_reg reg; - TCGv_reg tmp; + TCGv_i64 reg; + TCGv_i64 tmp; =20 if (ctl =3D=3D CR_SAR) { reg =3D load_gpr(ctx, a->r); tmp =3D tcg_temp_new(); - tcg_gen_andi_reg(tmp, reg, ctx->is_pa20 ? 63 : 31); + tcg_gen_andi_i64(tmp, reg, ctx->is_pa20 ? 63 : 31); save_or_nullify(ctx, cpu_sar, tmp); =20 cond_free(&ctx->null_cond); @@ -2167,10 +2069,10 @@ static bool trans_mtctl(DisasContext *ctx, arg_mtct= l *a) /* FIXME: Respect PSW_Q bit */ /* The write advances the queue and stores to the back element. */ tmp =3D tcg_temp_new(); - tcg_gen_ld_reg(tmp, tcg_env, + tcg_gen_ld_i64(tmp, tcg_env, offsetof(CPUHPPAState, cr_back[ctl - CR_IIASQ])); - tcg_gen_st_reg(tmp, tcg_env, offsetof(CPUHPPAState, cr[ctl])); - tcg_gen_st_reg(reg, tcg_env, + tcg_gen_st_i64(tmp, tcg_env, offsetof(CPUHPPAState, cr[ctl])); + tcg_gen_st_i64(reg, tcg_env, offsetof(CPUHPPAState, cr_back[ctl - CR_IIASQ])); break; =20 @@ -2178,14 +2080,14 @@ static bool trans_mtctl(DisasContext *ctx, arg_mtct= l *a) case CR_PID2: case CR_PID3: case CR_PID4: - tcg_gen_st_reg(reg, tcg_env, offsetof(CPUHPPAState, cr[ctl])); + tcg_gen_st_i64(reg, tcg_env, offsetof(CPUHPPAState, cr[ctl])); #ifndef CONFIG_USER_ONLY gen_helper_change_prot_id(tcg_env); #endif break; =20 default: - tcg_gen_st_reg(reg, tcg_env, offsetof(CPUHPPAState, cr[ctl])); + tcg_gen_st_i64(reg, tcg_env, offsetof(CPUHPPAState, cr[ctl])); break; } return nullify_end(ctx); @@ -2194,10 +2096,10 @@ static bool trans_mtctl(DisasContext *ctx, arg_mtct= l *a) =20 static bool trans_mtsarcm(DisasContext *ctx, arg_mtsarcm *a) { - TCGv_reg tmp =3D tcg_temp_new(); + TCGv_i64 tmp =3D tcg_temp_new(); =20 - tcg_gen_not_reg(tmp, load_gpr(ctx, a->r)); - tcg_gen_andi_reg(tmp, tmp, ctx->is_pa20 ? 63 : 31); + tcg_gen_not_i64(tmp, load_gpr(ctx, a->r)); + tcg_gen_andi_i64(tmp, tmp, ctx->is_pa20 ? 63 : 31); save_or_nullify(ctx, cpu_sar, tmp); =20 cond_free(&ctx->null_cond); @@ -2206,11 +2108,11 @@ static bool trans_mtsarcm(DisasContext *ctx, arg_mt= sarcm *a) =20 static bool trans_ldsid(DisasContext *ctx, arg_ldsid *a) { - TCGv_reg dest =3D dest_gpr(ctx, a->t); + TCGv_i64 dest =3D dest_gpr(ctx, a->t); =20 #ifdef CONFIG_USER_ONLY /* We don't implement space registers in user mode. */ - tcg_gen_movi_reg(dest, 0); + tcg_gen_movi_i64(dest, 0); #else TCGv_i64 t0 =3D tcg_temp_new_i64(); =20 @@ -2228,13 +2130,13 @@ static bool trans_rsm(DisasContext *ctx, arg_rsm *a) { CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); #ifndef CONFIG_USER_ONLY - TCGv_reg tmp; + TCGv_i64 tmp; =20 nullify_over(ctx); =20 tmp =3D tcg_temp_new(); - tcg_gen_ld_reg(tmp, tcg_env, offsetof(CPUHPPAState, psw)); - tcg_gen_andi_reg(tmp, tmp, ~a->i); + tcg_gen_ld_i64(tmp, tcg_env, offsetof(CPUHPPAState, psw)); + tcg_gen_andi_i64(tmp, tmp, ~a->i); gen_helper_swap_system_mask(tmp, tcg_env, tmp); save_gpr(ctx, a->t, tmp); =20 @@ -2248,13 +2150,13 @@ static bool trans_ssm(DisasContext *ctx, arg_ssm *a) { CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); #ifndef CONFIG_USER_ONLY - TCGv_reg tmp; + TCGv_i64 tmp; =20 nullify_over(ctx); =20 tmp =3D tcg_temp_new(); - tcg_gen_ld_reg(tmp, tcg_env, offsetof(CPUHPPAState, psw)); - tcg_gen_ori_reg(tmp, tmp, a->i); + tcg_gen_ld_i64(tmp, tcg_env, offsetof(CPUHPPAState, psw)); + tcg_gen_ori_i64(tmp, tmp, a->i); gen_helper_swap_system_mask(tmp, tcg_env, tmp); save_gpr(ctx, a->t, tmp); =20 @@ -2268,7 +2170,7 @@ static bool trans_mtsm(DisasContext *ctx, arg_mtsm *a) { CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); #ifndef CONFIG_USER_ONLY - TCGv_reg tmp, reg; + TCGv_i64 tmp, reg; nullify_over(ctx); =20 reg =3D load_gpr(ctx, a->r); @@ -2345,12 +2247,12 @@ static bool trans_getshadowregs(DisasContext *ctx, = arg_getshadowregs *a) static bool trans_nop_addrx(DisasContext *ctx, arg_ldst *a) { if (a->m) { - TCGv_reg dest =3D dest_gpr(ctx, a->b); - TCGv_reg src1 =3D load_gpr(ctx, a->b); - TCGv_reg src2 =3D load_gpr(ctx, a->x); + TCGv_i64 dest =3D dest_gpr(ctx, a->b); + TCGv_i64 src1 =3D load_gpr(ctx, a->b); + TCGv_i64 src2 =3D load_gpr(ctx, a->x); =20 /* The only thing we need to do is the base register modification.= */ - tcg_gen_add_reg(dest, src1, src2); + tcg_gen_add_i64(dest, src1, src2); save_gpr(ctx, a->b, dest); } cond_free(&ctx->null_cond); @@ -2359,9 +2261,9 @@ static bool trans_nop_addrx(DisasContext *ctx, arg_ld= st *a) =20 static bool trans_probe(DisasContext *ctx, arg_probe *a) { - TCGv_reg dest, ofs; + TCGv_i64 dest, ofs; TCGv_i32 level, want; - TCGv_tl addr; + TCGv_i64 addr; =20 nullify_over(ctx); =20 @@ -2372,7 +2274,7 @@ static bool trans_probe(DisasContext *ctx, arg_probe = *a) level =3D tcg_constant_i32(a->ri); } else { level =3D tcg_temp_new_i32(); - tcg_gen_trunc_reg_i32(level, load_gpr(ctx, a->ri)); + tcg_gen_extrl_i64_i32(level, load_gpr(ctx, a->ri)); tcg_gen_andi_i32(level, level, 3); } want =3D tcg_constant_i32(a->write ? PAGE_WRITE : PAGE_READ); @@ -2390,8 +2292,8 @@ static bool trans_ixtlbx(DisasContext *ctx, arg_ixtlb= x *a) } CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); #ifndef CONFIG_USER_ONLY - TCGv_tl addr; - TCGv_reg ofs, reg; + TCGv_i64 addr; + TCGv_i64 ofs, reg; =20 nullify_over(ctx); =20 @@ -2415,8 +2317,8 @@ static bool trans_pxtlbx(DisasContext *ctx, arg_pxtlb= x *a) { CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); #ifndef CONFIG_USER_ONLY - TCGv_tl addr; - TCGv_reg ofs; + TCGv_i64 addr; + TCGv_i64 ofs; =20 nullify_over(ctx); =20 @@ -2451,8 +2353,8 @@ static bool trans_ixtlbxf(DisasContext *ctx, arg_ixtl= bxf *a) } CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); #ifndef CONFIG_USER_ONLY - TCGv_tl addr, atl, stl; - TCGv_reg reg; + TCGv_i64 addr, atl, stl; + TCGv_i64 reg; =20 nullify_over(ctx); =20 @@ -2462,9 +2364,9 @@ static bool trans_ixtlbxf(DisasContext *ctx, arg_ixtl= bxf *a) * return gen_illegal(ctx); */ =20 - atl =3D tcg_temp_new_tl(); - stl =3D tcg_temp_new_tl(); - addr =3D tcg_temp_new_tl(); + atl =3D tcg_temp_new_i64(); + stl =3D tcg_temp_new_i64(); + addr =3D tcg_temp_new_i64(); =20 tcg_gen_ld32u_i64(stl, tcg_env, a->data ? offsetof(CPUHPPAState, cr[CR_ISR]) @@ -2513,8 +2415,8 @@ static bool trans_lpa(DisasContext *ctx, arg_ldst *a) { CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); #ifndef CONFIG_USER_ONLY - TCGv_tl vaddr; - TCGv_reg ofs, paddr; + TCGv_i64 vaddr; + TCGv_i64 ofs, paddr; =20 nullify_over(ctx); =20 @@ -2541,7 +2443,7 @@ static bool trans_lci(DisasContext *ctx, arg_lci *a) physical address. Two addresses with the same CI have a coherent view of the cache. Our implementation is to return 0 for all, since the entire address space is coherent. */ - save_gpr(ctx, a->t, tcg_constant_reg(0)); + save_gpr(ctx, a->t, tcg_constant_i64(0)); =20 cond_free(&ctx->null_cond); return true; @@ -2604,12 +2506,12 @@ static bool trans_sub_b_tsv(DisasContext *ctx, arg_= rrr_cf_d *a) =20 static bool trans_andcm(DisasContext *ctx, arg_rrr_cf_d *a) { - return do_log_reg(ctx, a, tcg_gen_andc_reg); + return do_log_reg(ctx, a, tcg_gen_andc_i64); } =20 static bool trans_and(DisasContext *ctx, arg_rrr_cf_d *a) { - return do_log_reg(ctx, a, tcg_gen_and_reg); + return do_log_reg(ctx, a, tcg_gen_and_i64); } =20 static bool trans_or(DisasContext *ctx, arg_rrr_cf_d *a) @@ -2625,8 +2527,8 @@ static bool trans_or(DisasContext *ctx, arg_rrr_cf_d = *a) } if (r2 =3D=3D 0) { /* COPY */ if (r1 =3D=3D 0) { - TCGv_reg dest =3D dest_gpr(ctx, rt); - tcg_gen_movi_reg(dest, 0); + TCGv_i64 dest =3D dest_gpr(ctx, rt); + tcg_gen_movi_i64(dest, 0); save_gpr(ctx, rt, dest); } else { save_gpr(ctx, rt, cpu_gr[r1]); @@ -2661,17 +2563,17 @@ static bool trans_or(DisasContext *ctx, arg_rrr_cf_= d *a) } #endif } - return do_log_reg(ctx, a, tcg_gen_or_reg); + return do_log_reg(ctx, a, tcg_gen_or_i64); } =20 static bool trans_xor(DisasContext *ctx, arg_rrr_cf_d *a) { - return do_log_reg(ctx, a, tcg_gen_xor_reg); + return do_log_reg(ctx, a, tcg_gen_xor_i64); } =20 static bool trans_cmpclr(DisasContext *ctx, arg_rrr_cf_d *a) { - TCGv_reg tcg_r1, tcg_r2; + TCGv_i64 tcg_r1, tcg_r2; =20 if (a->cf) { nullify_over(ctx); @@ -2684,20 +2586,20 @@ static bool trans_cmpclr(DisasContext *ctx, arg_rrr= _cf_d *a) =20 static bool trans_uxor(DisasContext *ctx, arg_rrr_cf_d *a) { - TCGv_reg tcg_r1, tcg_r2; + TCGv_i64 tcg_r1, tcg_r2; =20 if (a->cf) { nullify_over(ctx); } tcg_r1 =3D load_gpr(ctx, a->r1); tcg_r2 =3D load_gpr(ctx, a->r2); - do_unit(ctx, a->t, tcg_r1, tcg_r2, a->cf, a->d, false, tcg_gen_xor_reg= ); + do_unit(ctx, a->t, tcg_r1, tcg_r2, a->cf, a->d, false, tcg_gen_xor_i64= ); return nullify_end(ctx); } =20 static bool do_uaddcm(DisasContext *ctx, arg_rrr_cf_d *a, bool is_tc) { - TCGv_reg tcg_r1, tcg_r2, tmp; + TCGv_i64 tcg_r1, tcg_r2, tmp; =20 if (a->cf) { nullify_over(ctx); @@ -2705,8 +2607,8 @@ static bool do_uaddcm(DisasContext *ctx, arg_rrr_cf_d= *a, bool is_tc) tcg_r1 =3D load_gpr(ctx, a->r1); tcg_r2 =3D load_gpr(ctx, a->r2); tmp =3D tcg_temp_new(); - tcg_gen_not_reg(tmp, tcg_r2); - do_unit(ctx, a->t, tcg_r1, tmp, a->cf, a->d, is_tc, tcg_gen_add_reg); + tcg_gen_not_i64(tmp, tcg_r2); + do_unit(ctx, a->t, tcg_r1, tmp, a->cf, a->d, is_tc, tcg_gen_add_i64); return nullify_end(ctx); } =20 @@ -2722,19 +2624,19 @@ static bool trans_uaddcm_tc(DisasContext *ctx, arg_= rrr_cf_d *a) =20 static bool do_dcor(DisasContext *ctx, arg_rr_cf_d *a, bool is_i) { - TCGv_reg tmp; + TCGv_i64 tmp; =20 nullify_over(ctx); =20 tmp =3D tcg_temp_new(); - tcg_gen_shri_reg(tmp, cpu_psw_cb, 3); + tcg_gen_shri_i64(tmp, cpu_psw_cb, 3); if (!is_i) { - tcg_gen_not_reg(tmp, tmp); + tcg_gen_not_i64(tmp, tmp); } - tcg_gen_andi_reg(tmp, tmp, (uint64_t)0x1111111111111111ull); - tcg_gen_muli_reg(tmp, tmp, 6); + tcg_gen_andi_i64(tmp, tmp, (uint64_t)0x1111111111111111ull); + tcg_gen_muli_i64(tmp, tmp, 6); do_unit(ctx, a->t, load_gpr(ctx, a->r), tmp, a->cf, a->d, false, - is_i ? tcg_gen_add_reg : tcg_gen_sub_reg); + is_i ? tcg_gen_add_i64 : tcg_gen_sub_i64); return nullify_end(ctx); } =20 @@ -2750,8 +2652,8 @@ static bool trans_dcor_i(DisasContext *ctx, arg_rr_cf= _d *a) =20 static bool trans_ds(DisasContext *ctx, arg_rrr_cf *a) { - TCGv_reg dest, add1, add2, addc, zero, in1, in2; - TCGv_reg cout; + TCGv_i64 dest, add1, add2, addc, zero, in1, in2; + TCGv_i64 cout; =20 nullify_over(ctx); =20 @@ -2762,11 +2664,11 @@ static bool trans_ds(DisasContext *ctx, arg_rrr_cf = *a) add2 =3D tcg_temp_new(); addc =3D tcg_temp_new(); dest =3D tcg_temp_new(); - zero =3D tcg_constant_reg(0); + zero =3D tcg_constant_i64(0); =20 /* Form R1 << 1 | PSW[CB]{8}. */ - tcg_gen_add_reg(add1, in1, in1); - tcg_gen_add_reg(add1, add1, get_psw_carry(ctx, false)); + tcg_gen_add_i64(add1, in1, in1); + tcg_gen_add_i64(add1, add1, get_psw_carry(ctx, false)); =20 /* * Add or subtract R2, depending on PSW[V]. Proper computation of @@ -2774,28 +2676,28 @@ static bool trans_ds(DisasContext *ctx, arg_rrr_cf = *a) * the manual. By extracting and masking V, we can produce the * proper inputs to the addition without movcond. */ - tcg_gen_sextract_reg(addc, cpu_psw_v, 31, 1); - tcg_gen_xor_reg(add2, in2, addc); - tcg_gen_andi_reg(addc, addc, 1); + tcg_gen_sextract_i64(addc, cpu_psw_v, 31, 1); + tcg_gen_xor_i64(add2, in2, addc); + tcg_gen_andi_i64(addc, addc, 1); =20 - tcg_gen_add2_reg(dest, cpu_psw_cb_msb, add1, zero, add2, zero); - tcg_gen_add2_reg(dest, cpu_psw_cb_msb, dest, cpu_psw_cb_msb, addc, zer= o); + tcg_gen_add2_i64(dest, cpu_psw_cb_msb, add1, zero, add2, zero); + tcg_gen_add2_i64(dest, cpu_psw_cb_msb, dest, cpu_psw_cb_msb, addc, zer= o); =20 /* Write back the result register. */ save_gpr(ctx, a->t, dest); =20 /* Write back PSW[CB]. */ - tcg_gen_xor_reg(cpu_psw_cb, add1, add2); - tcg_gen_xor_reg(cpu_psw_cb, cpu_psw_cb, dest); + tcg_gen_xor_i64(cpu_psw_cb, add1, add2); + tcg_gen_xor_i64(cpu_psw_cb, cpu_psw_cb, dest); =20 /* Write back PSW[V] for the division step. */ cout =3D get_psw_carry(ctx, false); - tcg_gen_neg_reg(cpu_psw_v, cout); - tcg_gen_xor_reg(cpu_psw_v, cpu_psw_v, in2); + tcg_gen_neg_i64(cpu_psw_v, cout); + tcg_gen_xor_i64(cpu_psw_v, cpu_psw_v, in2); =20 /* Install the new nullification. */ if (a->cf) { - TCGv_reg sv =3D NULL; + TCGv_i64 sv =3D NULL; if (cond_need_sv(a->cf >> 1)) { /* ??? The lshift is supposed to contribute to overflow. */ sv =3D do_add_sv(ctx, dest, add1, add2); @@ -2838,13 +2740,13 @@ static bool trans_subi_tsv(DisasContext *ctx, arg_r= ri_cf *a) =20 static bool trans_cmpiclr(DisasContext *ctx, arg_rri_cf_d *a) { - TCGv_reg tcg_im, tcg_r2; + TCGv_i64 tcg_im, tcg_r2; =20 if (a->cf) { nullify_over(ctx); } =20 - tcg_im =3D tcg_constant_reg(a->i); + tcg_im =3D tcg_constant_i64(a->i); tcg_r2 =3D load_gpr(ctx, a->r); do_cmpclr(ctx, a->t, tcg_im, tcg_r2, a->cf, a->d); =20 @@ -2872,8 +2774,8 @@ static bool trans_st(DisasContext *ctx, arg_ldst *a) static bool trans_ldc(DisasContext *ctx, arg_ldst *a) { MemOp mop =3D MO_TE | MO_ALIGN | a->size; - TCGv_reg zero, dest, ofs; - TCGv_tl addr; + TCGv_i64 zero, dest, ofs; + TCGv_i64 addr; =20 if (!ctx->is_pa20 && a->size > MO_32) { return gen_illegal(ctx); @@ -2902,8 +2804,8 @@ static bool trans_ldc(DisasContext *ctx, arg_ldst *a) */ gen_helper_ldc_check(addr); =20 - zero =3D tcg_constant_reg(0); - tcg_gen_atomic_xchg_reg(dest, addr, zero, ctx->mmu_idx, mop); + zero =3D tcg_constant_i64(0); + tcg_gen_atomic_xchg_i64(dest, addr, zero, ctx->mmu_idx, mop); =20 if (a->m) { save_gpr(ctx, a->b, ofs); @@ -2915,8 +2817,8 @@ static bool trans_ldc(DisasContext *ctx, arg_ldst *a) =20 static bool trans_stby(DisasContext *ctx, arg_stby *a) { - TCGv_reg ofs, val; - TCGv_tl addr; + TCGv_i64 ofs, val; + TCGv_i64 addr; =20 nullify_over(ctx); =20 @@ -2937,7 +2839,7 @@ static bool trans_stby(DisasContext *ctx, arg_stby *a) } } if (a->m) { - tcg_gen_andi_reg(ofs, ofs, ~3); + tcg_gen_andi_i64(ofs, ofs, ~3); save_gpr(ctx, a->b, ofs); } =20 @@ -2946,8 +2848,8 @@ static bool trans_stby(DisasContext *ctx, arg_stby *a) =20 static bool trans_stdby(DisasContext *ctx, arg_stby *a) { - TCGv_reg ofs, val; - TCGv_tl addr; + TCGv_i64 ofs, val; + TCGv_i64 addr; =20 nullify_over(ctx); =20 @@ -2968,7 +2870,7 @@ static bool trans_stdby(DisasContext *ctx, arg_stby *= a) } } if (a->m) { - tcg_gen_andi_reg(ofs, ofs, ~7); + tcg_gen_andi_i64(ofs, ofs, ~7); save_gpr(ctx, a->b, ofs); } =20 @@ -2999,9 +2901,9 @@ static bool trans_sta(DisasContext *ctx, arg_ldst *a) =20 static bool trans_ldil(DisasContext *ctx, arg_ldil *a) { - TCGv_reg tcg_rt =3D dest_gpr(ctx, a->t); + TCGv_i64 tcg_rt =3D dest_gpr(ctx, a->t); =20 - tcg_gen_movi_reg(tcg_rt, a->i); + tcg_gen_movi_i64(tcg_rt, a->i); save_gpr(ctx, a->t, tcg_rt); cond_free(&ctx->null_cond); return true; @@ -3009,10 +2911,10 @@ static bool trans_ldil(DisasContext *ctx, arg_ldil = *a) =20 static bool trans_addil(DisasContext *ctx, arg_addil *a) { - TCGv_reg tcg_rt =3D load_gpr(ctx, a->r); - TCGv_reg tcg_r1 =3D dest_gpr(ctx, 1); + TCGv_i64 tcg_rt =3D load_gpr(ctx, a->r); + TCGv_i64 tcg_r1 =3D dest_gpr(ctx, 1); =20 - tcg_gen_addi_reg(tcg_r1, tcg_rt, a->i); + tcg_gen_addi_i64(tcg_r1, tcg_rt, a->i); save_gpr(ctx, 1, tcg_r1); cond_free(&ctx->null_cond); return true; @@ -3020,30 +2922,30 @@ static bool trans_addil(DisasContext *ctx, arg_addi= l *a) =20 static bool trans_ldo(DisasContext *ctx, arg_ldo *a) { - TCGv_reg tcg_rt =3D dest_gpr(ctx, a->t); + TCGv_i64 tcg_rt =3D dest_gpr(ctx, a->t); =20 /* Special case rb =3D=3D 0, for the LDI pseudo-op. The COPY pseudo-op is handled for free within tcg_gen_addi_tl. */ if (a->b =3D=3D 0) { - tcg_gen_movi_reg(tcg_rt, a->i); + tcg_gen_movi_i64(tcg_rt, a->i); } else { - tcg_gen_addi_reg(tcg_rt, cpu_gr[a->b], a->i); + tcg_gen_addi_i64(tcg_rt, cpu_gr[a->b], a->i); } save_gpr(ctx, a->t, tcg_rt); cond_free(&ctx->null_cond); return true; } =20 -static bool do_cmpb(DisasContext *ctx, unsigned r, TCGv_reg in1, +static bool do_cmpb(DisasContext *ctx, unsigned r, TCGv_i64 in1, unsigned c, unsigned f, bool d, unsigned n, int disp) { - TCGv_reg dest, in2, sv; + TCGv_i64 dest, in2, sv; DisasCond cond; =20 in2 =3D load_gpr(ctx, r); dest =3D tcg_temp_new(); =20 - tcg_gen_sub_reg(dest, in1, in2); + tcg_gen_sub_i64(dest, in1, in2); =20 sv =3D NULL; if (cond_need_sv(c)) { @@ -3070,14 +2972,14 @@ static bool trans_cmpbi(DisasContext *ctx, arg_cmpb= i *a) return false; } nullify_over(ctx); - return do_cmpb(ctx, a->r, tcg_constant_reg(a->i), + return do_cmpb(ctx, a->r, tcg_constant_i64(a->i), a->c, a->f, a->d, a->n, a->disp); } =20 -static bool do_addb(DisasContext *ctx, unsigned r, TCGv_reg in1, +static bool do_addb(DisasContext *ctx, unsigned r, TCGv_i64 in1, unsigned c, unsigned f, unsigned n, int disp) { - TCGv_reg dest, in2, sv, cb_cond; + TCGv_i64 dest, in2, sv, cb_cond; DisasCond cond; bool d =3D false; =20 @@ -3098,16 +3000,16 @@ static bool do_addb(DisasContext *ctx, unsigned r, = TCGv_reg in1, cb_cond =3D NULL; =20 if (cond_need_cb(c)) { - TCGv_reg cb =3D tcg_temp_new(); - TCGv_reg cb_msb =3D tcg_temp_new(); + TCGv_i64 cb =3D tcg_temp_new(); + TCGv_i64 cb_msb =3D tcg_temp_new(); =20 - tcg_gen_movi_reg(cb_msb, 0); - tcg_gen_add2_reg(dest, cb_msb, in1, cb_msb, in2, cb_msb); - tcg_gen_xor_reg(cb, in1, in2); - tcg_gen_xor_reg(cb, cb, dest); + tcg_gen_movi_i64(cb_msb, 0); + tcg_gen_add2_i64(dest, cb_msb, in1, cb_msb, in2, cb_msb); + tcg_gen_xor_i64(cb, in1, in2); + tcg_gen_xor_i64(cb, cb, dest); cb_cond =3D get_carry(ctx, d, cb, cb_msb); } else { - tcg_gen_add_reg(dest, in1, in2); + tcg_gen_add_i64(dest, in1, in2); } if (cond_need_sv(c)) { sv =3D do_add_sv(ctx, dest, in1, in2); @@ -3127,12 +3029,12 @@ static bool trans_addb(DisasContext *ctx, arg_addb = *a) static bool trans_addbi(DisasContext *ctx, arg_addbi *a) { nullify_over(ctx); - return do_addb(ctx, a->r, tcg_constant_reg(a->i), a->c, a->f, a->n, a-= >disp); + return do_addb(ctx, a->r, tcg_constant_i64(a->i), a->c, a->f, a->n, a-= >disp); } =20 static bool trans_bb_sar(DisasContext *ctx, arg_bb_sar *a) { - TCGv_reg tmp, tcg_r; + TCGv_i64 tmp, tcg_r; DisasCond cond; =20 nullify_over(ctx); @@ -3141,10 +3043,10 @@ static bool trans_bb_sar(DisasContext *ctx, arg_bb_= sar *a) tcg_r =3D load_gpr(ctx, a->r); if (cond_need_ext(ctx, a->d)) { /* Force shift into [32,63] */ - tcg_gen_ori_reg(tmp, cpu_sar, 32); - tcg_gen_shl_reg(tmp, tcg_r, tmp); + tcg_gen_ori_i64(tmp, cpu_sar, 32); + tcg_gen_shl_i64(tmp, tcg_r, tmp); } else { - tcg_gen_shl_reg(tmp, tcg_r, cpu_sar); + tcg_gen_shl_i64(tmp, tcg_r, cpu_sar); } =20 cond =3D cond_make_0_tmp(a->c ? TCG_COND_GE : TCG_COND_LT, tmp); @@ -3153,7 +3055,7 @@ static bool trans_bb_sar(DisasContext *ctx, arg_bb_sa= r *a) =20 static bool trans_bb_imm(DisasContext *ctx, arg_bb_imm *a) { - TCGv_reg tmp, tcg_r; + TCGv_i64 tmp, tcg_r; DisasCond cond; int p; =20 @@ -3162,7 +3064,7 @@ static bool trans_bb_imm(DisasContext *ctx, arg_bb_im= m *a) tmp =3D tcg_temp_new(); tcg_r =3D load_gpr(ctx, a->r); p =3D a->p | (cond_need_ext(ctx, a->d) ? 32 : 0); - tcg_gen_shli_reg(tmp, tcg_r, p); + tcg_gen_shli_i64(tmp, tcg_r, p); =20 cond =3D cond_make_0(a->c ? TCG_COND_GE : TCG_COND_LT, tmp); return do_cbranch(ctx, a->disp, a->n, &cond); @@ -3170,16 +3072,16 @@ static bool trans_bb_imm(DisasContext *ctx, arg_bb_= imm *a) =20 static bool trans_movb(DisasContext *ctx, arg_movb *a) { - TCGv_reg dest; + TCGv_i64 dest; DisasCond cond; =20 nullify_over(ctx); =20 dest =3D dest_gpr(ctx, a->r2); if (a->r1 =3D=3D 0) { - tcg_gen_movi_reg(dest, 0); + tcg_gen_movi_i64(dest, 0); } else { - tcg_gen_mov_reg(dest, cpu_gr[a->r1]); + tcg_gen_mov_i64(dest, cpu_gr[a->r1]); } =20 /* All MOVB conditions are 32-bit. */ @@ -3189,13 +3091,13 @@ static bool trans_movb(DisasContext *ctx, arg_movb = *a) =20 static bool trans_movbi(DisasContext *ctx, arg_movbi *a) { - TCGv_reg dest; + TCGv_i64 dest; DisasCond cond; =20 nullify_over(ctx); =20 dest =3D dest_gpr(ctx, a->r); - tcg_gen_movi_reg(dest, a->i); + tcg_gen_movi_i64(dest, a->i); =20 /* All MOVBI conditions are 32-bit. */ cond =3D do_sed_cond(ctx, a->c, false, dest); @@ -3204,7 +3106,7 @@ static bool trans_movbi(DisasContext *ctx, arg_movbi = *a) =20 static bool trans_shrp_sar(DisasContext *ctx, arg_shrp_sar *a) { - TCGv_reg dest, tmp; + TCGv_i64 dest, tmp; =20 if (!ctx->is_pa20 && a->d) { return false; @@ -3216,40 +3118,40 @@ static bool trans_shrp_sar(DisasContext *ctx, arg_s= hrp_sar *a) dest =3D dest_gpr(ctx, a->t); if (a->r1 =3D=3D 0) { if (a->d) { - tcg_gen_shr_reg(dest, dest, cpu_sar); + tcg_gen_shr_i64(dest, dest, cpu_sar); } else { - tcg_gen_ext32u_reg(dest, load_gpr(ctx, a->r2)); + tcg_gen_ext32u_i64(dest, load_gpr(ctx, a->r2)); tmp =3D tcg_temp_new(); - tcg_gen_andi_reg(tmp, cpu_sar, 31); - tcg_gen_shr_reg(dest, dest, tmp); + tcg_gen_andi_i64(tmp, cpu_sar, 31); + tcg_gen_shr_i64(dest, dest, tmp); } } else if (a->r1 =3D=3D a->r2) { if (a->d) { - tcg_gen_rotr_reg(dest, load_gpr(ctx, a->r2), cpu_sar); + tcg_gen_rotr_i64(dest, load_gpr(ctx, a->r2), cpu_sar); } else { TCGv_i32 t32 =3D tcg_temp_new_i32(); TCGv_i32 s32 =3D tcg_temp_new_i32(); =20 - tcg_gen_trunc_reg_i32(t32, load_gpr(ctx, a->r2)); - tcg_gen_trunc_reg_i32(s32, cpu_sar); + tcg_gen_extrl_i64_i32(t32, load_gpr(ctx, a->r2)); + tcg_gen_extrl_i64_i32(s32, cpu_sar); tcg_gen_andi_i32(s32, s32, 31); tcg_gen_rotr_i32(t32, t32, s32); - tcg_gen_extu_i32_reg(dest, t32); + tcg_gen_extu_i32_i64(dest, t32); } } else if (a->d) { - TCGv_reg t =3D tcg_temp_new(); - TCGv_reg n =3D tcg_temp_new(); + TCGv_i64 t =3D tcg_temp_new(); + TCGv_i64 n =3D tcg_temp_new(); =20 - tcg_gen_xori_reg(n, cpu_sar, 63); - tcg_gen_shl_reg(t, load_gpr(ctx, a->r2), n); - tcg_gen_shli_reg(t, t, 1); - tcg_gen_shr_reg(dest, load_gpr(ctx, a->r1), cpu_sar); - tcg_gen_or_reg(dest, dest, t); + tcg_gen_xori_i64(n, cpu_sar, 63); + tcg_gen_shl_i64(t, load_gpr(ctx, a->r2), n); + tcg_gen_shli_i64(t, t, 1); + tcg_gen_shr_i64(dest, load_gpr(ctx, a->r1), cpu_sar); + tcg_gen_or_i64(dest, dest, t); } else { TCGv_i64 t =3D tcg_temp_new_i64(); TCGv_i64 s =3D tcg_temp_new_i64(); =20 - tcg_gen_concat_reg_i64(t, load_gpr(ctx, a->r2), load_gpr(ctx, a->r= 1)); + tcg_gen_concat32_i64(t, load_gpr(ctx, a->r2), load_gpr(ctx, a->r1)= ); tcg_gen_extu_reg_i64(s, cpu_sar); tcg_gen_andi_i64(s, s, 31); tcg_gen_shr_i64(t, t, s); @@ -3268,7 +3170,7 @@ static bool trans_shrp_sar(DisasContext *ctx, arg_shr= p_sar *a) static bool trans_shrp_imm(DisasContext *ctx, arg_shrp_imm *a) { unsigned width, sa; - TCGv_reg dest, t2; + TCGv_i64 dest, t2; =20 if (!ctx->is_pa20 && a->d) { return false; @@ -3283,19 +3185,19 @@ static bool trans_shrp_imm(DisasContext *ctx, arg_s= hrp_imm *a) dest =3D dest_gpr(ctx, a->t); t2 =3D load_gpr(ctx, a->r2); if (a->r1 =3D=3D 0) { - tcg_gen_extract_reg(dest, t2, sa, width - sa); + tcg_gen_extract_i64(dest, t2, sa, width - sa); } else if (width =3D=3D TARGET_LONG_BITS) { - tcg_gen_extract2_reg(dest, t2, cpu_gr[a->r1], sa); + tcg_gen_extract2_i64(dest, t2, cpu_gr[a->r1], sa); } else { assert(!a->d); if (a->r1 =3D=3D a->r2) { TCGv_i32 t32 =3D tcg_temp_new_i32(); - tcg_gen_trunc_reg_i32(t32, t2); + tcg_gen_extrl_i64_i32(t32, t2); tcg_gen_rotri_i32(t32, t32, sa); - tcg_gen_extu_i32_reg(dest, t32); + tcg_gen_extu_i32_i64(dest, t32); } else { TCGv_i64 t64 =3D tcg_temp_new_i64(); - tcg_gen_concat_reg_i64(t64, t2, cpu_gr[a->r1]); + tcg_gen_concat32_i64(t64, t2, cpu_gr[a->r1]); tcg_gen_shri_i64(t64, t64, sa); tcg_gen_trunc_i64_reg(dest, t64); } @@ -3313,7 +3215,7 @@ static bool trans_shrp_imm(DisasContext *ctx, arg_shr= p_imm *a) static bool trans_extr_sar(DisasContext *ctx, arg_extr_sar *a) { unsigned widthm1 =3D a->d ? 63 : 31; - TCGv_reg dest, src, tmp; + TCGv_i64 dest, src, tmp; =20 if (!ctx->is_pa20 && a->d) { return false; @@ -3327,15 +3229,15 @@ static bool trans_extr_sar(DisasContext *ctx, arg_e= xtr_sar *a) tmp =3D tcg_temp_new(); =20 /* Recall that SAR is using big-endian bit numbering. */ - tcg_gen_andi_reg(tmp, cpu_sar, widthm1); - tcg_gen_xori_reg(tmp, tmp, widthm1); + tcg_gen_andi_i64(tmp, cpu_sar, widthm1); + tcg_gen_xori_i64(tmp, tmp, widthm1); =20 if (a->se) { - tcg_gen_sar_reg(dest, src, tmp); - tcg_gen_sextract_reg(dest, dest, 0, a->len); + tcg_gen_sar_i64(dest, src, tmp); + tcg_gen_sextract_i64(dest, dest, 0, a->len); } else { - tcg_gen_shr_reg(dest, src, tmp); - tcg_gen_extract_reg(dest, dest, 0, a->len); + tcg_gen_shr_i64(dest, src, tmp); + tcg_gen_extract_i64(dest, dest, 0, a->len); } save_gpr(ctx, a->t, dest); =20 @@ -3350,7 +3252,7 @@ static bool trans_extr_sar(DisasContext *ctx, arg_ext= r_sar *a) static bool trans_extr_imm(DisasContext *ctx, arg_extr_imm *a) { unsigned len, cpos, width; - TCGv_reg dest, src; + TCGv_i64 dest, src; =20 if (!ctx->is_pa20 && a->d) { return false; @@ -3369,9 +3271,9 @@ static bool trans_extr_imm(DisasContext *ctx, arg_ext= r_imm *a) dest =3D dest_gpr(ctx, a->t); src =3D load_gpr(ctx, a->r); if (a->se) { - tcg_gen_sextract_reg(dest, src, cpos, len); + tcg_gen_sextract_i64(dest, src, cpos, len); } else { - tcg_gen_extract_reg(dest, src, cpos, len); + tcg_gen_extract_i64(dest, src, cpos, len); } save_gpr(ctx, a->t, dest); =20 @@ -3387,7 +3289,7 @@ static bool trans_depi_imm(DisasContext *ctx, arg_dep= i_imm *a) { unsigned len, width; uint64_t mask0, mask1; - TCGv_reg dest; + TCGv_i64 dest; =20 if (!ctx->is_pa20 && a->d) { return false; @@ -3407,11 +3309,11 @@ static bool trans_depi_imm(DisasContext *ctx, arg_d= epi_imm *a) mask1 =3D deposit64(-1, a->cpos, len, a->i); =20 if (a->nz) { - TCGv_reg src =3D load_gpr(ctx, a->t); - tcg_gen_andi_reg(dest, src, mask1); - tcg_gen_ori_reg(dest, dest, mask0); + TCGv_i64 src =3D load_gpr(ctx, a->t); + tcg_gen_andi_i64(dest, src, mask1); + tcg_gen_ori_i64(dest, dest, mask0); } else { - tcg_gen_movi_reg(dest, mask0); + tcg_gen_movi_i64(dest, mask0); } save_gpr(ctx, a->t, dest); =20 @@ -3427,7 +3329,7 @@ static bool trans_dep_imm(DisasContext *ctx, arg_dep_= imm *a) { unsigned rs =3D a->nz ? a->t : 0; unsigned len, width; - TCGv_reg dest, val; + TCGv_i64 dest, val; =20 if (!ctx->is_pa20 && a->d) { return false; @@ -3445,9 +3347,9 @@ static bool trans_dep_imm(DisasContext *ctx, arg_dep_= imm *a) dest =3D dest_gpr(ctx, a->t); val =3D load_gpr(ctx, a->r); if (rs =3D=3D 0) { - tcg_gen_deposit_z_reg(dest, val, a->cpos, len); + tcg_gen_deposit_z_i64(dest, val, a->cpos, len); } else { - tcg_gen_deposit_reg(dest, cpu_gr[rs], val, a->cpos, len); + tcg_gen_deposit_i64(dest, cpu_gr[rs], val, a->cpos, len); } save_gpr(ctx, a->t, dest); =20 @@ -3460,11 +3362,11 @@ static bool trans_dep_imm(DisasContext *ctx, arg_de= p_imm *a) } =20 static bool do_dep_sar(DisasContext *ctx, unsigned rt, unsigned c, - bool d, bool nz, unsigned len, TCGv_reg val) + bool d, bool nz, unsigned len, TCGv_i64 val) { unsigned rs =3D nz ? rt : 0; unsigned widthm1 =3D d ? 63 : 31; - TCGv_reg mask, tmp, shift, dest; + TCGv_i64 mask, tmp, shift, dest; uint64_t msb =3D 1ULL << (len - 1); =20 dest =3D dest_gpr(ctx, rt); @@ -3472,19 +3374,19 @@ static bool do_dep_sar(DisasContext *ctx, unsigned = rt, unsigned c, tmp =3D tcg_temp_new(); =20 /* Convert big-endian bit numbering in SAR to left-shift. */ - tcg_gen_andi_reg(shift, cpu_sar, widthm1); - tcg_gen_xori_reg(shift, shift, widthm1); + tcg_gen_andi_i64(shift, cpu_sar, widthm1); + tcg_gen_xori_i64(shift, shift, widthm1); =20 mask =3D tcg_temp_new(); - tcg_gen_movi_reg(mask, msb + (msb - 1)); - tcg_gen_and_reg(tmp, val, mask); + tcg_gen_movi_i64(mask, msb + (msb - 1)); + tcg_gen_and_i64(tmp, val, mask); if (rs) { - tcg_gen_shl_reg(mask, mask, shift); - tcg_gen_shl_reg(tmp, tmp, shift); - tcg_gen_andc_reg(dest, cpu_gr[rs], mask); - tcg_gen_or_reg(dest, dest, tmp); + tcg_gen_shl_i64(mask, mask, shift); + tcg_gen_shl_i64(tmp, tmp, shift); + tcg_gen_andc_i64(dest, cpu_gr[rs], mask); + tcg_gen_or_i64(dest, dest, tmp); } else { - tcg_gen_shl_reg(dest, tmp, shift); + tcg_gen_shl_i64(dest, tmp, shift); } save_gpr(ctx, rt, dest); =20 @@ -3517,12 +3419,12 @@ static bool trans_depi_sar(DisasContext *ctx, arg_d= epi_sar *a) nullify_over(ctx); } return do_dep_sar(ctx, a->t, a->c, a->d, a->nz, a->len, - tcg_constant_reg(a->i)); + tcg_constant_i64(a->i)); } =20 static bool trans_be(DisasContext *ctx, arg_be *a) { - TCGv_reg tmp; + TCGv_i64 tmp; =20 #ifdef CONFIG_USER_ONLY /* ??? It seems like there should be a good way of using @@ -3541,7 +3443,7 @@ static bool trans_be(DisasContext *ctx, arg_be *a) #endif =20 tmp =3D tcg_temp_new(); - tcg_gen_addi_reg(tmp, load_gpr(ctx, a->b), a->disp); + tcg_gen_addi_i64(tmp, load_gpr(ctx, a->b), a->disp); tmp =3D do_ibranch_priv(ctx, tmp); =20 #ifdef CONFIG_USER_ONLY @@ -3555,8 +3457,8 @@ static bool trans_be(DisasContext *ctx, arg_be *a) tcg_gen_mov_i64(cpu_sr[0], cpu_iasq_f); } if (a->n && use_nullify_skip(ctx)) { - tcg_gen_mov_reg(cpu_iaoq_f, tmp); - tcg_gen_addi_reg(cpu_iaoq_b, cpu_iaoq_f, 4); + tcg_gen_mov_i64(cpu_iaoq_f, tmp); + tcg_gen_addi_i64(cpu_iaoq_b, cpu_iaoq_f, 4); tcg_gen_mov_i64(cpu_iasq_f, new_spc); tcg_gen_mov_i64(cpu_iasq_b, cpu_iasq_f); } else { @@ -3564,7 +3466,7 @@ static bool trans_be(DisasContext *ctx, arg_be *a) if (ctx->iaoq_b =3D=3D -1) { tcg_gen_mov_i64(cpu_iasq_f, cpu_iasq_b); } - tcg_gen_mov_reg(cpu_iaoq_b, tmp); + tcg_gen_mov_i64(cpu_iaoq_b, tmp); tcg_gen_mov_i64(cpu_iasq_b, new_spc); nullify_set(ctx, a->n); } @@ -3623,11 +3525,11 @@ static bool trans_b_gate(DisasContext *ctx, arg_b_g= ate *a) #endif =20 if (a->l) { - TCGv_reg tmp =3D dest_gpr(ctx, a->l); + TCGv_i64 tmp =3D dest_gpr(ctx, a->l); if (ctx->privilege < 3) { - tcg_gen_andi_reg(tmp, tmp, -4); + tcg_gen_andi_i64(tmp, tmp, -4); } - tcg_gen_ori_reg(tmp, tmp, ctx->privilege); + tcg_gen_ori_i64(tmp, tmp, ctx->privilege); save_gpr(ctx, a->l, tmp); } =20 @@ -3637,9 +3539,9 @@ static bool trans_b_gate(DisasContext *ctx, arg_b_gat= e *a) static bool trans_blr(DisasContext *ctx, arg_blr *a) { if (a->x) { - TCGv_reg tmp =3D tcg_temp_new(); - tcg_gen_shli_reg(tmp, load_gpr(ctx, a->x), 3); - tcg_gen_addi_reg(tmp, tmp, ctx->iaoq_f + 8); + TCGv_i64 tmp =3D tcg_temp_new(); + tcg_gen_shli_i64(tmp, load_gpr(ctx, a->x), 3); + tcg_gen_addi_i64(tmp, tmp, ctx->iaoq_f + 8); /* The computation here never changes privilege level. */ return do_ibranch(ctx, tmp, a->l, a->n); } else { @@ -3650,14 +3552,14 @@ static bool trans_blr(DisasContext *ctx, arg_blr *a) =20 static bool trans_bv(DisasContext *ctx, arg_bv *a) { - TCGv_reg dest; + TCGv_i64 dest; =20 if (a->x =3D=3D 0) { dest =3D load_gpr(ctx, a->b); } else { dest =3D tcg_temp_new(); - tcg_gen_shli_reg(dest, load_gpr(ctx, a->x), 3); - tcg_gen_add_reg(dest, dest, load_gpr(ctx, a->b)); + tcg_gen_shli_i64(dest, load_gpr(ctx, a->x), 3); + tcg_gen_add_i64(dest, dest, load_gpr(ctx, a->b)); } dest =3D do_ibranch_priv(ctx, dest); return do_ibranch(ctx, dest, 0, a->n); @@ -3665,7 +3567,7 @@ static bool trans_bv(DisasContext *ctx, arg_bv *a) =20 static bool trans_bve(DisasContext *ctx, arg_bve *a) { - TCGv_reg dest; + TCGv_i64 dest; =20 #ifdef CONFIG_USER_ONLY dest =3D do_ibranch_priv(ctx, load_gpr(ctx, a->b)); @@ -3988,12 +3890,12 @@ static bool trans_fcmp_d(DisasContext *ctx, arg_fcl= ass2 *a) =20 static bool trans_ftest(DisasContext *ctx, arg_ftest *a) { - TCGv_reg t; + TCGv_i64 t; =20 nullify_over(ctx); =20 t =3D tcg_temp_new(); - tcg_gen_ld32u_reg(t, tcg_env, offsetof(CPUHPPAState, fr0_shadow)); + tcg_gen_ld32u_i64(t, tcg_env, offsetof(CPUHPPAState, fr0_shadow)); =20 if (a->y =3D=3D 1) { int mask; @@ -4001,7 +3903,7 @@ static bool trans_ftest(DisasContext *ctx, arg_ftest = *a) =20 switch (a->c) { case 0: /* simple */ - tcg_gen_andi_reg(t, t, 0x4000000); + tcg_gen_andi_i64(t, t, 0x4000000); ctx->null_cond =3D cond_make_0(TCG_COND_NE, t); goto done; case 2: /* rej */ @@ -4030,17 +3932,17 @@ static bool trans_ftest(DisasContext *ctx, arg_ftes= t *a) return true; } if (inv) { - TCGv_reg c =3D tcg_constant_reg(mask); - tcg_gen_or_reg(t, t, c); + TCGv_i64 c =3D tcg_constant_i64(mask); + tcg_gen_or_i64(t, t, c); ctx->null_cond =3D cond_make(TCG_COND_EQ, t, c); } else { - tcg_gen_andi_reg(t, t, mask); + tcg_gen_andi_i64(t, t, mask); ctx->null_cond =3D cond_make_0(TCG_COND_EQ, t); } } else { unsigned cbit =3D (a->y ^ 1) - 1; =20 - tcg_gen_extract_reg(t, t, 21 - cbit, 1); + tcg_gen_extract_i64(t, t, 21 - cbit, 1); ctx->null_cond =3D cond_make_0(TCG_COND_NE, t); } =20 @@ -4295,7 +4197,7 @@ static void hppa_tr_translate_insn(DisasContextBase *= dcbase, CPUState *cs) if (ctx->iaoq_b =3D=3D -1) { ctx->iaoq_n =3D -1; ctx->iaoq_n_var =3D tcg_temp_new(); - tcg_gen_addi_reg(ctx->iaoq_n_var, cpu_iaoq_b, 4); + tcg_gen_addi_i64(ctx->iaoq_n_var, cpu_iaoq_b, 4); } else { ctx->iaoq_n =3D ctx->iaoq_b + 4; ctx->iaoq_n_var =3D NULL; @@ -4341,7 +4243,7 @@ static void hppa_tr_translate_insn(DisasContextBase *= dcbase, CPUState *cs) case DISAS_IAQ_N_STALE: case DISAS_IAQ_N_STALE_EXIT: if (ctx->iaoq_f =3D=3D -1) { - tcg_gen_mov_reg(cpu_iaoq_f, cpu_iaoq_b); + tcg_gen_mov_i64(cpu_iaoq_f, cpu_iaoq_b); copy_iaoq_entry(cpu_iaoq_b, ctx->iaoq_n, ctx->iaoq_n_var); #ifndef CONFIG_USER_ONLY tcg_gen_mov_i64(cpu_iasq_f, cpu_iasq_b); @@ -4351,7 +4253,7 @@ static void hppa_tr_translate_insn(DisasContextBase *= dcbase, CPUState *cs) ? DISAS_EXIT : DISAS_IAQ_N_UPDATED); } else if (ctx->iaoq_b =3D=3D -1) { - tcg_gen_mov_reg(cpu_iaoq_b, ctx->iaoq_n_var); + tcg_gen_mov_i64(cpu_iaoq_b, ctx->iaoq_n_var); } break; =20 --=20 2.34.1 From nobody Wed Nov 27 18:51:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1697666317; cv=none; d=zohomail.com; s=zohoarc; b=RhwJQm2mTMkbCQCA4DBseT/enOStt7rnIW4DoUmzl4VTxm2Tv53kJ9UQre1B+CY+E1hYnvfUJqy/RPAuhq1YM96S4BVV2XiB5QTp2MmH1s2N5XeemPN8y6K3whz7ctW17Nm1aMek8ENbq9l7bYYSPagBsz251D3GcVnfML07rDQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1697666317; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=4yNNnMvCvmrDYJiKz9Ub7lGJTKCUT9fcUBHvGYsxWNA=; b=EqKpGyzKmAQG+6Lu9V+F9Kr4DXiIrvRWaoPrnExItQtk92LnzMB9AzK7cPBvXRoJvijbW8XpcdGykF4UHsran7GRODqcfahAJdI4C+AeH+4Cvc8CL4AjTqJSVahsWjqDM2l/NfUG5Tv+Cqb8BFSOzy8tT8AwbnoiwupreIOlwhI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1697666317290736.0442884527043; Wed, 18 Oct 2023 14:58:37 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qtEVf-0002Cs-OC; Wed, 18 Oct 2023 17:55:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qtEVd-00029l-IK for qemu-devel@nongnu.org; Wed, 18 Oct 2023 17:55:21 -0400 Received: from mail-pf1-x433.google.com ([2607:f8b0:4864:20::433]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qtEVb-00051x-Ol for qemu-devel@nongnu.org; Wed, 18 Oct 2023 17:55:21 -0400 Received: by mail-pf1-x433.google.com with SMTP id d2e1a72fcca58-6b201a93c9cso4938736b3a.0 for ; Wed, 18 Oct 2023 14:55:19 -0700 (PDT) Received: from stoup.. ([71.212.149.95]) by smtp.gmail.com with ESMTPSA id r15-20020aa7962f000000b006889348ba6esm3796263pfg.127.2023.10.18.14.55.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Oct 2023 14:55:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1697666118; x=1698270918; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=4yNNnMvCvmrDYJiKz9Ub7lGJTKCUT9fcUBHvGYsxWNA=; b=lGpLBR8Fgat67nmlpmzUHguqxuXGUWFZMRZKTTjAkRVwMz/mdOE2j8pOpZ3V8ENgS7 h9hddAN8gbzTWrTbopgdVuFA6BWggBqzc9kEN0R/3s+f6id2/9Beuqd5Y85iMOYUCN1k AjgP2HgoI8wTh8t+uiipcW2W75/s9Gkf549sNHRf81es/+o7hBdCwfgfsbugq/5rzBr8 cK/7JvTD/+Qh4scK2Y5gkm6mCH4rG7v0YapMlvEjdV3NhqCJCIUimeLo59Po+5+bXdxI tYys+w7GpcdmyZ/qAasIde/tvMnJm5GlDQW9A0Dvvay12yJ6o7tWWqqPRMtBcTjnSLKI 6fDw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697666118; x=1698270918; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=4yNNnMvCvmrDYJiKz9Ub7lGJTKCUT9fcUBHvGYsxWNA=; b=l+uTQWcuYqHVjz6mJMaBg24s4KvR6cxC57vAeV1LA9P5MVY9Qbrs38NQ6l2mSnSV0B v8KtWseEIQ5Zbi4AyMPg2HVwlwddq2i4f5fLYxgLqNBHj2W5L62JHUbAJ9ji0YfwJ75Q dEzuR+52w1fBs02HxlNH/OTpWzNHRmDI4Np5oVes+OMbVRyrggSKxD9KAtMyerRLJXM3 aHuEQTH0amw+U50AJNtmscDhTQA5iItTHpoM7cObHkEy2cexZ2EEn9w5AZwfI0LzxgQK bvfZndA+/KQQ/aX/Fu60Sq/IWS8bWV5bHJmesjlKdJDDOBqUbEUIBrEp+4lpMPv18N7R LREQ== X-Gm-Message-State: AOJu0YwDlsnILR0OH2d/FWPc2HjKcSr/XcteVjJsVd1MHKHc3NTgRGLP bHFZ7vwuwwcu3TVRwwLE5t6j+Kq69oUcZAvG7yA= X-Google-Smtp-Source: AGHT+IHeBuFkR1n/Tz0hCu2wWZ/I9nicB4CbgAL7GpcV+BOToMpKGKLCbs7/KIRB7oLB/IPBW8WQMQ== X-Received: by 2002:a62:f245:0:b0:6b7:e577:3f7b with SMTP id y5-20020a62f245000000b006b7e5773f7bmr274404pfl.21.1697666118465; Wed, 18 Oct 2023 14:55:18 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH 48/61] target/hppa: Remove remaining TARGET_REGISTER_BITS redirections Date: Wed, 18 Oct 2023 14:51:22 -0700 Message-Id: <20231018215135.1561375-49-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231018215135.1561375-1-richard.henderson@linaro.org> References: <20231018215135.1561375-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::433; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697666322265100001 Content-Type: text/plain; charset="utf-8" The conversions to/from i64 can be eliminated entirely, folding computation into adjacent operations. Signed-off-by: Richard Henderson --- target/hppa/translate.c | 46 ++++++++++++----------------------------- 1 file changed, 13 insertions(+), 33 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 682cb518d6..c782c57149 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -33,15 +33,6 @@ #undef HELPER_H =20 =20 -/* Since we have a distinction between register size and address size, - we need to redefine all of these. */ - -#define tcg_gen_extu_reg_tl tcg_gen_mov_i64 -#define tcg_gen_trunc_i64_reg tcg_gen_mov_i64 -#define tcg_gen_extu_reg_i64 tcg_gen_mov_i64 -#define tcg_gen_ext_reg_i64 tcg_gen_mov_i64 - - typedef struct DisasCond { TCGCond c; TCGv_i64 a0, a1; @@ -1332,8 +1323,7 @@ static void form_gva(DisasContext *ctx, TCGv_i64 *pgv= a, TCGv_i64 *pofs, =20 *pofs =3D ofs; *pgva =3D addr =3D tcg_temp_new_i64(); - tcg_gen_extu_reg_tl(addr, modify <=3D 0 ? ofs : base); - tcg_gen_andi_tl(addr, addr, gva_offset_mask(ctx)); + tcg_gen_andi_tl(addr, modify <=3D 0 ? ofs : base, gva_offset_mask(ctx)= ); #ifndef CONFIG_USER_ONLY if (!is_phys) { tcg_gen_or_tl(addr, addr, space_select(ctx, sp, base)); @@ -1945,13 +1935,11 @@ static bool trans_mfsp(DisasContext *ctx, arg_mfsp = *a) unsigned rt =3D a->t; unsigned rs =3D a->sp; TCGv_i64 t0 =3D tcg_temp_new_i64(); - TCGv_i64 t1 =3D tcg_temp_new(); =20 load_spr(ctx, t0, rs); tcg_gen_shri_i64(t0, t0, 32); - tcg_gen_trunc_i64_reg(t1, t0); =20 - save_gpr(ctx, rt, t1); + save_gpr(ctx, rt, t0); =20 cond_free(&ctx->null_cond); return true; @@ -2008,22 +1996,21 @@ static bool trans_mtsp(DisasContext *ctx, arg_mtsp = *a) { unsigned rr =3D a->r; unsigned rs =3D a->sp; - TCGv_i64 t64; + TCGv_i64 tmp; =20 if (rs >=3D 5) { CHECK_MOST_PRIVILEGED(EXCP_PRIV_REG); } nullify_over(ctx); =20 - t64 =3D tcg_temp_new_i64(); - tcg_gen_extu_reg_i64(t64, load_gpr(ctx, rr)); - tcg_gen_shli_i64(t64, t64, 32); + tmp =3D tcg_temp_new_i64(); + tcg_gen_shli_i64(tmp, load_gpr(ctx, rr), 32); =20 if (rs >=3D 4) { - tcg_gen_st_i64(t64, tcg_env, offsetof(CPUHPPAState, sr[rs])); + tcg_gen_st_i64(tmp, tcg_env, offsetof(CPUHPPAState, sr[rs])); ctx->tb_flags &=3D ~TB_FLAG_SR_SAME; } else { - tcg_gen_mov_i64(cpu_sr[rs], t64); + tcg_gen_mov_i64(cpu_sr[rs], tmp); } =20 return nullify_end(ctx); @@ -2114,11 +2101,8 @@ static bool trans_ldsid(DisasContext *ctx, arg_ldsid= *a) /* We don't implement space registers in user mode. */ tcg_gen_movi_i64(dest, 0); #else - TCGv_i64 t0 =3D tcg_temp_new_i64(); - - tcg_gen_mov_i64(t0, space_select(ctx, a->sp, load_gpr(ctx, a->b))); - tcg_gen_shri_i64(t0, t0, 32); - tcg_gen_trunc_i64_reg(dest, t0); + tcg_gen_mov_i64(dest, space_select(ctx, a->sp, load_gpr(ctx, a->b))); + tcg_gen_shri_i64(dest, dest, 32); #endif save_gpr(ctx, a->t, dest); =20 @@ -3152,10 +3136,8 @@ static bool trans_shrp_sar(DisasContext *ctx, arg_sh= rp_sar *a) TCGv_i64 s =3D tcg_temp_new_i64(); =20 tcg_gen_concat32_i64(t, load_gpr(ctx, a->r2), load_gpr(ctx, a->r1)= ); - tcg_gen_extu_reg_i64(s, cpu_sar); - tcg_gen_andi_i64(s, s, 31); - tcg_gen_shr_i64(t, t, s); - tcg_gen_trunc_i64_reg(dest, t); + tcg_gen_andi_i64(s, cpu_sar, 31); + tcg_gen_shr_i64(dest, t, s); } save_gpr(ctx, a->t, dest); =20 @@ -3196,10 +3178,8 @@ static bool trans_shrp_imm(DisasContext *ctx, arg_sh= rp_imm *a) tcg_gen_rotri_i32(t32, t32, sa); tcg_gen_extu_i32_i64(dest, t32); } else { - TCGv_i64 t64 =3D tcg_temp_new_i64(); - tcg_gen_concat32_i64(t64, t2, cpu_gr[a->r1]); - tcg_gen_shri_i64(t64, t64, sa); - tcg_gen_trunc_i64_reg(dest, t64); + tcg_gen_concat32_i64(dest, t2, cpu_gr[a->r1]); + tcg_gen_extract_i64(dest, dest, sa, 32); } } save_gpr(ctx, a->t, dest); --=20 2.34.1 From nobody Wed Nov 27 18:51:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1697666521; cv=none; d=zohomail.com; s=zohoarc; b=PxfWYlaaRzETtfMxIiOk/KqU8n3ListOTxUvCyWjW3IenuMB5L7DB7vwKbogvhSqn6x1BvaHngwE0lcY7WTFWRxyV5eMIufuyl2X8TX/r526ZODzuU1Xi2uO8Cps+8IElCTL4akMUhpfsjSqpmULrWmHSrlHJ5pKyn/dH68/kDc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1697666521; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=zD/OD2M8jB+vs5HcR8Jr1nPSGY+rtPwbTcZp5cLt+Kg=; b=fj1tGcDxhC4mAf5iYijCvrey8x5miG7xeku+iMoRblAsqInrz+0k2KrV7k7O1yDm5FF759V3sLeSYND+NlbjucmmeVyEZsPbVniKLyxSwDO/MKgZIEiqUvxjOsTZ8qDlf9jongUbMJOhxcv1py/JlpIia9edeth0km4r0Dhuxxo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1697666520988669.8876155622058; Wed, 18 Oct 2023 15:02:00 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qtEVi-0002Dt-3s; Wed, 18 Oct 2023 17:55:26 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qtEVf-0002Cr-KV for qemu-devel@nongnu.org; Wed, 18 Oct 2023 17:55:23 -0400 Received: from mail-oo1-xc33.google.com ([2607:f8b0:4864:20::c33]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qtEVc-00052h-Qb for qemu-devel@nongnu.org; Wed, 18 Oct 2023 17:55:23 -0400 Received: by mail-oo1-xc33.google.com with SMTP id 006d021491bc7-57babef76deso4061422eaf.0 for ; Wed, 18 Oct 2023 14:55:20 -0700 (PDT) Received: from stoup.. ([71.212.149.95]) by smtp.gmail.com with ESMTPSA id r15-20020aa7962f000000b006889348ba6esm3796263pfg.127.2023.10.18.14.55.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Oct 2023 14:55:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1697666119; x=1698270919; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=zD/OD2M8jB+vs5HcR8Jr1nPSGY+rtPwbTcZp5cLt+Kg=; b=nEWebg0VEq5GjJgWJqCD5ez1q/xIy6Aajjmfgac2ueLPgThjfWGNInF0Lm9uczo473 zs3VlmxQFnj3/WsAtyzpR8gKE0bhuPAMs/iE8VJwSLrrZ5B/aoWDmesh/7RGakQrElOg pTihqIL8wR7nj8aOOiDD5oWtbcdNoDHCjs4HAlZdu42aPoNJVZuBiONP19JfAQHKN2QX TJuLeqGv0zKeujhgG14rE6IpZG+DDWMlOSYPyiX6hf2E0z7ecGYBqF7iWJRHUJFS4mHD eeCsOFAMBI2xOjoVeKUoSRumg+wJqYhxiXkt3lb2FBMIY6Eo0CfzY5zI9MJ8zp/NIjvT Oe5g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697666119; x=1698270919; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::c33; envelope-from=richard.henderson@linaro.org; helo=mail-oo1-xc33.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697666522854100003 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/hppa/translate.c | 158 ++++++++++++++++++++-------------------- 1 file changed, 80 insertions(+), 78 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index c782c57149..4a2bfb7757 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -32,6 +32,8 @@ #include "exec/helper-info.c.inc" #undef HELPER_H =20 +/* Choose to use explicit sizes within this file. */ +#undef tcg_temp_new =20 typedef struct DisasCond { TCGCond c; @@ -269,15 +271,15 @@ static DisasCond cond_make_0_tmp(TCGCond c, TCGv_i64 = a0) =20 static DisasCond cond_make_0(TCGCond c, TCGv_i64 a0) { - TCGv_i64 tmp =3D tcg_temp_new(); + TCGv_i64 tmp =3D tcg_temp_new_i64(); tcg_gen_mov_i64(tmp, a0); return cond_make_0_tmp(c, tmp); } =20 static DisasCond cond_make(TCGCond c, TCGv_i64 a0, TCGv_i64 a1) { - TCGv_i64 t0 =3D tcg_temp_new(); - TCGv_i64 t1 =3D tcg_temp_new(); + TCGv_i64 t0 =3D tcg_temp_new_i64(); + TCGv_i64 t1 =3D tcg_temp_new_i64(); =20 tcg_gen_mov_i64(t0, a0); tcg_gen_mov_i64(t1, a1); @@ -302,7 +304,7 @@ static void cond_free(DisasCond *cond) static TCGv_i64 load_gpr(DisasContext *ctx, unsigned reg) { if (reg =3D=3D 0) { - TCGv_i64 t =3D tcg_temp_new(); + TCGv_i64 t =3D tcg_temp_new_i64(); tcg_gen_movi_i64(t, 0); return t; } else { @@ -313,7 +315,7 @@ static TCGv_i64 load_gpr(DisasContext *ctx, unsigned re= g) static TCGv_i64 dest_gpr(DisasContext *ctx, unsigned reg) { if (reg =3D=3D 0 || ctx->null_cond.c !=3D TCG_COND_NEVER) { - return tcg_temp_new(); + return tcg_temp_new_i64(); } else { return cpu_gr[reg]; } @@ -437,7 +439,7 @@ static void nullify_over(DisasContext *ctx) =20 /* If we're using PSW[N], copy it to a temp because... */ if (ctx->null_cond.a0 =3D=3D cpu_psw_n) { - ctx->null_cond.a0 =3D tcg_temp_new(); + ctx->null_cond.a0 =3D tcg_temp_new_i64(); tcg_gen_mov_i64(ctx->null_cond.a0, cpu_psw_n); } /* ... we clear it before branching over the implementation, @@ -644,14 +646,14 @@ static DisasCond do_cond(DisasContext *ctx, unsigned = cf, bool d, break; case 1: /* =3D / <> (Z / !Z) */ if (cond_need_ext(ctx, d)) { - tmp =3D tcg_temp_new(); + tmp =3D tcg_temp_new_i64(); tcg_gen_ext32u_i64(tmp, res); res =3D tmp; } cond =3D cond_make_0(TCG_COND_EQ, res); break; case 2: /* < / >=3D (N ^ V / !(N ^ V) */ - tmp =3D tcg_temp_new(); + tmp =3D tcg_temp_new_i64(); tcg_gen_xor_i64(tmp, res, sv); if (cond_need_ext(ctx, d)) { tcg_gen_ext32s_i64(tmp, tmp); @@ -668,7 +670,7 @@ static DisasCond do_cond(DisasContext *ctx, unsigned cf= , bool d, * !(~(res ^ sv) >> 31) | !res * !(~(res ^ sv) >> 31 & res) */ - tmp =3D tcg_temp_new(); + tmp =3D tcg_temp_new_i64(); tcg_gen_eqv_i64(tmp, res, sv); if (cond_need_ext(ctx, d)) { tcg_gen_sextract_i64(tmp, tmp, 31, 1); @@ -685,7 +687,7 @@ static DisasCond do_cond(DisasContext *ctx, unsigned cf= , bool d, cond =3D cond_make_0(TCG_COND_EQ, cb_msb); break; case 5: /* ZNV / VNZ (!C | Z / C & !Z) */ - tmp =3D tcg_temp_new(); + tmp =3D tcg_temp_new_i64(); tcg_gen_neg_i64(tmp, cb_msb); tcg_gen_and_i64(tmp, tmp, res); if (cond_need_ext(ctx, d)) { @@ -695,14 +697,14 @@ static DisasCond do_cond(DisasContext *ctx, unsigned = cf, bool d, break; case 6: /* SV / NSV (V / !V) */ if (cond_need_ext(ctx, d)) { - tmp =3D tcg_temp_new(); + tmp =3D tcg_temp_new_i64(); tcg_gen_ext32s_i64(tmp, sv); sv =3D tmp; } cond =3D cond_make_0(TCG_COND_LT, sv); break; case 7: /* OD / EV */ - tmp =3D tcg_temp_new(); + tmp =3D tcg_temp_new_i64(); tcg_gen_andi_i64(tmp, res, 1); cond =3D cond_make_0_tmp(TCG_COND_NE, tmp); break; @@ -756,8 +758,8 @@ static DisasCond do_sub_cond(DisasContext *ctx, unsigne= d cf, bool d, tc =3D tcg_invert_cond(tc); } if (cond_need_ext(ctx, d)) { - TCGv_i64 t1 =3D tcg_temp_new(); - TCGv_i64 t2 =3D tcg_temp_new(); + TCGv_i64 t1 =3D tcg_temp_new_i64(); + TCGv_i64 t2 =3D tcg_temp_new_i64(); =20 if (ext_uns) { tcg_gen_ext32u_i64(t1, in1); @@ -833,7 +835,7 @@ static DisasCond do_log_cond(DisasContext *ctx, unsigne= d cf, bool d, } =20 if (cond_need_ext(ctx, d)) { - TCGv_i64 tmp =3D tcg_temp_new(); + TCGv_i64 tmp =3D tcg_temp_new_i64(); =20 if (ext_uns) { tcg_gen_ext32u_i64(tmp, res); @@ -878,8 +880,8 @@ static DisasCond do_unit_cond(unsigned cf, bool d, TCGv= _i64 res, * do our normal thing and compute carry-in of bit B+1 since that * leaves us with carry bits spread across two words. */ - cb =3D tcg_temp_new(); - tmp =3D tcg_temp_new(); + cb =3D tcg_temp_new_i64(); + tmp =3D tcg_temp_new_i64(); tcg_gen_or_i64(cb, in1, in2); tcg_gen_and_i64(tmp, in1, in2); tcg_gen_andc_i64(cb, cb, res); @@ -897,7 +899,7 @@ static DisasCond do_unit_cond(unsigned cf, bool d, TCGv= _i64 res, /* See hasless(v,1) from * https://graphics.stanford.edu/~seander/bithacks.html#ZeroInWord */ - tmp =3D tcg_temp_new(); + tmp =3D tcg_temp_new_i64(); tcg_gen_subi_i64(tmp, res, d_repl * 0x01010101u); tcg_gen_andc_i64(tmp, tmp, res); tcg_gen_andi_i64(tmp, tmp, d_repl * 0x80808080u); @@ -905,7 +907,7 @@ static DisasCond do_unit_cond(unsigned cf, bool d, TCGv= _i64 res, break; =20 case 3: /* SHZ / NHZ */ - tmp =3D tcg_temp_new(); + tmp =3D tcg_temp_new_i64(); tcg_gen_subi_i64(tmp, res, d_repl * 0x00010001u); tcg_gen_andc_i64(tmp, tmp, res); tcg_gen_andi_i64(tmp, tmp, d_repl * 0x80008000u); @@ -941,7 +943,7 @@ static TCGv_i64 get_carry(DisasContext *ctx, bool d, TCGv_i64 cb, TCGv_i64 cb_msb) { if (cond_need_ext(ctx, d)) { - TCGv_i64 t =3D tcg_temp_new(); + TCGv_i64 t =3D tcg_temp_new_i64(); tcg_gen_extract_i64(t, cb, 32, 1); return t; } @@ -957,8 +959,8 @@ static TCGv_i64 get_psw_carry(DisasContext *ctx, bool d) static TCGv_i64 do_add_sv(DisasContext *ctx, TCGv_i64 res, TCGv_i64 in1, TCGv_i64 in2) { - TCGv_i64 sv =3D tcg_temp_new(); - TCGv_i64 tmp =3D tcg_temp_new(); + TCGv_i64 sv =3D tcg_temp_new_i64(); + TCGv_i64 tmp =3D tcg_temp_new_i64(); =20 tcg_gen_xor_i64(sv, res, in1); tcg_gen_xor_i64(tmp, in1, in2); @@ -971,8 +973,8 @@ static TCGv_i64 do_add_sv(DisasContext *ctx, TCGv_i64 r= es, static TCGv_i64 do_sub_sv(DisasContext *ctx, TCGv_i64 res, TCGv_i64 in1, TCGv_i64 in2) { - TCGv_i64 sv =3D tcg_temp_new(); - TCGv_i64 tmp =3D tcg_temp_new(); + TCGv_i64 sv =3D tcg_temp_new_i64(); + TCGv_i64 tmp =3D tcg_temp_new_i64(); =20 tcg_gen_xor_i64(sv, res, in1); tcg_gen_xor_i64(tmp, in1, in2); @@ -989,21 +991,21 @@ static void do_add(DisasContext *ctx, unsigned rt, TC= Gv_i64 in1, unsigned c =3D cf >> 1; DisasCond cond; =20 - dest =3D tcg_temp_new(); + dest =3D tcg_temp_new_i64(); cb =3D NULL; cb_msb =3D NULL; cb_cond =3D NULL; =20 if (shift) { - tmp =3D tcg_temp_new(); + tmp =3D tcg_temp_new_i64(); tcg_gen_shli_i64(tmp, in1, shift); in1 =3D tmp; } =20 if (!is_l || cond_need_cb(c)) { TCGv_i64 zero =3D tcg_constant_i64(0); - cb_msb =3D tcg_temp_new(); - cb =3D tcg_temp_new(); + cb_msb =3D tcg_temp_new_i64(); + cb =3D tcg_temp_new_i64(); =20 tcg_gen_add2_i64(dest, cb_msb, in1, zero, in2, zero); if (is_c) { @@ -1035,7 +1037,7 @@ static void do_add(DisasContext *ctx, unsigned rt, TC= Gv_i64 in1, /* Emit any conditional trap before any writeback. */ cond =3D do_cond(ctx, cf, d, dest, cb_cond, sv); if (is_tc) { - tmp =3D tcg_temp_new(); + tmp =3D tcg_temp_new_i64(); tcg_gen_setcond_i64(cond.c, tmp, cond.a0, cond.a1); gen_helper_tcond(tcg_env, tmp); } @@ -1090,9 +1092,9 @@ static void do_sub(DisasContext *ctx, unsigned rt, TC= Gv_i64 in1, unsigned c =3D cf >> 1; DisasCond cond; =20 - dest =3D tcg_temp_new(); - cb =3D tcg_temp_new(); - cb_msb =3D tcg_temp_new(); + dest =3D tcg_temp_new_i64(); + cb =3D tcg_temp_new_i64(); + cb_msb =3D tcg_temp_new_i64(); =20 zero =3D tcg_constant_i64(0); if (is_b) { @@ -1131,7 +1133,7 @@ static void do_sub(DisasContext *ctx, unsigned rt, TC= Gv_i64 in1, =20 /* Emit any conditional trap before any writeback. */ if (is_tc) { - tmp =3D tcg_temp_new(); + tmp =3D tcg_temp_new_i64(); tcg_gen_setcond_i64(cond.c, tmp, cond.a0, cond.a1); gen_helper_tcond(tcg_env, tmp); } @@ -1180,7 +1182,7 @@ static void do_cmpclr(DisasContext *ctx, unsigned rt,= TCGv_i64 in1, TCGv_i64 dest, sv; DisasCond cond; =20 - dest =3D tcg_temp_new(); + dest =3D tcg_temp_new_i64(); tcg_gen_sub_i64(dest, in1, in2); =20 /* Compute signed overflow if required. */ @@ -1245,13 +1247,13 @@ static void do_unit(DisasContext *ctx, unsigned rt,= TCGv_i64 in1, save_gpr(ctx, rt, dest); cond_free(&ctx->null_cond); } else { - dest =3D tcg_temp_new(); + dest =3D tcg_temp_new_i64(); fn(dest, in1, in2); =20 cond =3D do_unit_cond(cf, d, dest, in1, in2); =20 if (is_tc) { - TCGv_i64 tmp =3D tcg_temp_new(); + TCGv_i64 tmp =3D tcg_temp_new_i64(); tcg_gen_setcond_i64(cond.c, tmp, cond.a0, cond.a1); gen_helper_tcond(tcg_env, tmp); } @@ -1286,7 +1288,7 @@ static TCGv_i64 space_select(DisasContext *ctx, int s= p, TCGv_i64 base) } =20 ptr =3D tcg_temp_new_ptr(); - tmp =3D tcg_temp_new(); + tmp =3D tcg_temp_new_i64(); spc =3D tcg_temp_new_i64(); =20 /* Extract top 2 bits of the address, shift left 3 for uint64_t index.= */ @@ -1311,11 +1313,11 @@ static void form_gva(DisasContext *ctx, TCGv_i64 *p= gva, TCGv_i64 *pofs, =20 /* Note that RX is mutually exclusive with DISP. */ if (rx) { - ofs =3D tcg_temp_new(); + ofs =3D tcg_temp_new_i64(); tcg_gen_shli_i64(ofs, cpu_gr[rx], scale); tcg_gen_add_i64(ofs, ofs, base); } else if (disp || modify) { - ofs =3D tcg_temp_new(); + ofs =3D tcg_temp_new_i64(); tcg_gen_addi_i64(ofs, base, disp); } else { ofs =3D base; @@ -1421,7 +1423,7 @@ static bool do_load(DisasContext *ctx, unsigned rt, u= nsigned rb, dest =3D dest_gpr(ctx, rt); } else { /* Make sure if RT =3D=3D RB, we see the result of the load. */ - dest =3D tcg_temp_new(); + dest =3D tcg_temp_new_i64(); } do_load_64(ctx, dest, rb, rx, scale, disp, sp, modify, mop); save_gpr(ctx, rt, dest); @@ -1737,7 +1739,7 @@ static bool do_ibranch(DisasContext *ctx, TCGv_i64 de= st, if (link !=3D 0) { copy_iaoq_entry(cpu_gr[link], ctx->iaoq_n, ctx->iaoq_n_var); } - next =3D tcg_temp_new(); + next =3D tcg_temp_new_i64(); tcg_gen_mov_i64(next, dest); if (is_n) { if (use_nullify_skip(ctx)) { @@ -1778,8 +1780,8 @@ static bool do_ibranch(DisasContext *ctx, TCGv_i64 de= st, a0 =3D ctx->null_cond.a0; a1 =3D ctx->null_cond.a1; =20 - tmp =3D tcg_temp_new(); - next =3D tcg_temp_new(); + tmp =3D tcg_temp_new_i64(); + next =3D tcg_temp_new_i64(); =20 copy_iaoq_entry(tmp, ctx->iaoq_n, ctx->iaoq_n_var); tcg_gen_movcond_i64(c, next, a0, a1, tmp, dest); @@ -1821,11 +1823,11 @@ static TCGv_i64 do_ibranch_priv(DisasContext *ctx, = TCGv_i64 offset) return offset; case 3: /* Privilege 3 is minimum and is never allowed to increase. */ - dest =3D tcg_temp_new(); + dest =3D tcg_temp_new_i64(); tcg_gen_ori_i64(dest, offset, 3); break; default: - dest =3D tcg_temp_new(); + dest =3D tcg_temp_new_i64(); tcg_gen_andi_i64(dest, offset, -4); tcg_gen_ori_i64(dest, dest, ctx->privilege); tcg_gen_movcond_i64(TCG_COND_GTU, dest, dest, offset, dest, offset= ); @@ -1983,7 +1985,7 @@ static bool trans_mfctl(DisasContext *ctx, arg_mfctl = *a) break; } =20 - tmp =3D tcg_temp_new(); + tmp =3D tcg_temp_new_i64(); tcg_gen_ld_i64(tmp, tcg_env, offsetof(CPUHPPAState, cr[ctl])); save_gpr(ctx, rt, tmp); =20 @@ -2024,7 +2026,7 @@ static bool trans_mtctl(DisasContext *ctx, arg_mtctl = *a) =20 if (ctl =3D=3D CR_SAR) { reg =3D load_gpr(ctx, a->r); - tmp =3D tcg_temp_new(); + tmp =3D tcg_temp_new_i64(); tcg_gen_andi_i64(tmp, reg, ctx->is_pa20 ? 63 : 31); save_or_nullify(ctx, cpu_sar, tmp); =20 @@ -2055,7 +2057,7 @@ static bool trans_mtctl(DisasContext *ctx, arg_mtctl = *a) case CR_IIAOQ: /* FIXME: Respect PSW_Q bit */ /* The write advances the queue and stores to the back element. */ - tmp =3D tcg_temp_new(); + tmp =3D tcg_temp_new_i64(); tcg_gen_ld_i64(tmp, tcg_env, offsetof(CPUHPPAState, cr_back[ctl - CR_IIASQ])); tcg_gen_st_i64(tmp, tcg_env, offsetof(CPUHPPAState, cr[ctl])); @@ -2083,7 +2085,7 @@ static bool trans_mtctl(DisasContext *ctx, arg_mtctl = *a) =20 static bool trans_mtsarcm(DisasContext *ctx, arg_mtsarcm *a) { - TCGv_i64 tmp =3D tcg_temp_new(); + TCGv_i64 tmp =3D tcg_temp_new_i64(); =20 tcg_gen_not_i64(tmp, load_gpr(ctx, a->r)); tcg_gen_andi_i64(tmp, tmp, ctx->is_pa20 ? 63 : 31); @@ -2118,7 +2120,7 @@ static bool trans_rsm(DisasContext *ctx, arg_rsm *a) =20 nullify_over(ctx); =20 - tmp =3D tcg_temp_new(); + tmp =3D tcg_temp_new_i64(); tcg_gen_ld_i64(tmp, tcg_env, offsetof(CPUHPPAState, psw)); tcg_gen_andi_i64(tmp, tmp, ~a->i); gen_helper_swap_system_mask(tmp, tcg_env, tmp); @@ -2138,7 +2140,7 @@ static bool trans_ssm(DisasContext *ctx, arg_ssm *a) =20 nullify_over(ctx); =20 - tmp =3D tcg_temp_new(); + tmp =3D tcg_temp_new_i64(); tcg_gen_ld_i64(tmp, tcg_env, offsetof(CPUHPPAState, psw)); tcg_gen_ori_i64(tmp, tmp, a->i); gen_helper_swap_system_mask(tmp, tcg_env, tmp); @@ -2158,7 +2160,7 @@ static bool trans_mtsm(DisasContext *ctx, arg_mtsm *a) nullify_over(ctx); =20 reg =3D load_gpr(ctx, a->r); - tmp =3D tcg_temp_new(); + tmp =3D tcg_temp_new_i64(); gen_helper_swap_system_mask(tmp, tcg_env, reg); =20 /* Exit the TB to recognize new interrupts. */ @@ -2406,7 +2408,7 @@ static bool trans_lpa(DisasContext *ctx, arg_ldst *a) =20 form_gva(ctx, &vaddr, &ofs, a->b, a->x, 0, 0, a->sp, a->m, false); =20 - paddr =3D tcg_temp_new(); + paddr =3D tcg_temp_new_i64(); gen_helper_lpa(paddr, tcg_env, vaddr); =20 /* Note that physical address result overrides base modification. */ @@ -2590,7 +2592,7 @@ static bool do_uaddcm(DisasContext *ctx, arg_rrr_cf_d= *a, bool is_tc) } tcg_r1 =3D load_gpr(ctx, a->r1); tcg_r2 =3D load_gpr(ctx, a->r2); - tmp =3D tcg_temp_new(); + tmp =3D tcg_temp_new_i64(); tcg_gen_not_i64(tmp, tcg_r2); do_unit(ctx, a->t, tcg_r1, tmp, a->cf, a->d, is_tc, tcg_gen_add_i64); return nullify_end(ctx); @@ -2612,7 +2614,7 @@ static bool do_dcor(DisasContext *ctx, arg_rr_cf_d *a= , bool is_i) =20 nullify_over(ctx); =20 - tmp =3D tcg_temp_new(); + tmp =3D tcg_temp_new_i64(); tcg_gen_shri_i64(tmp, cpu_psw_cb, 3); if (!is_i) { tcg_gen_not_i64(tmp, tmp); @@ -2644,10 +2646,10 @@ static bool trans_ds(DisasContext *ctx, arg_rrr_cf = *a) in1 =3D load_gpr(ctx, a->r1); in2 =3D load_gpr(ctx, a->r2); =20 - add1 =3D tcg_temp_new(); - add2 =3D tcg_temp_new(); - addc =3D tcg_temp_new(); - dest =3D tcg_temp_new(); + add1 =3D tcg_temp_new_i64(); + add2 =3D tcg_temp_new_i64(); + addc =3D tcg_temp_new_i64(); + dest =3D tcg_temp_new_i64(); zero =3D tcg_constant_i64(0); =20 /* Form R1 << 1 | PSW[CB]{8}. */ @@ -2770,7 +2772,7 @@ static bool trans_ldc(DisasContext *ctx, arg_ldst *a) if (a->m) { /* Base register modification. Make sure if RT =3D=3D RB, we see the result of the load. */ - dest =3D tcg_temp_new(); + dest =3D tcg_temp_new_i64(); } else { dest =3D dest_gpr(ctx, a->t); } @@ -2927,7 +2929,7 @@ static bool do_cmpb(DisasContext *ctx, unsigned r, TC= Gv_i64 in1, DisasCond cond; =20 in2 =3D load_gpr(ctx, r); - dest =3D tcg_temp_new(); + dest =3D tcg_temp_new_i64(); =20 tcg_gen_sub_i64(dest, in1, in2); =20 @@ -2979,13 +2981,13 @@ static bool do_addb(DisasContext *ctx, unsigned r, = TCGv_i64 in1, } =20 in2 =3D load_gpr(ctx, r); - dest =3D tcg_temp_new(); + dest =3D tcg_temp_new_i64(); sv =3D NULL; cb_cond =3D NULL; =20 if (cond_need_cb(c)) { - TCGv_i64 cb =3D tcg_temp_new(); - TCGv_i64 cb_msb =3D tcg_temp_new(); + TCGv_i64 cb =3D tcg_temp_new_i64(); + TCGv_i64 cb_msb =3D tcg_temp_new_i64(); =20 tcg_gen_movi_i64(cb_msb, 0); tcg_gen_add2_i64(dest, cb_msb, in1, cb_msb, in2, cb_msb); @@ -3023,7 +3025,7 @@ static bool trans_bb_sar(DisasContext *ctx, arg_bb_sa= r *a) =20 nullify_over(ctx); =20 - tmp =3D tcg_temp_new(); + tmp =3D tcg_temp_new_i64(); tcg_r =3D load_gpr(ctx, a->r); if (cond_need_ext(ctx, a->d)) { /* Force shift into [32,63] */ @@ -3045,7 +3047,7 @@ static bool trans_bb_imm(DisasContext *ctx, arg_bb_im= m *a) =20 nullify_over(ctx); =20 - tmp =3D tcg_temp_new(); + tmp =3D tcg_temp_new_i64(); tcg_r =3D load_gpr(ctx, a->r); p =3D a->p | (cond_need_ext(ctx, a->d) ? 32 : 0); tcg_gen_shli_i64(tmp, tcg_r, p); @@ -3105,7 +3107,7 @@ static bool trans_shrp_sar(DisasContext *ctx, arg_shr= p_sar *a) tcg_gen_shr_i64(dest, dest, cpu_sar); } else { tcg_gen_ext32u_i64(dest, load_gpr(ctx, a->r2)); - tmp =3D tcg_temp_new(); + tmp =3D tcg_temp_new_i64(); tcg_gen_andi_i64(tmp, cpu_sar, 31); tcg_gen_shr_i64(dest, dest, tmp); } @@ -3123,8 +3125,8 @@ static bool trans_shrp_sar(DisasContext *ctx, arg_shr= p_sar *a) tcg_gen_extu_i32_i64(dest, t32); } } else if (a->d) { - TCGv_i64 t =3D tcg_temp_new(); - TCGv_i64 n =3D tcg_temp_new(); + TCGv_i64 t =3D tcg_temp_new_i64(); + TCGv_i64 n =3D tcg_temp_new_i64(); =20 tcg_gen_xori_i64(n, cpu_sar, 63); tcg_gen_shl_i64(t, load_gpr(ctx, a->r2), n); @@ -3206,7 +3208,7 @@ static bool trans_extr_sar(DisasContext *ctx, arg_ext= r_sar *a) =20 dest =3D dest_gpr(ctx, a->t); src =3D load_gpr(ctx, a->r); - tmp =3D tcg_temp_new(); + tmp =3D tcg_temp_new_i64(); =20 /* Recall that SAR is using big-endian bit numbering. */ tcg_gen_andi_i64(tmp, cpu_sar, widthm1); @@ -3350,14 +3352,14 @@ static bool do_dep_sar(DisasContext *ctx, unsigned = rt, unsigned c, uint64_t msb =3D 1ULL << (len - 1); =20 dest =3D dest_gpr(ctx, rt); - shift =3D tcg_temp_new(); - tmp =3D tcg_temp_new(); + shift =3D tcg_temp_new_i64(); + tmp =3D tcg_temp_new_i64(); =20 /* Convert big-endian bit numbering in SAR to left-shift. */ tcg_gen_andi_i64(shift, cpu_sar, widthm1); tcg_gen_xori_i64(shift, shift, widthm1); =20 - mask =3D tcg_temp_new(); + mask =3D tcg_temp_new_i64(); tcg_gen_movi_i64(mask, msb + (msb - 1)); tcg_gen_and_i64(tmp, val, mask); if (rs) { @@ -3422,7 +3424,7 @@ static bool trans_be(DisasContext *ctx, arg_be *a) nullify_over(ctx); #endif =20 - tmp =3D tcg_temp_new(); + tmp =3D tcg_temp_new_i64(); tcg_gen_addi_i64(tmp, load_gpr(ctx, a->b), a->disp); tmp =3D do_ibranch_priv(ctx, tmp); =20 @@ -3519,7 +3521,7 @@ static bool trans_b_gate(DisasContext *ctx, arg_b_gat= e *a) static bool trans_blr(DisasContext *ctx, arg_blr *a) { if (a->x) { - TCGv_i64 tmp =3D tcg_temp_new(); + TCGv_i64 tmp =3D tcg_temp_new_i64(); tcg_gen_shli_i64(tmp, load_gpr(ctx, a->x), 3); tcg_gen_addi_i64(tmp, tmp, ctx->iaoq_f + 8); /* The computation here never changes privilege level. */ @@ -3537,7 +3539,7 @@ static bool trans_bv(DisasContext *ctx, arg_bv *a) if (a->x =3D=3D 0) { dest =3D load_gpr(ctx, a->b); } else { - dest =3D tcg_temp_new(); + dest =3D tcg_temp_new_i64(); tcg_gen_shli_i64(dest, load_gpr(ctx, a->x), 3); tcg_gen_add_i64(dest, dest, load_gpr(ctx, a->b)); } @@ -3874,7 +3876,7 @@ static bool trans_ftest(DisasContext *ctx, arg_ftest = *a) =20 nullify_over(ctx); =20 - t =3D tcg_temp_new(); + t =3D tcg_temp_new_i64(); tcg_gen_ld32u_i64(t, tcg_env, offsetof(CPUHPPAState, fr0_shadow)); =20 if (a->y =3D=3D 1) { @@ -4176,7 +4178,7 @@ static void hppa_tr_translate_insn(DisasContextBase *= dcbase, CPUState *cs) This will be overwritten by a branch. */ if (ctx->iaoq_b =3D=3D -1) { ctx->iaoq_n =3D -1; - ctx->iaoq_n_var =3D tcg_temp_new(); + ctx->iaoq_n_var =3D tcg_temp_new_i64(); tcg_gen_addi_i64(ctx->iaoq_n_var, cpu_iaoq_b, 4); } else { ctx->iaoq_n =3D ctx->iaoq_b + 4; --=20 2.34.1 From nobody Wed Nov 27 18:51:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1697666511; cv=none; d=zohomail.com; s=zohoarc; b=OQxN4mk4kl3CTxoVNBnKqvws4JlRWLIZEGgeFIzdoZLmgOfVr1ES0YnnsRIj3PMQjK98FgIbKMPltlYrL3ESwulJ+109XwV8VzDdeJwI7V0jE10x2CkW8rnwpLyqGOMv6997X5tNlyIJ40wIOpobSiu27neHLBFLN36HL+8uziE= ARC-Message-Signature: i=1; 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id r15-20020aa7962f000000b006889348ba6esm3796263pfg.127.2023.10.18.14.55.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Oct 2023 14:55:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1697666120; x=1698270920; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=kK32N3vgLhgiOtEEROoXYbcFL4Ddcs6GJ1O6rcXX12s=; b=fQZ1dvXwbMAU8bVaEqQyqB5sNx2hblDRJpoc7fUfluVqSCjyFEannUQO4quXWb9LjS pxmxC7pLW7cd7GaqJxVA/oVE7rUMmNGMIN3paXALSeULkSQ7vELdyT+aBmQDqMZHMCI8 7TtRewvzGbbRteix8DPKVAVvJD4sX1wyzI00A+AowIoJLGTc0SVo5UEc8muho3/HKXcF OR4Nw4V7dA9/gef+zfXQoBPAMMDLCzg8NsA8RJgpj6kLsim6kz3xeZ37rslHry3vCngj NGiSYst8fyzvBflMepUpgPIBMUpp3/T8PKHFIstIOTnrI67ufSxNlfgQc0N7Cf8mPvGh SSsg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697666120; x=1698270920; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=kK32N3vgLhgiOtEEROoXYbcFL4Ddcs6GJ1O6rcXX12s=; b=VWAFiqe2MNl3AikMY/HaM2R3np31HakM65npVkCTAUi+rLGzVo5GA9hqJnO1T0iLzT Iehc7R4P46lcASxuhUIMKRaJngAkHsFv240gRlcbsoMw3GnJqivdXw8c+yNuZeQF+EMc U+DOnat6DWwZZAMGVTJAovqXhzLv19m49fj9eVQeFMe97AWko+MpdUqYXq8yvpIAY0T0 mKEcGBbGSy0BTw3Zd5lazmMtSEE5y1O0si+aFP809jhDo0Tur0Zn7iGQWEAD3p7zoyjP AYAk5h3TkmZmZ149TEzLIjP/tV4Q/P+NeQshmx9R+qYi4owxOvWJrzg8bCUYu/vMOuZn udpg== X-Gm-Message-State: AOJu0Yyfc8c/9D3lOn0QS8SF3AGDY9f9c1r50oYnRf8tZjFw/56JFd4N 1Bd1iD+v3AXCc1PQrnW01A9MdIodGiKlr1THo3Q= X-Google-Smtp-Source: AGHT+IFhbvI+52dPP4FnSypjKXed+LCDbJi1/eLA3cypu9xCIZjMVetEghzXf9J178Bw79Zrv+W8aA== X-Received: by 2002:a9d:63c1:0:b0:6b5:f457:adaa with SMTP id e1-20020a9d63c1000000b006b5f457adaamr545139otl.29.1697666120491; Wed, 18 Oct 2023 14:55:20 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH 50/61] target/hppa: Replace tcg_gen_*_tl with tcg_gen_*_i64 Date: Wed, 18 Oct 2023 14:51:24 -0700 Message-Id: <20231018215135.1561375-51-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231018215135.1561375-1-richard.henderson@linaro.org> References: <20231018215135.1561375-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::331; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697666512747100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/hppa/translate.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 4a2bfb7757..366a8f1acc 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -1325,10 +1325,10 @@ static void form_gva(DisasContext *ctx, TCGv_i64 *p= gva, TCGv_i64 *pofs, =20 *pofs =3D ofs; *pgva =3D addr =3D tcg_temp_new_i64(); - tcg_gen_andi_tl(addr, modify <=3D 0 ? ofs : base, gva_offset_mask(ctx)= ); + tcg_gen_andi_i64(addr, modify <=3D 0 ? ofs : base, gva_offset_mask(ctx= )); #ifndef CONFIG_USER_ONLY if (!is_phys) { - tcg_gen_or_tl(addr, addr, space_select(ctx, sp, base)); + tcg_gen_or_i64(addr, addr, space_select(ctx, sp, base)); } #endif } @@ -2361,7 +2361,7 @@ static bool trans_ixtlbxf(DisasContext *ctx, arg_ixtl= bxf *a) a->data ? offsetof(CPUHPPAState, cr[CR_IOR]) : offsetof(CPUHPPAState, cr[CR_IIAOQ])); tcg_gen_shli_i64(stl, stl, 32); - tcg_gen_or_tl(addr, atl, stl); + tcg_gen_or_i64(addr, atl, stl); =20 reg =3D load_gpr(ctx, a->r); if (a->addr) { @@ -2911,7 +2911,7 @@ static bool trans_ldo(DisasContext *ctx, arg_ldo *a) TCGv_i64 tcg_rt =3D dest_gpr(ctx, a->t); =20 /* Special case rb =3D=3D 0, for the LDI pseudo-op. - The COPY pseudo-op is handled for free within tcg_gen_addi_tl. */ + The COPY pseudo-op is handled for free within tcg_gen_addi_i64. */ if (a->b =3D=3D 0) { tcg_gen_movi_i64(tcg_rt, a->i); } else { --=20 2.34.1 From nobody Wed Nov 27 18:51:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1697666499; cv=none; d=zohomail.com; s=zohoarc; b=QWA2X2xWOvujQnivNqg1oWH/hmvEifKHR174QMBCE3ku/vWOzvZrFROwNPeFeRw8spM4fCxrWSU1E+iUauaJcWHIDk0Gi8yUaPrUrolwXm6Tp0smj/JbYqcA0fvwOGwy1TOjbre79PtMdRvLNROJqBz8dZszQmMQQKvrM2ZWc9w= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1697666499; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=DYe6qSFa58+9C+lzb+b7/7YPN7n3mkRlSU5qeFeX9fI=; b=aJk01T/6cOgNr6I+Au3jmb0gioTkOO5/hKaEucGus6+2GAMwhSlfRnSnEbhUezwywQy9dvuL+FDbPHenRv++nOMFfCuN44bG7nMv+AN1M72Nh+Oxzh/MQLJcaSksBcoDd7zppPNzEaU2ySuG7tJo95+tWZxXQjoVZKpATDMwF9w= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1697666499323710.6507695765171; Wed, 18 Oct 2023 15:01:39 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qtEVi-0002Dy-8C; Wed, 18 Oct 2023 17:55:26 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qtEVg-0002DI-DM for qemu-devel@nongnu.org; Wed, 18 Oct 2023 17:55:24 -0400 Received: from mail-pf1-x436.google.com ([2607:f8b0:4864:20::436]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qtEVe-00053y-K4 for qemu-devel@nongnu.org; Wed, 18 Oct 2023 17:55:24 -0400 Received: by mail-pf1-x436.google.com with SMTP id d2e1a72fcca58-6bd0e1b1890so3704073b3a.3 for ; Wed, 18 Oct 2023 14:55:22 -0700 (PDT) Received: from stoup.. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::436; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697666500719100003 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/hppa/helper.h | 3 +++ target/hppa/insns.decode | 8 +++++++- target/hppa/op_helper.c | 32 ++++++++++++++++++++++++++++++++ target/hppa/translate.c | 37 +++++++++++++++++++++++++++++++++++++ 4 files changed, 79 insertions(+), 1 deletion(-) diff --git a/target/hppa/helper.h b/target/hppa/helper.h index 4b2c66316f..ff2695797e 100644 --- a/target/hppa/helper.h +++ b/target/hppa/helper.h @@ -14,6 +14,9 @@ DEF_HELPER_FLAGS_3(stdby_e_parallel, TCG_CALL_NO_WG, void= , env, tl, tl) =20 DEF_HELPER_FLAGS_1(ldc_check, TCG_CALL_NO_RWG, void, tl) =20 +DEF_HELPER_FLAGS_2(hadd_ss, TCG_CALL_NO_RWG, i64, i64, i64) +DEF_HELPER_FLAGS_2(hadd_us, TCG_CALL_NO_RWG, i64, i64, i64) + DEF_HELPER_FLAGS_4(probe, TCG_CALL_NO_WG, tl, env, tl, i32, i32) =20 DEF_HELPER_FLAGS_1(loaded_fr0, TCG_CALL_NO_RWG, void, env) diff --git a/target/hppa/insns.decode b/target/hppa/insns.decode index db1b9f750f..88248ed3e2 100644 --- a/target/hppa/insns.decode +++ b/target/hppa/insns.decode @@ -65,6 +65,7 @@ &ldst t b x disp sp m scale size =20 &rr_cf_d t r cf d +&rrr t r1 r2 &rrr_cf t r1 r2 cf &rrr_cf_d t r1 r2 cf d &rrr_cf_d_sh t r1 r2 cf d sh @@ -81,6 +82,7 @@ #### =20 @rr_cf_d ...... r:5 ..... cf:4 ...... d:1 t:5 &rr_cf_d +@rrr ...... r2:5 r1:5 .... ....... t:5 &rrr @rrr_cf ...... r2:5 r1:5 cf:4 ....... t:5 &rrr_cf @rrr_cf_d ...... r2:5 r1:5 cf:4 ...... d:1 t:5 &rrr_cf_d @rrr_cf_d_sh ...... r2:5 r1:5 cf:4 .... sh:2 d:1 t:5 &rrr_cf_d_sh @@ -208,6 +210,10 @@ subi_tsv 100101 ..... ..... .... 1 ........... = @rri_cf =20 cmpiclr 100100 ..... ..... .... . ........... @rri_cf_d =20 +hadd 000010 ..... ..... 00000011 11 0 ..... @rrr +hadd_ss 000010 ..... ..... 00000011 01 0 ..... @rrr +hadd_us 000010 ..... ..... 00000011 00 0 ..... @rrr + #### # Index Mem #### @@ -429,7 +435,7 @@ fmpyfadd_d 101110 rm1:5 rm2:5 ... 0 1 ..0 0 0 neg:= 1 t:5 ra3=3D%rc32 =20 @f0e_f_3 ...... ..... ..... ... .0 110 ..0 ..... \ &fclass3 r1=3D%ra64 r2=3D%rb64 t=3D%rt64 -@f0e_d_3 ...... r1:5 r2:5 ... 01 110 000 t:5 +@f0e_d_3 ...... r1:5 r2:5 ... 01 110 000 t:5 &fclass3 =20 # Floating point class 0 =20 diff --git a/target/hppa/op_helper.c b/target/hppa/op_helper.c index 0bccca1e11..a230a3a0c3 100644 --- a/target/hppa/op_helper.c +++ b/target/hppa/op_helper.c @@ -377,3 +377,35 @@ target_ulong HELPER(read_interval_timer)(void) return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) >> 2; #endif } + +uint64_t HELPER(hadd_ss)(uint64_t r1, uint64_t r2) +{ + uint64_t ret =3D 0; + + for (int i =3D 0; i < 64; i +=3D 16) { + int f1 =3D sextract64(r1, i, 16); + int f2 =3D sextract64(r2, i, 16); + int fr =3D f1 + f2; + + fr =3D MIN(fr, INT16_MAX); + fr =3D MAX(fr, INT16_MIN); + ret =3D deposit64(ret, i, 16, fr); + } + return ret; +} + +uint64_t HELPER(hadd_us)(uint64_t r1, uint64_t r2) +{ + uint64_t ret =3D 0; + + for (int i =3D 0; i < 64; i +=3D 16) { + int f1 =3D extract64(r1, i, 16); + int f2 =3D sextract64(r2, i, 16); + int fr =3D f1 + f2; + + fr =3D MIN(fr, UINT16_MAX); + fr =3D MAX(fr, 0); + ret =3D deposit64(ret, i, 16, fr); + } + return ret; +} diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 366a8f1acc..bbf216fcde 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -23,6 +23,7 @@ #include "qemu/host-utils.h" #include "exec/exec-all.h" #include "tcg/tcg-op.h" +#include "tcg/tcg-op-gvec.h" #include "exec/helper-proto.h" #include "exec/helper-gen.h" #include "exec/translator.h" @@ -2739,6 +2740,42 @@ static bool trans_cmpiclr(DisasContext *ctx, arg_rri= _cf_d *a) return nullify_end(ctx); } =20 +static bool do_multimedia(DisasContext *ctx, arg_rrr *a, + void (*fn)(TCGv_i64, TCGv_i64, TCGv_i64)) +{ + TCGv_i64 r1, r2, dest; + + if (!ctx->is_pa20) { + return false; + } + + nullify_over(ctx); + + r1 =3D load_gpr(ctx, a->r1); + r2 =3D load_gpr(ctx, a->r2); + dest =3D dest_gpr(ctx, a->t); + + fn(dest, r1, r2); + save_gpr(ctx, a->t, dest); + + return nullify_end(ctx); +} + +static bool trans_hadd(DisasContext *ctx, arg_rrr *a) +{ + return do_multimedia(ctx, a, tcg_gen_vec_add16_i64); +} + +static bool trans_hadd_ss(DisasContext *ctx, arg_rrr *a) +{ + return do_multimedia(ctx, a, gen_helper_hadd_ss); +} + +static bool trans_hadd_us(DisasContext *ctx, arg_rrr *a) +{ + return do_multimedia(ctx, a, gen_helper_hadd_us); +} + static bool trans_ld(DisasContext *ctx, arg_ldst *a) { if (!ctx->is_pa20 && a->size > MO_32) { --=20 2.34.1 From nobody Wed Nov 27 18:51:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::32a; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697666338094100003 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/hppa/helper.h | 2 ++ target/hppa/insns.decode | 4 ++++ target/hppa/op_helper.c | 32 ++++++++++++++++++++++++++++++++ target/hppa/translate.c | 15 +++++++++++++++ 4 files changed, 53 insertions(+) diff --git a/target/hppa/helper.h b/target/hppa/helper.h index ff2695797e..99486f4cf8 100644 --- a/target/hppa/helper.h +++ b/target/hppa/helper.h @@ -16,6 +16,8 @@ DEF_HELPER_FLAGS_1(ldc_check, TCG_CALL_NO_RWG, void, tl) =20 DEF_HELPER_FLAGS_2(hadd_ss, TCG_CALL_NO_RWG, i64, i64, i64) DEF_HELPER_FLAGS_2(hadd_us, TCG_CALL_NO_RWG, i64, i64, i64) +DEF_HELPER_FLAGS_2(hsub_ss, TCG_CALL_NO_RWG, i64, i64, i64) +DEF_HELPER_FLAGS_2(hsub_us, TCG_CALL_NO_RWG, i64, i64, i64) =20 DEF_HELPER_FLAGS_4(probe, TCG_CALL_NO_WG, tl, env, tl, i32, i32) =20 diff --git a/target/hppa/insns.decode b/target/hppa/insns.decode index 88248ed3e2..1830b06c76 100644 --- a/target/hppa/insns.decode +++ b/target/hppa/insns.decode @@ -214,6 +214,10 @@ hadd 000010 ..... ..... 00000011 11 0 .....= @rrr hadd_ss 000010 ..... ..... 00000011 01 0 ..... @rrr hadd_us 000010 ..... ..... 00000011 00 0 ..... @rrr =20 +hsub 000010 ..... ..... 00000001 11 0 ..... @rrr +hsub_ss 000010 ..... ..... 00000001 01 0 ..... @rrr +hsub_us 000010 ..... ..... 00000001 00 0 ..... @rrr + #### # Index Mem #### diff --git a/target/hppa/op_helper.c b/target/hppa/op_helper.c index a230a3a0c3..ece523bea0 100644 --- a/target/hppa/op_helper.c +++ b/target/hppa/op_helper.c @@ -409,3 +409,35 @@ uint64_t HELPER(hadd_us)(uint64_t r1, uint64_t r2) } return ret; } + +uint64_t HELPER(hsub_ss)(uint64_t r1, uint64_t r2) +{ + uint64_t ret =3D 0; + + for (int i =3D 0; i < 64; i +=3D 16) { + int f1 =3D sextract64(r1, i, 16); + int f2 =3D sextract64(r2, i, 16); + int fr =3D f1 - f2; + + fr =3D MIN(fr, INT16_MAX); + fr =3D MAX(fr, INT16_MIN); + ret =3D deposit64(ret, i, 16, fr); + } + return ret; +} + +uint64_t HELPER(hsub_us)(uint64_t r1, uint64_t r2) +{ + uint64_t ret =3D 0; + + for (int i =3D 0; i < 64; i +=3D 16) { + int f1 =3D extract64(r1, i, 16); + int f2 =3D sextract64(r2, i, 16); + int fr =3D f1 - f2; + + fr =3D MIN(fr, UINT16_MAX); + fr =3D MAX(fr, 0); + ret =3D deposit64(ret, i, 16, fr); + } + return ret; +} diff --git a/target/hppa/translate.c b/target/hppa/translate.c index bbf216fcde..97d27cb2a9 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -2776,6 +2776,21 @@ static bool trans_hadd_us(DisasContext *ctx, arg_rrr= *a) return do_multimedia(ctx, a, gen_helper_hadd_us); } =20 +static bool trans_hsub(DisasContext *ctx, arg_rrr *a) +{ + return do_multimedia(ctx, a, tcg_gen_vec_sub16_i64); +} + +static bool trans_hsub_ss(DisasContext *ctx, arg_rrr *a) +{ + return do_multimedia(ctx, a, gen_helper_hsub_ss); +} + +static bool trans_hsub_us(DisasContext *ctx, arg_rrr *a) +{ + return do_multimedia(ctx, a, gen_helper_hsub_us); +} + static bool trans_ld(DisasContext *ctx, arg_ldst *a) { if (!ctx->is_pa20 && a->size > MO_32) { --=20 2.34.1 From nobody Wed Nov 27 18:51:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1697666284; cv=none; d=zohomail.com; s=zohoarc; b=VzG3zOIz2nwGpKWKa5fNFDIUkrlirv05fYHuZyRpJ7snyJRaeXSGJlzhRaFxaGgcb43bcd98CDLv35SkWZ7qhyfzvFVi2ootIosxSj35mJDFzXEfKdBo45VFf7Fnv0lJatHYv0jdYALBBhHNWO7gxt/XuMqJ9uA9fulHGS2EpYc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42c; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697666285357100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/hppa/helper.h | 1 + target/hppa/insns.decode | 2 ++ target/hppa/op_helper.c | 14 ++++++++++++++ target/hppa/translate.c | 5 +++++ 4 files changed, 22 insertions(+) diff --git a/target/hppa/helper.h b/target/hppa/helper.h index 99486f4cf8..1feb2fdfc4 100644 --- a/target/hppa/helper.h +++ b/target/hppa/helper.h @@ -16,6 +16,7 @@ DEF_HELPER_FLAGS_1(ldc_check, TCG_CALL_NO_RWG, void, tl) =20 DEF_HELPER_FLAGS_2(hadd_ss, TCG_CALL_NO_RWG, i64, i64, i64) DEF_HELPER_FLAGS_2(hadd_us, TCG_CALL_NO_RWG, i64, i64, i64) +DEF_HELPER_FLAGS_2(havg, TCG_CALL_NO_RWG, i64, i64, i64) DEF_HELPER_FLAGS_2(hsub_ss, TCG_CALL_NO_RWG, i64, i64, i64) DEF_HELPER_FLAGS_2(hsub_us, TCG_CALL_NO_RWG, i64, i64, i64) =20 diff --git a/target/hppa/insns.decode b/target/hppa/insns.decode index 1830b06c76..fb0f9d6dbd 100644 --- a/target/hppa/insns.decode +++ b/target/hppa/insns.decode @@ -214,6 +214,8 @@ hadd 000010 ..... ..... 00000011 11 0 ..... = @rrr hadd_ss 000010 ..... ..... 00000011 01 0 ..... @rrr hadd_us 000010 ..... ..... 00000011 00 0 ..... @rrr =20 +havg 000010 ..... ..... 00000010 11 0 ..... @rrr + hsub 000010 ..... ..... 00000001 11 0 ..... @rrr hsub_ss 000010 ..... ..... 00000001 01 0 ..... @rrr hsub_us 000010 ..... ..... 00000001 00 0 ..... @rrr diff --git a/target/hppa/op_helper.c b/target/hppa/op_helper.c index ece523bea0..cba610ac75 100644 --- a/target/hppa/op_helper.c +++ b/target/hppa/op_helper.c @@ -410,6 +410,20 @@ uint64_t HELPER(hadd_us)(uint64_t r1, uint64_t r2) return ret; } =20 +uint64_t HELPER(havg)(uint64_t r1, uint64_t r2) +{ + uint64_t ret =3D 0; + + for (int i =3D 0; i < 64; i +=3D 16) { + int f1 =3D extract64(r1, i, 16); + int f2 =3D extract64(r2, i, 16); + int fr =3D f1 + f2; + + ret =3D deposit64(ret, i, 16, (fr >> 1) | (fr & 1)); + } + return ret; +} + uint64_t HELPER(hsub_ss)(uint64_t r1, uint64_t r2) { uint64_t ret =3D 0; diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 97d27cb2a9..b3335ba595 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -2776,6 +2776,11 @@ static bool trans_hadd_us(DisasContext *ctx, arg_rrr= *a) return do_multimedia(ctx, a, gen_helper_hadd_us); } =20 +static bool trans_havg(DisasContext *ctx, arg_rrr *a) +{ + return do_multimedia(ctx, a, gen_helper_havg); +} + static bool trans_hsub(DisasContext *ctx, arg_rrr *a) { return do_multimedia(ctx, a, tcg_gen_vec_sub16_i64); --=20 2.34.1 From nobody Wed Nov 27 18:51:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::c2c; envelope-from=richard.henderson@linaro.org; helo=mail-oo1-xc2c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697666516742100013 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/hppa/insns.decode | 5 +++++ target/hppa/translate.c | 35 +++++++++++++++++++++++++++++++++++ 2 files changed, 40 insertions(+) diff --git a/target/hppa/insns.decode b/target/hppa/insns.decode index fb0f9d6dbd..f0c4866ca2 100644 --- a/target/hppa/insns.decode +++ b/target/hppa/insns.decode @@ -69,6 +69,7 @@ &rrr_cf t r1 r2 cf &rrr_cf_d t r1 r2 cf d &rrr_cf_d_sh t r1 r2 cf d sh +&rri t r i &rri_cf t r i cf &rri_cf_d t r i cf d =20 @@ -216,6 +217,10 @@ hadd_us 000010 ..... ..... 00000011 00 0 .....= @rrr =20 havg 000010 ..... ..... 00000010 11 0 ..... @rrr =20 +hshl 111110 00000 r:5 100010 i:4 0 t:5 &rri +hshr_s 111110 r:5 00000 110011 i:4 0 t:5 &rri +hshr_u 111110 r:5 00000 110010 i:4 0 t:5 &rri + hsub 000010 ..... ..... 00000001 11 0 ..... @rrr hsub_ss 000010 ..... ..... 00000001 01 0 ..... @rrr hsub_us 000010 ..... ..... 00000001 00 0 ..... @rrr diff --git a/target/hppa/translate.c b/target/hppa/translate.c index b3335ba595..b912673531 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -2761,6 +2761,26 @@ static bool do_multimedia(DisasContext *ctx, arg_rrr= *a, return nullify_end(ctx); } =20 +static bool do_multimedia_sh(DisasContext *ctx, arg_rri *a, + void (*fn)(TCGv_i64, TCGv_i64, int64_t)) +{ + TCGv_i64 r, dest; + + if (!ctx->is_pa20) { + return false; + } + + nullify_over(ctx); + + r =3D load_gpr(ctx, a->r); + dest =3D dest_gpr(ctx, a->t); + + fn(dest, r, a->i); + save_gpr(ctx, a->t, dest); + + return nullify_end(ctx); +} + static bool trans_hadd(DisasContext *ctx, arg_rrr *a) { return do_multimedia(ctx, a, tcg_gen_vec_add16_i64); @@ -2781,6 +2801,21 @@ static bool trans_havg(DisasContext *ctx, arg_rrr *a) return do_multimedia(ctx, a, gen_helper_havg); } =20 +static bool trans_hshl(DisasContext *ctx, arg_rri *a) +{ + return do_multimedia_sh(ctx, a, tcg_gen_vec_shl16i_i64); +} + +static bool trans_hshr_s(DisasContext *ctx, arg_rri *a) +{ + return do_multimedia_sh(ctx, a, tcg_gen_vec_sar16i_i64); +} + +static bool trans_hshr_u(DisasContext *ctx, arg_rri *a) +{ + return do_multimedia_sh(ctx, a, tcg_gen_vec_shr16i_i64); +} + static bool trans_hsub(DisasContext *ctx, arg_rrr *a) { return do_multimedia(ctx, a, tcg_gen_vec_sub16_i64); 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::333; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697666492750100003 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/hppa/helper.h | 2 ++ target/hppa/insns.decode | 12 ++++++++++-- target/hppa/op_helper.c | 32 ++++++++++++++++++++++++++++++++ target/hppa/translate.c | 32 ++++++++++++++++++++++++++++++++ 4 files changed, 76 insertions(+), 2 deletions(-) diff --git a/target/hppa/helper.h b/target/hppa/helper.h index 1feb2fdfc4..c4c3093a83 100644 --- a/target/hppa/helper.h +++ b/target/hppa/helper.h @@ -17,6 +17,8 @@ DEF_HELPER_FLAGS_1(ldc_check, TCG_CALL_NO_RWG, void, tl) DEF_HELPER_FLAGS_2(hadd_ss, TCG_CALL_NO_RWG, i64, i64, i64) DEF_HELPER_FLAGS_2(hadd_us, TCG_CALL_NO_RWG, i64, i64, i64) DEF_HELPER_FLAGS_2(havg, TCG_CALL_NO_RWG, i64, i64, i64) +DEF_HELPER_FLAGS_3(hshladd, TCG_CALL_NO_RWG, i64, i64, i64, i32) +DEF_HELPER_FLAGS_3(hshradd, TCG_CALL_NO_RWG, i64, i64, i64, i32) DEF_HELPER_FLAGS_2(hsub_ss, TCG_CALL_NO_RWG, i64, i64, i64) DEF_HELPER_FLAGS_2(hsub_us, TCG_CALL_NO_RWG, i64, i64, i64) =20 diff --git a/target/hppa/insns.decode b/target/hppa/insns.decode index f0c4866ca2..d7befbf73d 100644 --- a/target/hppa/insns.decode +++ b/target/hppa/insns.decode @@ -68,6 +68,7 @@ &rrr t r1 r2 &rrr_cf t r1 r2 cf &rrr_cf_d t r1 r2 cf d +&rrr_sh t r1 r2 sh &rrr_cf_d_sh t r1 r2 cf d sh &rri t r i &rri_cf t r i cf @@ -86,6 +87,7 @@ @rrr ...... r2:5 r1:5 .... ....... t:5 &rrr @rrr_cf ...... r2:5 r1:5 cf:4 ....... t:5 &rrr_cf @rrr_cf_d ...... r2:5 r1:5 cf:4 ...... d:1 t:5 &rrr_cf_d +@rrr_sh ...... r2:5 r1:5 ........ sh:2 . t:5 &rrr_sh @rrr_cf_d_sh ...... r2:5 r1:5 cf:4 .... sh:2 d:1 t:5 &rrr_cf_d_sh @rrr_cf_d_sh0 ...... r2:5 r1:5 cf:4 ...... d:1 t:5 &rrr_cf_d_sh sh=3D0 @rri_cf ...... r:5 t:5 cf:4 . ........... &rri_cf i=3D%lowsi= gn_11 @@ -187,14 +189,20 @@ dcor_i 000010 ..... 00000 .... 101111 . ....= . @rr_cf_d add 000010 ..... ..... .... 0110.. . ..... @rrr_cf_d_sh add_l 000010 ..... ..... .... 1010.. . ..... @rrr_cf_d_sh add_tsv 000010 ..... ..... .... 1110.. . ..... @rrr_cf_d_sh -add_c 000010 ..... ..... .... 011100 . ..... @rrr_cf_d_sh0 +{ + add_c 000010 ..... ..... .... 011100 . ..... @rrr_cf_d_sh0 + hshladd 000010 ..... ..... 0000 0111.. 0 ..... @rrr_sh +} add_c_tsv 000010 ..... ..... .... 111100 . ..... @rrr_cf_d_sh0 =20 sub 000010 ..... ..... .... 010000 . ..... @rrr_cf_d sub_tsv 000010 ..... ..... .... 110000 . ..... @rrr_cf_d sub_tc 000010 ..... ..... .... 010011 . ..... @rrr_cf_d sub_tsv_tc 000010 ..... ..... .... 110011 . ..... @rrr_cf_d -sub_b 000010 ..... ..... .... 010100 . ..... @rrr_cf_d +{ + sub_b 000010 ..... ..... .... 010100 . ..... @rrr_cf_d + hshradd 000010 ..... ..... 0000 0101.. 0 ..... @rrr_sh +} sub_b_tsv 000010 ..... ..... .... 110100 . ..... @rrr_cf_d =20 ldil 001000 t:5 ..................... i=3D%assemble_21 diff --git a/target/hppa/op_helper.c b/target/hppa/op_helper.c index cba610ac75..9d8e728460 100644 --- a/target/hppa/op_helper.c +++ b/target/hppa/op_helper.c @@ -455,3 +455,35 @@ uint64_t HELPER(hsub_us)(uint64_t r1, uint64_t r2) } return ret; } + +uint64_t HELPER(hshladd)(uint64_t r1, uint64_t r2, uint32_t sh) +{ + uint64_t ret =3D 0; + + for (int i =3D 0; i < 64; i +=3D 16) { + int f1 =3D sextract64(r1, i, 16); + int f2 =3D sextract64(r2, i, 16); + int fr =3D (f1 << sh) + f2; + + fr =3D MIN(fr, INT16_MAX); + fr =3D MAX(fr, INT16_MIN); + ret =3D deposit64(ret, i, 16, fr); + } + return ret; +} + +uint64_t HELPER(hshradd)(uint64_t r1, uint64_t r2, uint32_t sh) +{ + uint64_t ret =3D 0; + + for (int i =3D 0; i < 64; i +=3D 16) { + int f1 =3D sextract64(r1, i, 16); + int f2 =3D sextract64(r2, i, 16); + int fr =3D (f1 >> sh) + f2; + + fr =3D MIN(fr, INT16_MAX); + fr =3D MAX(fr, INT16_MIN); + ret =3D deposit64(ret, i, 16, fr); + } + return ret; +} diff --git a/target/hppa/translate.c b/target/hppa/translate.c index b912673531..b0aefecd2e 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -2781,6 +2781,28 @@ static bool do_multimedia_sh(DisasContext *ctx, arg_= rri *a, return nullify_end(ctx); } =20 +static bool do_multimedia_shadd(DisasContext *ctx, arg_rrr_sh *a, + void (*fn)(TCGv_i64, TCGv_i64, + TCGv_i64, TCGv_i32)) +{ + TCGv_i64 r1, r2, dest; + + if (!ctx->is_pa20) { + return false; + } + + nullify_over(ctx); + + r1 =3D load_gpr(ctx, a->r1); + r2 =3D load_gpr(ctx, a->r2); + dest =3D dest_gpr(ctx, a->t); + + fn(dest, r1, r2, tcg_constant_i32(a->sh)); + save_gpr(ctx, a->t, dest); + + return nullify_end(ctx); +} + static bool trans_hadd(DisasContext *ctx, arg_rrr *a) { return do_multimedia(ctx, a, tcg_gen_vec_add16_i64); @@ -2816,6 +2838,16 @@ static bool trans_hshr_u(DisasContext *ctx, arg_rri = *a) return do_multimedia_sh(ctx, a, tcg_gen_vec_shr16i_i64); } =20 +static bool trans_hshladd(DisasContext *ctx, arg_rrr_sh *a) +{ + return do_multimedia_shadd(ctx, a, gen_helper_hshladd); +} + +static bool trans_hshradd(DisasContext *ctx, arg_rrr_sh *a) +{ + return do_multimedia_shadd(ctx, a, gen_helper_hshradd); +} + static bool trans_hsub(DisasContext *ctx, arg_rrr *a) { return do_multimedia(ctx, a, tcg_gen_vec_sub16_i64); --=20 2.34.1 From nobody Wed Nov 27 18:51:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42e; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697666398240100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/hppa/insns.decode | 5 ++++ target/hppa/translate.c | 55 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 60 insertions(+) diff --git a/target/hppa/insns.decode b/target/hppa/insns.decode index d7befbf73d..323e9275bf 100644 --- a/target/hppa/insns.decode +++ b/target/hppa/insns.decode @@ -233,6 +233,11 @@ hsub 000010 ..... ..... 00000001 11 0 .....= @rrr hsub_ss 000010 ..... ..... 00000001 01 0 ..... @rrr hsub_us 000010 ..... ..... 00000001 00 0 ..... @rrr =20 +mixh_l 111110 ..... ..... 1 00 00100000 ..... @rrr +mixh_r 111110 ..... ..... 1 10 00100000 ..... @rrr +mixw_l 111110 ..... ..... 1 00 00000000 ..... @rrr +mixw_r 111110 ..... ..... 1 10 00000000 ..... @rrr + #### # Index Mem #### diff --git a/target/hppa/translate.c b/target/hppa/translate.c index b0aefecd2e..bd8a858da6 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -2863,6 +2863,61 @@ static bool trans_hsub_us(DisasContext *ctx, arg_rrr= *a) return do_multimedia(ctx, a, gen_helper_hsub_us); } =20 +static void gen_mixh_l(TCGv_i64 dst, TCGv_i64 r1, TCGv_i64 r2) +{ + uint64_t mask =3D 0xffff0000ffff0000ull; + TCGv_i64 tmp =3D tcg_temp_new_i64(); + + tcg_gen_andi_i64(tmp, r2, mask); + tcg_gen_andi_i64(dst, r1, mask); + tcg_gen_shri_i64(tmp, tmp, 16); + tcg_gen_or_i64(dst, dst, tmp); +} + +static bool trans_mixh_l(DisasContext *ctx, arg_rrr *a) +{ + return do_multimedia(ctx, a, gen_mixh_l); +} + +static void gen_mixh_r(TCGv_i64 dst, TCGv_i64 r1, TCGv_i64 r2) +{ + uint64_t mask =3D 0x0000ffff0000ffffull; + TCGv_i64 tmp =3D tcg_temp_new_i64(); + + tcg_gen_andi_i64(tmp, r1, mask); + tcg_gen_andi_i64(dst, r2, mask); + tcg_gen_shli_i64(tmp, tmp, 16); + tcg_gen_or_i64(dst, dst, tmp); +} + +static bool trans_mixh_r(DisasContext *ctx, arg_rrr *a) +{ + return do_multimedia(ctx, a, gen_mixh_r); +} + +static void gen_mixw_l(TCGv_i64 dst, TCGv_i64 r1, TCGv_i64 r2) +{ + TCGv_i64 tmp =3D tcg_temp_new_i64(); + + tcg_gen_shri_i64(tmp, r2, 32); + tcg_gen_deposit_i64(dst, r1, tmp, 0, 32); +} + +static bool trans_mixw_l(DisasContext *ctx, arg_rrr *a) +{ + return do_multimedia(ctx, a, gen_mixw_l); +} + +static void gen_mixw_r(TCGv_i64 dst, TCGv_i64 r1, TCGv_i64 r2) +{ + tcg_gen_deposit_i64(dst, r2, r1, 32, 32); +} + +static bool trans_mixw_r(DisasContext *ctx, arg_rrr *a) +{ + return do_multimedia(ctx, a, gen_mixw_r); +} + static bool trans_ld(DisasContext *ctx, arg_ldst *a) { if (!ctx->is_pa20 && a->size > MO_32) { --=20 2.34.1 From nobody Wed Nov 27 18:51:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1697666557; cv=none; d=zohomail.com; s=zohoarc; b=bRbRtbEtycxXTvTVCyDG9ho6ZGQN7V2DPDOS/KLr8rjUl0ywBaNujI7HohVFLgDFij8OQ0ko+tlSvxCjoEvKMZSBWGR8hagQxlspNuK7uW7nR4B51W8vwRuc8Rj30G95sGeNdpwarqmkM0LuCEbqZnk8JjXrfgxKbpk9tYkwzLo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42f; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697666558910100007 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/hppa/insns.decode | 2 ++ target/hppa/translate.c | 29 +++++++++++++++++++++++++++++ 2 files changed, 31 insertions(+) diff --git a/target/hppa/insns.decode b/target/hppa/insns.decode index 323e9275bf..c8f4317576 100644 --- a/target/hppa/insns.decode +++ b/target/hppa/insns.decode @@ -238,6 +238,8 @@ mixh_r 111110 ..... ..... 1 10 00100000 ..... = @rrr mixw_l 111110 ..... ..... 1 00 00000000 ..... @rrr mixw_r 111110 ..... ..... 1 10 00000000 ..... @rrr =20 +permh 111110 r1:5 r2:5 0 c0:2 0 c1:2 c2:2 c3:2 0 t:5 + #### # Index Mem #### diff --git a/target/hppa/translate.c b/target/hppa/translate.c index bd8a858da6..40b5a3d8c3 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -2918,6 +2918,35 @@ static bool trans_mixw_r(DisasContext *ctx, arg_rrr = *a) return do_multimedia(ctx, a, gen_mixw_r); } =20 +static bool trans_permh(DisasContext *ctx, arg_permh *a) +{ + TCGv_i64 r, t0, t1, t2, t3; + + if (!ctx->is_pa20) { + return false; + } + + nullify_over(ctx); + + r =3D load_gpr(ctx, a->r1); + t0 =3D tcg_temp_new_i64(); + t1 =3D tcg_temp_new_i64(); + t2 =3D tcg_temp_new_i64(); + t3 =3D tcg_temp_new_i64(); + + tcg_gen_extract_i64(t0, r, (3 - a->c0) * 16, 16); + tcg_gen_extract_i64(t1, r, (3 - a->c1) * 16, 16); + tcg_gen_extract_i64(t2, r, (3 - a->c2) * 16, 16); + tcg_gen_extract_i64(t3, r, (3 - a->c3) * 16, 16); + + tcg_gen_deposit_i64(t0, t1, t0, 16, 48); + tcg_gen_deposit_i64(t2, t3, t2, 16, 48); + tcg_gen_deposit_i64(t0, t2, t0, 32, 32); + + save_gpr(ctx, a->t, t0); + return nullify_end(ctx); +} + static bool trans_ld(DisasContext *ctx, arg_ldst *a) { if (!ctx->is_pa20 && a->size > MO_32) { --=20 2.34.1 From nobody Wed Nov 27 18:51:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id r15-20020aa7962f000000b006889348ba6esm3796263pfg.127.2023.10.18.14.55.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Oct 2023 14:55:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1697666127; x=1698270927; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=IfXXjPSCAekTKnfIpCckOL6yHpkL7tvWXEcAjeu6hPU=; b=Jv1wp4dy/uMbbKRKlcXmBIXFn8ZmG7/7xM7twHvg5FN9fQCH3D0U5SESPRUd02aBI1 z5+mymZr/YCX/E/dGiGdcX8ObZ8x7pUEqhm2i2kSz0D6KdAOrooRBPSD8zAc2LReRrb9 zGUVEFpQRDKDangngRz9tY4YruZYzsYQAfPus3NIhwSKhYGEbhOHDNZqsVwnQJovdgIw 7bZwCIbPAJXFG93SEI75lb6/NNfXGa0P5uwLEvGyLlm8BSgdwmKW9hbkJuAsN11vXGe6 UsvdeU/F/Sues5eotk+A2G9TAZEAFmIRZdYmBOze3WIWI+Uc0mThyLaYt4g0cu2q3P3D BLFw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697666127; x=1698270927; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=IfXXjPSCAekTKnfIpCckOL6yHpkL7tvWXEcAjeu6hPU=; b=JH1/ZNq1vw2pYbZiM0ftEFFAffcNMwnRBwqWwc0msKKv1XmEcfGa7gy6VShks6Bclh Wmv4UE4AfH2xa2oYMZEVlQn3NJFbevs/QPpDVNtbnYU9BHYY9p35ewxL0xAqpkpeX4Y2 pk9ghIr7k7Tn3tjAUb3jUapOP8EUG63PXIq2GRMFG5RykDp+plCp9M4i8ACCvwZAZH+x vkAASC2k0p4JisrswXV7rcbj483yHoTT0l8/jiKhvSAOKLb+3mcD3ymcxr6nwEixzU0p A7eSN3JSTVIMKqzYbAB8hvodxAlBcRfJ39u/NSBlW+hpCxOUHONpTWuSFEHfuEKghwyJ e1sw== X-Gm-Message-State: AOJu0YwoHQs1E7qPQDESl+DTEkEErCoa/o2Q9G0aJgl/RsN3K1+Txgb/ LKjVAWTPukD0x7x3U4Vy2v8EJU7ujuyluFp0/2k= X-Google-Smtp-Source: AGHT+IEf0qS3Knw3NMn/ddcwS75SfDemZxsP5NTyw4vXtCcN0EKDeyY9y5too4+bMvCxMEPW/o5fYA== X-Received: by 2002:a05:6a00:2789:b0:68a:5cf8:dae4 with SMTP id bd9-20020a056a00278900b0068a5cf8dae4mr168682pfb.3.1697666126834; Wed, 18 Oct 2023 14:55:26 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH 58/61] target/hppa: Fix interruption based on default PSW Date: Wed, 18 Oct 2023 14:51:32 -0700 Message-Id: <20231018215135.1561375-59-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231018215135.1561375-1-richard.henderson@linaro.org> References: <20231018215135.1561375-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::430; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697666571102100003 Content-Type: text/plain; charset="utf-8" From: Helge Deller The default PSW is set by the operating system with the PDC_PSW firmware call. Use that setting to decide if wide mode is to be enabled for interruptions and EIRR usage. Signed-off-by: Helge Deller Reviewed-by: Richard Henderson Signed-off-by: Richard Henderson --- target/hppa/cpu.h | 2 ++ target/hppa/int_helper.c | 17 +++++++++++++---- 2 files changed, 15 insertions(+), 4 deletions(-) diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 5ce05046c0..5c7fddbc2b 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -124,6 +124,8 @@ #define PSW_SM_W 0x200 /* PA2.0 only : Enable Wide Mode */ =20 #define CR_RC 0 +#define CR_PSW_DEFAULT 6 /* see SeaBIOS PDC_PSW firmware call */ +#define PDC_PSW_WIDE_BIT 2 #define CR_PID1 8 #define CR_PID2 9 #define CR_PID3 12 diff --git a/target/hppa/int_helper.c b/target/hppa/int_helper.c index f355c4c76b..021f410bef 100644 --- a/target/hppa/int_helper.c +++ b/target/hppa/int_helper.c @@ -52,9 +52,16 @@ static void io_eir_write(void *opaque, hwaddr addr, uint64_t data, unsigned size) { HPPACPU *cpu =3D opaque; - int le_bit =3D ~data & 31; + int widthm1 =3D 31; + int le_bit; =20 - cpu->env.cr[CR_EIRR] |=3D (target_ulong)1 << le_bit; + /* The default PSW.W controls the width of EIRR. */ + if (cpu->is_pa20 && cpu->env.cr[CR_PSW_DEFAULT] & PDC_PSW_WIDE_BIT) { + widthm1 =3D 63; + } + le_bit =3D ~data & widthm1; + + cpu->env.cr[CR_EIRR] |=3D 1ull << le_bit; eval_interrupt(cpu); } =20 @@ -104,8 +111,10 @@ void hppa_cpu_do_interrupt(CPUState *cs) /* step 1 */ env->cr[CR_IPSW] =3D old_psw =3D cpu_hppa_get_psw(env); =20 - /* step 2 -- note PSW_W =3D=3D 0 for !HPPA64. */ - cpu_hppa_put_psw(env, PSW_W | (i =3D=3D EXCP_HPMC ? PSW_M : 0)); + /* step 2 -- Note PSW_W is masked out again for pa1.x */ + cpu_hppa_put_psw(env, + (env->cr[CR_PSW_DEFAULT] & PDC_PSW_WIDE_BIT ? PSW_W := 0) | + (i =3D=3D EXCP_HPMC ? PSW_M : 0)); =20 /* step 3 */ env->cr[CR_IIASQ] =3D iasq_f >> 32; --=20 2.34.1 From nobody Wed Nov 27 18:51:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1697666398; cv=none; d=zohomail.com; s=zohoarc; b=aRzk+1UPZ9s9eOh4QmsHeEH5I5mu2HUqmPw351aDeb4qN7mG5cMjn62m3NCl9/9nlSQtKstnnP5lPA+kiHww0Y4XLBpNbZnsNNdYFR7wWe/Y+f1/T5AxoLktSNQx1fLtqjdT8OwPT4veIusfZizge/SwQXHnIVe5uacsUTCOWZM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1697666398; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=tHP2tYsmSSxOo6HHRVeOWeqkS383GwwwAeL+hfFxJSs=; b=O7dG1j6Oa6k8MhH+Hj0oNooIGleD22atcm4An8dCE2Si+LLvr0ZhIxCh5+nVWSGDAgSKt7bYiWc2qGRl9H0joe3LgIvppD1D08G2qeBNmXeG/wr4GgMAV+20ExwNiqrcQ/8jBliVyjBRzUaubBtRQinGehIfxnlCo594dhtuXwY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1697666398737189.5152630271598; Wed, 18 Oct 2023 14:59:58 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qtEVn-0002MU-U1; Wed, 18 Oct 2023 17:55:31 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qtEVm-0002Iu-Io for qemu-devel@nongnu.org; Wed, 18 Oct 2023 17:55:30 -0400 Received: from mail-oo1-xc2d.google.com ([2607:f8b0:4864:20::c2d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qtEVk-00058X-Nm for qemu-devel@nongnu.org; Wed, 18 Oct 2023 17:55:30 -0400 Received: by mail-oo1-xc2d.google.com with SMTP id 006d021491bc7-581d487f8dbso1242613eaf.1 for ; Wed, 18 Oct 2023 14:55:28 -0700 (PDT) Received: from stoup.. ([71.212.149.95]) by smtp.gmail.com with ESMTPSA id r15-20020aa7962f000000b006889348ba6esm3796263pfg.127.2023.10.18.14.55.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Oct 2023 14:55:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1697666127; x=1698270927; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=tHP2tYsmSSxOo6HHRVeOWeqkS383GwwwAeL+hfFxJSs=; b=ImD/qiw1YiELKJwJKwCrLZIkYq6QrIrPe5y0ePplAmsnAHgS5/512p59Hd+f9Y0KYI IRwUQTiQDZwpSWFL5z9H3+qqCLTd7s3WfZKbxsx3hu4dThAmxGYNXNyJHT7wVsZzBYtN 5YrsmX86t2lxLOXVzdzQ02Wt6nsICzmn3V5XsUJ7uGm8yLSd8r5wUyRSltYSh9aMkrmk 3LN0jKT5OffVj7ERbBrnmgknYLXpEYQjOFPVpiLZ8YOwNNMotN5jkRbijc+9nwtb7p2B a0s4xiCOtJyLBEiIeA0cQJb4QoEHAqGuHOHwG7gJ4g3OSYxqNqvi6Ks7z8eRQZUT+T91 eODQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697666127; x=1698270927; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=tHP2tYsmSSxOo6HHRVeOWeqkS383GwwwAeL+hfFxJSs=; b=blWhCRPx+axkYUK+7jvcv6L+959e0lPS+Z3j1DIwwXPDphkUPxsdCJ7IzEag9PDBMG mCHTTOCQv+6rQZotkAPPW8/jHSKiJxdNTEl16Nnt3DMlUEUrpYw0JKy1EsR4brvDOjjG r5125NY4SudAsV3ptIkymOMmFuhdWcxaGvdusNkJHKzFatFquPl1ra5XvC03CLeYYFOx FM0KuE1grcSlYhkrKICHHRGaGWop1tWKgWprW2SWVxtvFBSwseFre49mhJNGSZdNpVQa 5+7sb7w6p6ONdXTThVDg3H37N0nkug/+ytKR6F47JjZEthkOAuVc9lE6EHzoHyipSznF NjWw== X-Gm-Message-State: AOJu0YzpuWP+pDmszCrkAVvRgJSByIhCqF+D1TsHeGx5/LI4AssYZ/5p /gGh52B7eWlNETrYPjYwjvaT7gtFDdv8hsFRNfA= X-Google-Smtp-Source: AGHT+IHegTZe4RKPlhcCgZWirONfshWbK/imB1KbIqCDBehCWd9qYQvbYfhDYs9Sx4YJOXqFl+YYZg== X-Received: by 2002:a05:6358:190f:b0:150:8ba9:4d with SMTP id w15-20020a056358190f00b001508ba9004dmr320605rwm.3.1697666127581; Wed, 18 Oct 2023 14:55:27 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH 59/61] target/hppa: Precompute zero into DisasContext Date: Wed, 18 Oct 2023 14:51:33 -0700 Message-Id: <20231018215135.1561375-60-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231018215135.1561375-1-richard.henderson@linaro.org> References: <20231018215135.1561375-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::c2d; envelope-from=richard.henderson@linaro.org; helo=mail-oo1-xc2d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697666400264100005 Content-Type: text/plain; charset="utf-8" Reduce the number of times we look for the constant 0. Signed-off-by: Richard Henderson --- target/hppa/translate.c | 34 ++++++++++++++++++---------------- 1 file changed, 18 insertions(+), 16 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 40b5a3d8c3..9a9876c529 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -53,6 +53,8 @@ typedef struct DisasContext { DisasCond null_cond; TCGLabel *null_lab; =20 + TCGv_i64 zero; + uint32_t insn; uint32_t tb_flags; int mmu_idx; @@ -1004,14 +1006,13 @@ static void do_add(DisasContext *ctx, unsigned rt, = TCGv_i64 in1, } =20 if (!is_l || cond_need_cb(c)) { - TCGv_i64 zero =3D tcg_constant_i64(0); cb_msb =3D tcg_temp_new_i64(); cb =3D tcg_temp_new_i64(); =20 - tcg_gen_add2_i64(dest, cb_msb, in1, zero, in2, zero); + tcg_gen_add2_i64(dest, cb_msb, in1, ctx->zero, in2, ctx->zero); if (is_c) { tcg_gen_add2_i64(dest, cb_msb, dest, cb_msb, - get_psw_carry(ctx, d), zero); + get_psw_carry(ctx, d), ctx->zero); } tcg_gen_xor_i64(cb, in1, in2); tcg_gen_xor_i64(cb, cb, dest); @@ -1089,7 +1090,7 @@ static void do_sub(DisasContext *ctx, unsigned rt, TC= Gv_i64 in1, TCGv_i64 in2, bool is_tsv, bool is_b, bool is_tc, unsigned cf, bool d) { - TCGv_i64 dest, sv, cb, cb_msb, zero, tmp; + TCGv_i64 dest, sv, cb, cb_msb, tmp; unsigned c =3D cf >> 1; DisasCond cond; =20 @@ -1097,12 +1098,12 @@ static void do_sub(DisasContext *ctx, unsigned rt, = TCGv_i64 in1, cb =3D tcg_temp_new_i64(); cb_msb =3D tcg_temp_new_i64(); =20 - zero =3D tcg_constant_i64(0); if (is_b) { /* DEST,C =3D IN1 + ~IN2 + C. */ tcg_gen_not_i64(cb, in2); - tcg_gen_add2_i64(dest, cb_msb, in1, zero, get_psw_carry(ctx, d), z= ero); - tcg_gen_add2_i64(dest, cb_msb, dest, cb_msb, cb, zero); + tcg_gen_add2_i64(dest, cb_msb, in1, ctx->zero, + get_psw_carry(ctx, d), ctx->zero); + tcg_gen_add2_i64(dest, cb_msb, dest, cb_msb, cb, ctx->zero); tcg_gen_xor_i64(cb, cb, in1); tcg_gen_xor_i64(cb, cb, dest); } else { @@ -1111,7 +1112,7 @@ static void do_sub(DisasContext *ctx, unsigned rt, TC= Gv_i64 in1, * operations by seeding the high word with 1 and subtracting. */ TCGv_i64 one =3D tcg_constant_i64(1); - tcg_gen_sub2_i64(dest, cb_msb, in1, one, in2, zero); + tcg_gen_sub2_i64(dest, cb_msb, in1, one, in2, ctx->zero); tcg_gen_eqv_i64(cb, in1, in2); tcg_gen_xor_i64(cb, cb, dest); } @@ -2430,7 +2431,7 @@ static bool trans_lci(DisasContext *ctx, arg_lci *a) physical address. Two addresses with the same CI have a coherent view of the cache. Our implementation is to return 0 for all, since the entire address space is coherent. */ - save_gpr(ctx, a->t, tcg_constant_i64(0)); + save_gpr(ctx, a->t, ctx->zero); =20 cond_free(&ctx->null_cond); return true; @@ -2639,7 +2640,7 @@ static bool trans_dcor_i(DisasContext *ctx, arg_rr_cf= _d *a) =20 static bool trans_ds(DisasContext *ctx, arg_rrr_cf *a) { - TCGv_i64 dest, add1, add2, addc, zero, in1, in2; + TCGv_i64 dest, add1, add2, addc, in1, in2; TCGv_i64 cout; =20 nullify_over(ctx); @@ -2651,7 +2652,6 @@ static bool trans_ds(DisasContext *ctx, arg_rrr_cf *a) add2 =3D tcg_temp_new_i64(); addc =3D tcg_temp_new_i64(); dest =3D tcg_temp_new_i64(); - zero =3D tcg_constant_i64(0); =20 /* Form R1 << 1 | PSW[CB]{8}. */ tcg_gen_add_i64(add1, in1, in1); @@ -2667,8 +2667,9 @@ static bool trans_ds(DisasContext *ctx, arg_rrr_cf *a) tcg_gen_xor_i64(add2, in2, addc); tcg_gen_andi_i64(addc, addc, 1); =20 - tcg_gen_add2_i64(dest, cpu_psw_cb_msb, add1, zero, add2, zero); - tcg_gen_add2_i64(dest, cpu_psw_cb_msb, dest, cpu_psw_cb_msb, addc, zer= o); + tcg_gen_add2_i64(dest, cpu_psw_cb_msb, add1, ctx->zero, add2, ctx->zer= o); + tcg_gen_add2_i64(dest, cpu_psw_cb_msb, dest, cpu_psw_cb_msb, + addc, ctx->zero); =20 /* Write back the result register. */ save_gpr(ctx, a->t, dest); @@ -2968,7 +2969,7 @@ static bool trans_st(DisasContext *ctx, arg_ldst *a) static bool trans_ldc(DisasContext *ctx, arg_ldst *a) { MemOp mop =3D MO_TE | MO_ALIGN | a->size; - TCGv_i64 zero, dest, ofs; + TCGv_i64 dest, ofs; TCGv_i64 addr; =20 if (!ctx->is_pa20 && a->size > MO_32) { @@ -2998,8 +2999,7 @@ static bool trans_ldc(DisasContext *ctx, arg_ldst *a) */ gen_helper_ldc_check(addr); =20 - zero =3D tcg_constant_i64(0); - tcg_gen_atomic_xchg_i64(dest, addr, zero, ctx->mmu_idx, mop); + tcg_gen_atomic_xchg_i64(dest, addr, ctx->zero, ctx->mmu_idx, mop); =20 if (a->m) { save_gpr(ctx, a->b, ofs); @@ -4337,6 +4337,8 @@ static void hppa_tr_init_disas_context(DisasContextBa= se *dcbase, CPUState *cs) ctx->iaoq_n =3D -1; ctx->iaoq_n_var =3D NULL; =20 + ctx->zero =3D tcg_constant_i64(0); + /* Bound the number of instructions by those left on the page. */ bound =3D -(ctx->base.pc_first | TARGET_PAGE_MASK) / 4; ctx->base.max_insns =3D MIN(ctx->base.max_insns, bound); --=20 2.34.1 From nobody Wed Nov 27 18:51:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1697666513; cv=none; d=zohomail.com; s=zohoarc; b=e0Any/isMuskXDSSr/4Mky55TU22HnUgXQyuXsTVSjUlEN7qNWsLgzD3AamtUp+I0X6HpArErNKzjFw6+XVDATLhs63s32xcLocR8U2UIPYwJFc77/SyyfNhTAtQkPbAVcPUX0N+on13GYP0uNzhIgZDRvZoG5NFPo25lpxllzI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1697666513; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=fmtUHmtXH5nM9zU0wQnJIph+Od9hcdbRCgT1SyGzFJs=; b=CsdV+gOtzy7jGoQpVKIEUnmkRHvb5cntZ0pDRQfg8jmmyn1g2pAFv6P5dRwLKa9YK/Ge0GwDD+uY0uIQthgZUjPYb0EQq4Lhdol+Bj0i8HeZM1dpP5f56NUIlMpM9o3yRDjPGTG9orImF5plAp7uetZ8jGF2wFNXcG+O/+U3+r4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1697666513337790.0049461102458; Wed, 18 Oct 2023 15:01:53 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qtEVr-0002Y7-SH; Wed, 18 Oct 2023 17:55:35 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qtEVn-0002Kb-4i for qemu-devel@nongnu.org; Wed, 18 Oct 2023 17:55:31 -0400 Received: from mail-oo1-xc29.google.com ([2607:f8b0:4864:20::c29]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qtEVl-00059R-Ld for qemu-devel@nongnu.org; Wed, 18 Oct 2023 17:55:30 -0400 Received: by mail-oo1-xc29.google.com with SMTP id 006d021491bc7-57b68556d6dso4072750eaf.1 for ; Wed, 18 Oct 2023 14:55:29 -0700 (PDT) Received: from stoup.. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::c29; envelope-from=richard.henderson@linaro.org; helo=mail-oo1-xc29.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697666514885100009 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/hppa/translate.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 9a9876c529..a9e0e1706f 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -307,9 +307,7 @@ static void cond_free(DisasCond *cond) static TCGv_i64 load_gpr(DisasContext *ctx, unsigned reg) { if (reg =3D=3D 0) { - TCGv_i64 t =3D tcg_temp_new_i64(); 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id r15-20020aa7962f000000b006889348ba6esm3796263pfg.127.2023.10.18.14.55.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Oct 2023 14:55:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1697666129; x=1698270929; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=bHJACBbF9+uJIXW5w/FHxtZpUnFRR5qhz5RTWQgzwyE=; b=dSgcWlCfzhAx+Tb6iYsZCaT5ZgDQBvMWum4STXVeXIhhPxhTBNg9zVkxqzbd9Fo2qu rTwRWC22w5P/HQmaMq3Ig02m9act/JNMSGXRKVz21CcMkKmGyVLLi6EaCQGF4hGhDc3U YqNI9gKB5weHPWhYOok0fKx32hba4EZ6swdq8qSOcdCY1cQfO3A9bjTczVwg7S5ahmLm mw4LL3cgfXUYym6NuMLVAR5XuFrT0vtqqlJLlkU/T/emF0BTZRZocEot+lbeDg2kVP3D peYEl21yp4WyAvS/IEidkspq5gbJAi7Qt0j3QR4FSg4ta0rGNVzsO1/pz53m6cG5s1Yi 7+vw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697666129; x=1698270929; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=bHJACBbF9+uJIXW5w/FHxtZpUnFRR5qhz5RTWQgzwyE=; b=TVf69puw3wv43mA7Ks7F62KvFtcfXtn/5vIFG2v7V988rp0Wzl4Epc79OUyUkYFINo T0ioZIl+5cQiSr4JHJUvNZFf8MFAhHMlDXBEGqatDW2x2wrCiIiuKIfIBU/0PiUISi5S XCUQsQUNL03GVZUoHfMTHns1NGfzJX5pWtN4Lmd8P6PjzbXe5zQMxjW956J060ZgJHt0 YRcvPYyLMcmWrmLcdZXULQ2fRC6yfy1y5OVSXYQ+nH5x/IAihxvMcX+zxZigc7yeGF5K 4v4KlK9eQvaZrNIvLmuhCFk0p+7R9vtuP7nyOiX6unbkLsxX05KK4B5Hj2sW30HUUkoG yL4A== X-Gm-Message-State: AOJu0Yy18YcBVmuWJ5SCIPAm+eevCVX5FEKhX6DYnm1o8LcwoqCEBV+g UjxLy1zfLx8idurrA04w+M1Pz0RU6mlDK4RVGeU= X-Google-Smtp-Source: AGHT+IG+eLqL3CGQ2mgCgE1Xgh7vd7rshBzReNb+um9k7z8QSrOMRt6cWtDc+ecqcju5yOOJKWQ2Tg== X-Received: by 2002:a05:6a00:a1a:b0:6be:43d5:6505 with SMTP id p26-20020a056a000a1a00b006be43d56505mr417860pfh.6.1697666129395; Wed, 18 Oct 2023 14:55:29 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH 61/61] target/hppa: Simplify trans_dep*_imm Date: Wed, 18 Oct 2023 14:51:35 -0700 Message-Id: <20231018215135.1561375-62-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231018215135.1561375-1-richard.henderson@linaro.org> References: <20231018215135.1561375-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42c; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697666332053100006 Content-Type: text/plain; charset="utf-8" All of the special cases here are now handled during generic expansion. Signed-off-by: Richard Henderson --- target/hppa/translate.c | 80 +++++++++++++---------------------------- 1 file changed, 25 insertions(+), 55 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index a9e0e1706f..e8ce41b5a7 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -3473,80 +3473,50 @@ static bool trans_extr_imm(DisasContext *ctx, arg_e= xtr_imm *a) return nullify_end(ctx); } =20 -static bool trans_depi_imm(DisasContext *ctx, arg_depi_imm *a) +static bool do_dep_imm(DisasContext *ctx, unsigned rt, unsigned c, + bool d, unsigned len, unsigned cpos, + TCGv_i64 src, TCGv_i64 val) { - unsigned len, width; - uint64_t mask0, mask1; + unsigned width =3D d ? 64 : 32; TCGv_i64 dest; =20 - if (!ctx->is_pa20 && a->d) { - return false; + if (cpos + len > width) { + len =3D width - cpos; } - if (a->c) { + + if (c) { nullify_over(ctx); } =20 - len =3D a->len; - width =3D a->d ? 64 : 32; - if (a->cpos + len > width) { - len =3D width - a->cpos; - } + dest =3D dest_gpr(ctx, rt); + tcg_gen_deposit_i64(dest, src, val, cpos, len); + save_gpr(ctx, rt, dest); =20 - dest =3D dest_gpr(ctx, a->t); - mask0 =3D deposit64(0, a->cpos, len, a->i); - mask1 =3D deposit64(-1, a->cpos, len, a->i); - - if (a->nz) { - TCGv_i64 src =3D load_gpr(ctx, a->t); - tcg_gen_andi_i64(dest, src, mask1); - tcg_gen_ori_i64(dest, dest, mask0); - } else { - tcg_gen_movi_i64(dest, mask0); - } - save_gpr(ctx, a->t, dest); - - /* Install the new nullification. */ cond_free(&ctx->null_cond); - if (a->c) { - ctx->null_cond =3D do_sed_cond(ctx, a->c, a->d, dest); + if (c) { + ctx->null_cond =3D do_sed_cond(ctx, c, d, dest); } return nullify_end(ctx); } =20 -static bool trans_dep_imm(DisasContext *ctx, arg_dep_imm *a) +static bool trans_depi_imm(DisasContext *ctx, arg_depi_imm *a) { - unsigned rs =3D a->nz ? a->t : 0; - unsigned len, width; - TCGv_i64 dest, val; - if (!ctx->is_pa20 && a->d) { return false; } - if (a->c) { - nullify_over(ctx); - } + return do_dep_imm(ctx, a->t, a->c, a->d, a->len, a->cpos, + a->nz ? load_gpr(ctx, a->t) : ctx->zero, + tcg_constant_i64(a->i)); +} =20 - len =3D a->len; - width =3D a->d ? 64 : 32; - if (a->cpos + len > width) { - len =3D width - a->cpos; +static bool trans_dep_imm(DisasContext *ctx, arg_dep_imm *a) +{ + if (!ctx->is_pa20 && a->d) { + return false; } - - dest =3D dest_gpr(ctx, a->t); - val =3D load_gpr(ctx, a->r); - if (rs =3D=3D 0) { - tcg_gen_deposit_z_i64(dest, val, a->cpos, len); - } else { - tcg_gen_deposit_i64(dest, cpu_gr[rs], val, a->cpos, len); - } - save_gpr(ctx, a->t, dest); - - /* Install the new nullification. */ - cond_free(&ctx->null_cond); - if (a->c) { - ctx->null_cond =3D do_sed_cond(ctx, a->c, a->d, dest); - } - return nullify_end(ctx); + return do_dep_imm(ctx, a->t, a->c, a->d, a->len, a->cpos, + a->nz ? load_gpr(ctx, a->t) : ctx->zero, + load_gpr(ctx, a->r)); } =20 static bool do_dep_sar(DisasContext *ctx, unsigned rt, unsigned c, --=20 2.34.1