From nobody Wed Nov 27 20:38:12 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=google.com ARC-Seal: i=1; a=rsa-sha256; t=1697652980; cv=none; d=zohomail.com; s=zohoarc; b=PQBKTu0kZ4IFH/mO8cIGE9DOWbX8AO/kCNSsC25IlQ1BcHWL1Pxt70d+Zop/vqCE5iep+Mah7Yq5R8zQ5g4wtr+SKwuZomNFERfcWcSJbaExKoeyv+v4yop09yaatYkrKJnTpA7w7XgKrIM0jg5meCVnNMPuc64uhetAslEFS4w= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1697652980; h=Content-Type:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=90akPlnyRJ5zgnZFIuWWHhh2caiIuDeE7ak8tV8kgG4=; b=Yq9H5VIbXQ5KbxxBsdHXYALvgoOAdGytY7vcxGYxDo54rqfHI6xBML7FUkvN08qjf1epRE2yfCdQZrPXtKJBzNlBelpcroWGgnAiXg8jiECyPFi06d+jP/a6Y5geHArOO7Frrru9FGfQ5HBkgSFau03EfnGZwhvjET7Vadh6XGg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1697652980538203.94371182372174; Wed, 18 Oct 2023 11:16:20 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qtB1p-0006om-9a; Wed, 18 Oct 2023 14:12:21 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from <3_R8wZQwKCi4XKLSROcdOPKXQYYQVO.MYWaOWe-NOfOVXYXQXe.YbQ@flex--nabihestefan.bounces.google.com>) id 1qtB1n-0006m0-TR for qemu-devel@nongnu.org; Wed, 18 Oct 2023 14:12:19 -0400 Received: from mail-yw1-x1149.google.com ([2607:f8b0:4864:20::1149]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from <3_R8wZQwKCi4XKLSROcdOPKXQYYQVO.MYWaOWe-NOfOVXYXQXe.YbQ@flex--nabihestefan.bounces.google.com>) id 1qtB1j-0008CX-7V for qemu-devel@nongnu.org; Wed, 18 Oct 2023 14:12:19 -0400 Received: by mail-yw1-x1149.google.com with SMTP id 00721157ae682-5a7cfdacf8fso63575867b3.0 for ; Wed, 18 Oct 2023 11:12:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1697652733; x=1698257533; darn=nongnu.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=90akPlnyRJ5zgnZFIuWWHhh2caiIuDeE7ak8tV8kgG4=; b=ZLTquW+4AZFeIHYiXPsdEPYkm+Lsy8sNcgMXkLGfEM2GOcLEchuY1fd+IPJ/tGJIWG 2/S2/I6TMEMZ5OJ2HmvIc87NCINpqPqUaBIpxasrXiSz7c8HviSd9/r4ha5Z205vFcok XHw0Mf5J1h6D9+2oQmAX9S2otvco64aRj5XGLC1MBKQKm0xTijqzrrR9RX+bw1rxCRsA S+SLMN/Ps7ppRRUdGddu/E+hhYSiixsOBS/R0Yj2ds4hXQ6jvVpuJUb4CYY6J43n86wh 6jdJeSQCkYVxf7rdgFylNST0tStieuWTWEaAAS6tpdZhg9kR2jT/l02BYmoQ2hI7IX2m oXBQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697652733; x=1698257533; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=90akPlnyRJ5zgnZFIuWWHhh2caiIuDeE7ak8tV8kgG4=; b=c6hmRrkrgW7DxP9f+uaienKn1MGdteyjnhkyKv3YxBJmOrteI/cGy8c9GzIfmr5fHw e2IhBb42EmAjXlwqFwaBg2tHLvGV/f5sxqUYY7N/RU0qNnLaygeusr7V+n9T4f4Z2AE2 +PKEmB5A5wj+gv3Krd8k77GIOq7kxWP4sp75gm87nov2haMXNgWlt4M4bHhXPw0adoss +L/RDgdw334JsFt1G0L/7rv6ec2mtT4WS8oftMEzfEfO9DYuEAlG3ETdzO7k/2n9Bof5 lYnvKALEwMK52Q0rgFAp1ykbo6GxmpV3JBSFMRkBxl/h5OsB9l4Mt9SjdsHfwFfVYo0E oogA== X-Gm-Message-State: AOJu0Yyjn4IQiEnRZkjVrjWqQUvzGaR0tFiUe4nLPcdTp4bAJweVsl8t cs+Z0IT2vLqx2pMSnWDUApZADYitA0P2K5i8Z7A= X-Google-Smtp-Source: AGHT+IGWYgI7ulgEIvO+7hytcQlWUrfKg0cwA22oxr0NSq4dMsBtqzGNAZODxh1xwBJCmMYqB0iys8xyjnw0xPb8/6A= X-Received: from nabihestefan.c.googlers.com ([fda3:e722:ac3:cc00:20:ed76:c0a8:2737]) (user=nabihestefan job=sendgmr) by 2002:a25:74cc:0:b0:d89:cd65:c2b0 with SMTP id p195-20020a2574cc000000b00d89cd65c2b0mr152457ybc.6.1697652733659; Wed, 18 Oct 2023 11:12:13 -0700 (PDT) Date: Wed, 18 Oct 2023 18:11:52 +0000 In-Reply-To: <20231018181152.745496-1-nabihestefan@google.com> Mime-Version: 1.0 References: <20231018181152.745496-1-nabihestefan@google.com> X-Mailer: git-send-email 2.42.0.655.g421f12c284-goog Message-ID: <20231018181152.745496-12-nabihestefan@google.com> Subject: [PATCH 11/11] tests/qtest: Adding PCS Module test to GMAC Qtest From: Nabih Estefan To: peter.maydell@linaro.org Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, kfting@nuvoton.com, wuhaotsh@google.com, jasonwang@redhat.com, avi.fishman@nuvoton.com, nabihestefan@google.com Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1149; envelope-from=3_R8wZQwKCi4XKLSROcdOPKXQYYQVO.MYWaOWe-NOfOVXYXQXe.YbQ@flex--nabihestefan.bounces.google.com; helo=mail-yw1-x1149.google.com X-Spam_score_int: -95 X-Spam_score: -9.6 X-Spam_bar: --------- X-Spam_report: (-9.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SPF_TEMPERROR=0.01, UPPERCASE_50_75=0.008, USER_IN_DEF_DKIM_WL=-7.5 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @google.com) X-ZM-MESSAGEID: 1697652981687100003 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Nabih Estefan Diaz - Add PCS Register check to npcm_gmac-test Signed-off-by: Nabih Estefan Diaz --- tests/qtest/npcm_gmac-test.c | 134 ++++++++++++++++++++++++++++++++++- 1 file changed, 133 insertions(+), 1 deletion(-) diff --git a/tests/qtest/npcm_gmac-test.c b/tests/qtest/npcm_gmac-test.c index 130a1599a8..0958b13814 100644 --- a/tests/qtest/npcm_gmac-test.c +++ b/tests/qtest/npcm_gmac-test.c @@ -20,6 +20,10 @@ /* Name of the GMAC Device */ #define TYPE_NPCM_GMAC "npcm-gmac" =20 +/* Address of the PCS Module */ +#define PCS_BASE_ADDRESS 0xf0780000 +#define NPCM_PCS_IND_AC_BA 0x1fe + typedef struct GMACModule { int irq; uint64_t base_addr; @@ -111,6 +115,62 @@ typedef enum NPCMRegister { NPCM_GMAC_PTP_STNSUR =3D 0x714, NPCM_GMAC_PTP_TAR =3D 0x718, NPCM_GMAC_PTP_TTSR =3D 0x71c, + + /* PCS Registers */ + NPCM_PCS_SR_CTL_ID1 =3D 0x3c0008, + NPCM_PCS_SR_CTL_ID2 =3D 0x3c000a, + NPCM_PCS_SR_CTL_STS =3D 0x3c0010, + + NPCM_PCS_SR_MII_CTRL =3D 0x3e0000, + NPCM_PCS_SR_MII_STS =3D 0x3e0002, + NPCM_PCS_SR_MII_DEV_ID1 =3D 0x3e0004, + NPCM_PCS_SR_MII_DEV_ID2 =3D 0x3e0006, + NPCM_PCS_SR_MII_AN_ADV =3D 0x3e0008, + NPCM_PCS_SR_MII_LP_BABL =3D 0x3e000a, + NPCM_PCS_SR_MII_AN_EXPN =3D 0x3e000c, + NPCM_PCS_SR_MII_EXT_STS =3D 0x3e001e, + + NPCM_PCS_SR_TIM_SYNC_ABL =3D 0x3e0e10, + NPCM_PCS_SR_TIM_SYNC_TX_MAX_DLY_LWR =3D 0x3e0e12, + NPCM_PCS_SR_TIM_SYNC_TX_MAX_DLY_UPR =3D 0x3e0e14, + NPCM_PCS_SR_TIM_SYNC_TX_MIN_DLY_LWR =3D 0x3e0e16, + NPCM_PCS_SR_TIM_SYNC_TX_MIN_DLY_UPR =3D 0x3e0e18, + NPCM_PCS_SR_TIM_SYNC_RX_MAX_DLY_LWR =3D 0x3e0e1a, + NPCM_PCS_SR_TIM_SYNC_RX_MAX_DLY_UPR =3D 0x3e0e1c, + NPCM_PCS_SR_TIM_SYNC_RX_MIN_DLY_LWR =3D 0x3e0e1e, + NPCM_PCS_SR_TIM_SYNC_RX_MIN_DLY_UPR =3D 0x3e0e20, + + NPCM_PCS_VR_MII_MMD_DIG_CTRL1 =3D 0x3f0000, + NPCM_PCS_VR_MII_AN_CTRL =3D 0x3f0002, + NPCM_PCS_VR_MII_AN_INTR_STS =3D 0x3f0004, + NPCM_PCS_VR_MII_TC =3D 0x3f0006, + NPCM_PCS_VR_MII_DBG_CTRL =3D 0x3f000a, + NPCM_PCS_VR_MII_EEE_MCTRL0 =3D 0x3f000c, + NPCM_PCS_VR_MII_EEE_TXTIMER =3D 0x3f0010, + NPCM_PCS_VR_MII_EEE_RXTIMER =3D 0x3f0012, + NPCM_PCS_VR_MII_LINK_TIMER_CTRL =3D 0x3f0014, + NPCM_PCS_VR_MII_EEE_MCTRL1 =3D 0x3f0016, + NPCM_PCS_VR_MII_DIG_STS =3D 0x3f0020, + NPCM_PCS_VR_MII_ICG_ERRCNT1 =3D 0x3f0022, + NPCM_PCS_VR_MII_MISC_STS =3D 0x3f0030, + NPCM_PCS_VR_MII_RX_LSTS =3D 0x3f0040, + NPCM_PCS_VR_MII_MP_TX_BSTCTRL0 =3D 0x3f0070, + NPCM_PCS_VR_MII_MP_TX_LVLCTRL0 =3D 0x3f0074, + NPCM_PCS_VR_MII_MP_TX_GENCTRL0 =3D 0x3f007a, + NPCM_PCS_VR_MII_MP_TX_GENCTRL1 =3D 0x3f007c, + NPCM_PCS_VR_MII_MP_TX_STS =3D 0x3f0090, + NPCM_PCS_VR_MII_MP_RX_GENCTRL0 =3D 0x3f00b0, + NPCM_PCS_VR_MII_MP_RX_GENCTRL1 =3D 0x3f00b2, + NPCM_PCS_VR_MII_MP_RX_LOS_CTRL0 =3D 0x3f00ba, + NPCM_PCS_VR_MII_MP_MPLL_CTRL0 =3D 0x3f00f0, + NPCM_PCS_VR_MII_MP_MPLL_CTRL1 =3D 0x3f00f2, + NPCM_PCS_VR_MII_MP_MPLL_STS =3D 0x3f0110, + NPCM_PCS_VR_MII_MP_MISC_CTRL2 =3D 0x3f0126, + NPCM_PCS_VR_MII_MP_LVL_CTRL =3D 0x3f0130, + NPCM_PCS_VR_MII_MP_MISC_CTRL0 =3D 0x3f0132, + NPCM_PCS_VR_MII_MP_MISC_CTRL1 =3D 0x3f0134, + NPCM_PCS_VR_MII_DIG_CTRL2 =3D 0x3f01c2, + NPCM_PCS_VR_MII_DIG_ERRCNT_SEL =3D 0x3f01c4, } NPCMRegister; =20 static uint32_t gmac_read(QTestState *qts, const GMACModule *mod, @@ -119,6 +179,15 @@ static uint32_t gmac_read(QTestState *qts, const GMACM= odule *mod, return qtest_readl(qts, mod->base_addr + regno); } =20 +static uint16_t pcs_read(QTestState *qts, const GMACModule *mod, + NPCMRegister regno) +{ + uint32_t write_value =3D (regno & 0x3ffe00) >> 9; + qtest_writel(qts, PCS_BASE_ADDRESS + NPCM_PCS_IND_AC_BA, write_value); + uint32_t read_offset =3D regno & 0x1ff; + return qtest_readl(qts, PCS_BASE_ADDRESS + read_offset); +} + /* Check that GMAC registers are reset to default value */ static void test_init(gconstpointer test_data) { @@ -129,7 +198,12 @@ static void test_init(gconstpointer test_data) #define CHECK_REG32(regno, value) \ do { \ g_assert_cmphex(gmac_read(qts, mod, (regno)), =3D=3D, (value)); \ - } while (0) + } while (0) ; + +#define CHECK_REG_PCS(regno, value) \ + do { \ + g_assert_cmphex(pcs_read(qts, mod, (regno)), =3D=3D, (value)); \ + } while (0) ; =20 CHECK_REG32(NPCM_DMA_BUS_MODE, 0x00020100); CHECK_REG32(NPCM_DMA_XMT_POLL_DEMAND, 0); @@ -180,6 +254,64 @@ static void test_init(gconstpointer test_data) CHECK_REG32(NPCM_GMAC_PTP_TAR, 0); CHECK_REG32(NPCM_GMAC_PTP_TTSR, 0); =20 + /* TODO Add registers PCS */ + if (mod->base_addr =3D=3D 0xf0802000) { + CHECK_REG_PCS(NPCM_PCS_SR_CTL_ID1, 0x699e) + CHECK_REG_PCS(NPCM_PCS_SR_CTL_ID2, 0) + CHECK_REG_PCS(NPCM_PCS_SR_CTL_STS, 0x8000) + + CHECK_REG_PCS(NPCM_PCS_SR_MII_CTRL, 0x1140) + CHECK_REG_PCS(NPCM_PCS_SR_MII_STS, 0x0109) + CHECK_REG_PCS(NPCM_PCS_SR_MII_DEV_ID1, 0x699e) + CHECK_REG_PCS(NPCM_PCS_SR_MII_DEV_ID2, 0x0ced0) + CHECK_REG_PCS(NPCM_PCS_SR_MII_AN_ADV, 0x0020) + CHECK_REG_PCS(NPCM_PCS_SR_MII_LP_BABL, 0) + CHECK_REG_PCS(NPCM_PCS_SR_MII_AN_EXPN, 0) + CHECK_REG_PCS(NPCM_PCS_SR_MII_EXT_STS, 0xc000) + + CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_ABL, 0x0003) + CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_TX_MAX_DLY_LWR, 0x0038) + CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_TX_MAX_DLY_UPR, 0) + CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_TX_MIN_DLY_LWR, 0x0038) + CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_TX_MIN_DLY_UPR, 0) + CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_RX_MAX_DLY_LWR, 0x0058) + CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_RX_MAX_DLY_UPR, 0) + CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_RX_MIN_DLY_LWR, 0x0048) + CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_RX_MIN_DLY_UPR, 0) + + CHECK_REG_PCS(NPCM_PCS_VR_MII_MMD_DIG_CTRL1, 0x2400) + CHECK_REG_PCS(NPCM_PCS_VR_MII_AN_CTRL, 0) + CHECK_REG_PCS(NPCM_PCS_VR_MII_AN_INTR_STS, 0x000a) + CHECK_REG_PCS(NPCM_PCS_VR_MII_TC, 0) + CHECK_REG_PCS(NPCM_PCS_VR_MII_DBG_CTRL, 0) + CHECK_REG_PCS(NPCM_PCS_VR_MII_EEE_MCTRL0, 0x899c) + CHECK_REG_PCS(NPCM_PCS_VR_MII_EEE_TXTIMER, 0) + CHECK_REG_PCS(NPCM_PCS_VR_MII_EEE_RXTIMER, 0) + CHECK_REG_PCS(NPCM_PCS_VR_MII_LINK_TIMER_CTRL, 0) + CHECK_REG_PCS(NPCM_PCS_VR_MII_EEE_MCTRL1, 0) + CHECK_REG_PCS(NPCM_PCS_VR_MII_DIG_STS, 0x0010) + CHECK_REG_PCS(NPCM_PCS_VR_MII_ICG_ERRCNT1, 0) + CHECK_REG_PCS(NPCM_PCS_VR_MII_MISC_STS, 0) + CHECK_REG_PCS(NPCM_PCS_VR_MII_RX_LSTS, 0) + CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_TX_BSTCTRL0, 0x00a) + CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_TX_LVLCTRL0, 0x007f) + CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_TX_GENCTRL0, 0x0001) + CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_TX_GENCTRL1, 0) + CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_TX_STS, 0) + CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_RX_GENCTRL0, 0x0100) + CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_RX_GENCTRL1, 0x1100) + CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_RX_LOS_CTRL0, 0x000e) + CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_MPLL_CTRL0, 0x0100) + CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_MPLL_CTRL1, 0x0032) + CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_MPLL_STS, 0x0001) + CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_MISC_CTRL2, 0) + CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_LVL_CTRL, 0x0019) + CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_MISC_CTRL0, 0) + CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_MISC_CTRL1, 0) + CHECK_REG_PCS(NPCM_PCS_VR_MII_DIG_CTRL2, 0) + CHECK_REG_PCS(NPCM_PCS_VR_MII_DIG_ERRCNT_SEL, 0) + } + qtest_quit(qts); } =20 --=20 2.42.0.655.g421f12c284-goog