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Sat, 14 Oct 2023 03:01:39 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHaTcA3z1ebPPQcvgS+Y5SzU5ShRgib0paegdeQwhEFJcyLy86SkzUfDmbD65e/UwfICSdUTw== X-Received: by 2002:a2e:a9a2:0:b0:2c5:84c:62d3 with SMTP id x34-20020a2ea9a2000000b002c5084c62d3mr2907384ljq.5.1697277699276; Sat, 14 Oct 2023 03:01:39 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Subject: [PATCH 09/18] target/i386: do not clobber A0 in POP translation Date: Sat, 14 Oct 2023 12:01:11 +0200 Message-ID: <20231014100121.109817-10-pbonzini@redhat.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231014100121.109817-1-pbonzini@redhat.com> References: <20231014100121.109817-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1697278065065100003 Content-Type: text/plain; charset="utf-8" The new decoder likes to compute the address in A0 very early, so the gen_lea_v_seg in gen_pop_T0 would clobber the address of the memory operand. Instead use T0 since it is already available and will be overwritten immediately after. Signed-off-by: Paolo Bonzini Reviewed-by: Richard Henderson --- target/i386/tcg/translate.c | 34 ++++++++++++++++++++-------------- 1 file changed, 20 insertions(+), 14 deletions(-) diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 038151a8c3e..39b5752e780 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -628,17 +628,17 @@ static TCGv eip_cur_tl(DisasContext *s) } } =20 -/* Compute SEG:REG into A0. SEG is selected from the override segment +/* Compute SEG:REG into DEST. SEG is selected from the override segment (OVR_SEG) and the default segment (DEF_SEG). OVR_SEG may be -1 to indicate no override. */ -static void gen_lea_v_seg(DisasContext *s, MemOp aflag, TCGv a0, - int def_seg, int ovr_seg) +static void gen_lea_v_seg_dest(DisasContext *s, MemOp aflag, TCGv dest, TC= Gv a0, + int def_seg, int ovr_seg) { switch (aflag) { #ifdef TARGET_X86_64 case MO_64: if (ovr_seg < 0) { - tcg_gen_mov_tl(s->A0, a0); + tcg_gen_mov_tl(dest, a0); return; } break; @@ -649,14 +649,14 @@ static void gen_lea_v_seg(DisasContext *s, MemOp afla= g, TCGv a0, ovr_seg =3D def_seg; } if (ovr_seg < 0) { - tcg_gen_ext32u_tl(s->A0, a0); + tcg_gen_ext32u_tl(dest, a0); return; } break; case MO_16: /* 16 bit address */ - tcg_gen_ext16u_tl(s->A0, a0); - a0 =3D s->A0; + tcg_gen_ext16u_tl(dest, a0); + a0 =3D dest; if (ovr_seg < 0) { if (ADDSEG(s)) { ovr_seg =3D def_seg; @@ -673,17 +673,23 @@ static void gen_lea_v_seg(DisasContext *s, MemOp afla= g, TCGv a0, TCGv seg =3D cpu_seg_base[ovr_seg]; =20 if (aflag =3D=3D MO_64) { - tcg_gen_add_tl(s->A0, a0, seg); + tcg_gen_add_tl(dest, a0, seg); } else if (CODE64(s)) { - tcg_gen_ext32u_tl(s->A0, a0); - tcg_gen_add_tl(s->A0, s->A0, seg); + tcg_gen_ext32u_tl(dest, a0); + tcg_gen_add_tl(dest, dest, seg); } else { - tcg_gen_add_tl(s->A0, a0, seg); - tcg_gen_ext32u_tl(s->A0, s->A0); + tcg_gen_add_tl(dest, a0, seg); + tcg_gen_ext32u_tl(dest, dest); } } } =20 +static void gen_lea_v_seg(DisasContext *s, MemOp aflag, TCGv a0, + int def_seg, int ovr_seg) +{ + gen_lea_v_seg_dest(s, aflag, s->A0, a0, def_seg, ovr_seg); +} + static inline void gen_string_movl_A0_ESI(DisasContext *s) { gen_lea_v_seg(s, s->aflag, cpu_regs[R_ESI], R_DS, s->override); @@ -2590,8 +2596,8 @@ static MemOp gen_pop_T0(DisasContext *s) { MemOp d_ot =3D mo_pushpop(s, s->dflag); =20 - gen_lea_v_seg(s, mo_stacksize(s), cpu_regs[R_ESP], R_SS, -1); - gen_op_ld_v(s, d_ot, s->T0, s->A0); + gen_lea_v_seg_dest(s, mo_stacksize(s), s->T0, cpu_regs[R_ESP], R_SS, -= 1); + gen_op_ld_v(s, d_ot, s->T0, s->T0); =20 return d_ot; } --=20 2.41.0