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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=2607:f8b0:4864:20::42b; envelope-from=akihiko.odaki@daynix.com; helo=mail-pf1-x42b.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @daynix-com.20230601.gappssmtp.com) X-ZM-MESSAGEID: 1697254642409100002 Content-Type: text/plain; charset="utf-8" gdb_core_xml_file was assigned each time a CPU is instantiated before this change. Signed-off-by: Akihiko Odaki --- target/riscv/cpu.c | 5 +++++ target/riscv/tcg/tcg-cpu.c | 4 ---- 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index ac4a6c7eec..a811215150 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1575,6 +1575,11 @@ static void riscv_cpu_class_init(ObjectClass *c, voi= d *data) cc->get_pc =3D riscv_cpu_get_pc; cc->gdb_read_register =3D riscv_cpu_gdb_read_register; cc->gdb_write_register =3D riscv_cpu_gdb_write_register; +#ifdef TARGET_RISCV64 + cc->gdb_core_xml_file =3D "riscv-64bit-cpu.xml"; +#elif defined(TARGET_RISCV32) + cc->gdb_core_xml_file =3D "riscv-32bit-cpu.xml"; +#endif cc->gdb_num_core_regs =3D 33; cc->gdb_stop_before_watchpoint =3D true; cc->disas_set_info =3D riscv_cpu_disas_set_info; diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index e0cbc56320..626fb2acea 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -150,8 +150,6 @@ static void riscv_cpu_validate_misa_priv(CPURISCVState = *env, Error **errp) =20 static void riscv_cpu_validate_misa_mxl(RISCVCPU *cpu, Error **errp) { - RISCVCPUClass *mcc =3D RISCV_CPU_GET_CLASS(cpu); - CPUClass *cc =3D CPU_CLASS(mcc); CPURISCVState *env =3D &cpu->env; =20 /* Validate that MISA_MXL is set properly. */ @@ -159,11 +157,9 @@ static void riscv_cpu_validate_misa_mxl(RISCVCPU *cpu,= Error **errp) #ifdef TARGET_RISCV64 case MXL_RV64: case MXL_RV128: - cc->gdb_core_xml_file =3D "riscv-64bit-cpu.xml"; break; #elif defined(TARGET_RISCV32) case MXL_RV32: - cc->gdb_core_xml_file =3D "riscv-32bit-cpu.xml"; break; #endif default: --=20 2.42.0