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Fri, 13 Oct 2023 07:11:54 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Paolo Bonzini , Evgeny Iakovlev , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Gavin Shan , =?UTF-8?q?Alex=20Benn=C3=A9e?= , qemu-arm@nongnu.org, Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PATCH v3 3/10] hw/char/pl011: Split RX/TX path of pl011_reset_fifo() Date: Fri, 13 Oct 2023 16:11:24 +0200 Message-ID: <20231013141131.1531-4-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231013141131.1531-1-philmd@linaro.org> References: <20231013141131.1531-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::52c; envelope-from=philmd@linaro.org; helo=mail-ed1-x52c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1697206432285100005 To be able to reset the RX or TX FIFO separately, split pl011_reset_fifo() in two. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Richard Henderson --- hw/char/pl011.c | 19 ++++++++++++++----- 1 file changed, 14 insertions(+), 5 deletions(-) diff --git a/hw/char/pl011.c b/hw/char/pl011.c index 58edeb9ddb..1f07c7b021 100644 --- a/hw/char/pl011.c +++ b/hw/char/pl011.c @@ -132,14 +132,21 @@ static inline unsigned pl011_get_fifo_depth(PL011Stat= e *s) return pl011_is_fifo_enabled(s) ? PL011_FIFO_DEPTH : 1; } =20 -static inline void pl011_reset_fifo(PL011State *s) +static inline void pl011_reset_rx_fifo(PL011State *s) { s->read_count =3D 0; s->read_pos =3D 0; =20 /* Reset FIFO flags */ - s->flags &=3D ~(PL011_FLAG_RXFF | PL011_FLAG_TXFF); - s->flags |=3D PL011_FLAG_RXFE | PL011_FLAG_TXFE; + s->flags &=3D ~PL011_FLAG_RXFF; + s->flags |=3D PL011_FLAG_RXFE; +} + +static inline void pl011_reset_tx_fifo(PL011State *s) +{ + /* Reset FIFO flags */ + s->flags &=3D ~PL011_FLAG_TXFF; + s->flags |=3D PL011_FLAG_TXFE; } =20 static uint64_t pl011_read(void *opaque, hwaddr offset, @@ -289,7 +296,8 @@ static void pl011_write(void *opaque, hwaddr offset, case 11: /* UARTLCR_H */ /* Reset the FIFO state on FIFO enable or disable */ if ((s->lcr ^ value) & LCR_FEN) { - pl011_reset_fifo(s); + pl011_reset_rx_fifo(s); + pl011_reset_tx_fifo(s); } if ((s->lcr ^ value) & LCR_BRK) { int break_enable =3D value & LCR_BRK; @@ -506,7 +514,8 @@ static void pl011_reset(DeviceState *dev) s->ifl =3D 0x12; s->cr =3D 0x300; s->flags =3D 0; - pl011_reset_fifo(s); + pl011_reset_rx_fifo(s); + pl011_reset_tx_fifo(s); } =20 static void pl011_class_init(ObjectClass *oc, void *data) --=20 2.41.0