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[217.169.11.214]) by smtp.gmail.com with ESMTPSA id p8-20020adfce08000000b003271be8440csm20455185wrn.101.2023.10.13.04.01.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Oct 2023 04:01:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1697194885; x=1697799685; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=rzGngqylYHpKDCiaLpKrbx65UfqvHRS/0as6l/bM/+g=; b=cDch8EPd6VGrxuyuHK0ZgcLhFoNp87imtLNdmpXuw0ssFBoM0HaZz6rpA8vbwoZgGp Y5GtCfBAUv/IS3VLv9xmA0FB0DbTxnO/219isJkGcYSaMkzx036yDQOXq/qKRGKXqq24 C402+N4xCyXXeGWIwQUpJWEf7G9iFOKM5BvNxOu8OaJtjC4PMqrvkHStSsXWVrc1m9nd YNflevPaFg5ABdBXYYFfGjNnwVvO3xKUwaevwYB8ggZ7if7Tj75Vta12szKfPpnIIZns RJsHrCU14HXdmrSH5XAsy9oHJs+R1X0kjreHsSFc6hQZAsk9C0stRgytDOm9P7e5ue+k d99Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697194885; x=1697799685; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=rzGngqylYHpKDCiaLpKrbx65UfqvHRS/0as6l/bM/+g=; b=asIpX4SUqyyD+obxpHEzumF/OWePEH8vFrSTTLz+f6Nni05yTxkSQG4wjed2hZtuDl WJwc2cHyj9JfjbvgFAmetetuiWxr2Wrkf2Qf99apvKh2xVYR5we9+5LPHQ4uVSjQumwR 4J1ZIBm8H0LnZRaQCkoNQj4pMSyBAWtb5FHGLXUjeC01IrqicWwgoKDaKUYbME94U+CL 911PRjrvhXkz032H7wdSTxBQAJ6/biiPaWa3eFvpyFMIxczaORKDc7B532+EPZS2FgpP AIRYi73HTkOu7fF1b9elI3F04odZFJD9dvtlH1essVqgj107VAZUqeCSBFBtCMVc1tsA vj9Q== X-Gm-Message-State: AOJu0YyRz1PZ6ag0NJOf/VfmQe/VfW83E/cZg8m+dW5t5YrAfKS4eeJI Ks9lm0DE4XxJ+EEHf5VCy1pNFVaZC4+yvJVIy1Y= X-Google-Smtp-Source: AGHT+IGR4q1WmBFNVCN08rblp6GVFD57rbwqv0NURjqMvE9vDTug6EmIWzq1k5Z2wVIM6Tm6JmDLrA== X-Received: by 2002:adf:a41e:0:b0:32d:3e9d:fddf with SMTP id d30-20020adfa41e000000b0032d3e9dfddfmr8282332wra.50.1697194885402; Fri, 13 Oct 2023 04:01:25 -0700 (PDT) From: Rob Bradford To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, atishp@rivosinc.com, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, liweiwei@iscas.ac.cn, dbarboza@ventanamicro.com, zhiwei_liu@linux.alibaba.com, Rob Bradford Subject: [PATCH v3 1/6] target/riscv: Propagate error from PMU setup Date: Fri, 13 Oct 2023 11:54:43 +0100 Message-ID: <20231013110111.34619-2-rbradford@rivosinc.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231013110111.34619-1-rbradford@rivosinc.com> References: <20231013110111.34619-1-rbradford@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=rbradford@rivosinc.com; helo=mail-wr1-x42b.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @rivosinc-com.20230601.gappssmtp.com) X-ZM-MESSAGEID: 1697195004447100002 Content-Type: text/plain; charset="utf-8" More closely follow the QEMU style by returning an Error and propagating it there is an error relating to the PMU setup. Further simplify the function by removing the num_counters parameter as this is available from the passed in cpu pointer. Signed-off-by: Rob Bradford Reviewed-by: Alistair Francis Reviewed-by: LIU Zhiwei --- target/riscv/cpu.c | 8 +++++++- target/riscv/pmu.c | 19 +++++++++---------- target/riscv/pmu.h | 3 ++- 3 files changed, 18 insertions(+), 12 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index ac2b94b6a6..c9d8fc12fe 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1488,7 +1488,13 @@ static void riscv_cpu_realize_tcg(DeviceState *dev, = Error **errp) } =20 if (cpu->cfg.pmu_num) { - if (!riscv_pmu_init(cpu, cpu->cfg.pmu_num) && cpu->cfg.ext_sscofpm= f) { + riscv_pmu_init(cpu, &local_err); + if (local_err !=3D NULL) { + error_propagate(errp, local_err); + return; + } + + if (cpu->cfg.ext_sscofpmf) { cpu->pmu_timer =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, riscv_pmu_timer_cb, cpu); } diff --git a/target/riscv/pmu.c b/target/riscv/pmu.c index 36f6307d28..13801ccb78 100644 --- a/target/riscv/pmu.c +++ b/target/riscv/pmu.c @@ -434,22 +434,21 @@ int riscv_pmu_setup_timer(CPURISCVState *env, uint64_= t value, uint32_t ctr_idx) } =20 =20 -int riscv_pmu_init(RISCVCPU *cpu, int num_counters) +void riscv_pmu_init(RISCVCPU *cpu, Error **errp) { - if (num_counters > (RV_MAX_MHPMCOUNTERS - 3)) { - return -1; + uint8_t pmu_num =3D cpu->cfg.pmu_num; + + if (pmu_num > (RV_MAX_MHPMCOUNTERS - 3)) { + error_setg(errp, "Number of counters exceeds maximum available"); + return; } =20 cpu->pmu_event_ctr_map =3D g_hash_table_new(g_direct_hash, g_direct_eq= ual); if (!cpu->pmu_event_ctr_map) { - /* PMU support can not be enabled */ - qemu_log_mask(LOG_UNIMP, "PMU events can't be supported\n"); - cpu->cfg.pmu_num =3D 0; - return -1; + error_setg(errp, "Unable to allocate PMU event hash table"); + return; } =20 /* Create a bitmask of available programmable counters */ - cpu->pmu_avail_ctrs =3D MAKE_32BIT_MASK(3, num_counters); - - return 0; + cpu->pmu_avail_ctrs =3D MAKE_32BIT_MASK(3, pmu_num); } diff --git a/target/riscv/pmu.h b/target/riscv/pmu.h index 2bfb71ba87..88e0713296 100644 --- a/target/riscv/pmu.h +++ b/target/riscv/pmu.h @@ -17,13 +17,14 @@ */ =20 #include "cpu.h" +#include "qapi/error.h" =20 bool riscv_pmu_ctr_monitor_instructions(CPURISCVState *env, uint32_t target_ctr); bool riscv_pmu_ctr_monitor_cycles(CPURISCVState *env, uint32_t target_ctr); void riscv_pmu_timer_cb(void *priv); -int riscv_pmu_init(RISCVCPU *cpu, int num_counters); +void riscv_pmu_init(RISCVCPU *cpu, Error **errp); int riscv_pmu_update_event_map(CPURISCVState *env, uint64_t value, uint32_t ctr_idx); int riscv_pmu_incr_ctr(RISCVCPU *cpu, enum riscv_pmu_event_idx event_idx); --=20 2.41.0