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[81.111.69.236]) by smtp.gmail.com with ESMTPSA id m12-20020a056000024c00b0032d88e370basm3803122wrz.34.2023.10.12.03.01.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Oct 2023 03:01:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1697104872; x=1697709672; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=tshq197do4wem94F6Ogz/4zKOLZ/viu1Un/xTiiiD6o=; b=VdrJu4h/GA0MuwwrTyPbRcoGRgb8yFKBsQz8JTzXrrQYqiVUzBFjnA56FdoPQ0O0wv mYZ1X66qCMojSMnaK9xPxpOhPt1Y+TAryBhGhGkhndSVheydJhPBOculbp+l0dgK8Rs/ YIFeoIXu2P4ZvHfWMnU3K+2zS7zxrFdmq2eCPoZMRfhSF9zXBtCc8KT42aj4RERxyAnP JZxeu4Ry+3Upj7mMAKox+mN9Yue+1wSeAvErIrOXGTFO+6tSeT0BSw8FNQfIP7Y0zvZP btIIG/COShrsfWsGd5zzJa9dVJw7VQeJi3ikPOJWfR2HJCOpKDZGytOb9YNYTaUWlUuU 3msg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697104872; x=1697709672; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=tshq197do4wem94F6Ogz/4zKOLZ/viu1Un/xTiiiD6o=; b=JGIbU6r7nD68lqw3dQhUfPddz50ZOdcwvmteBedhi8uK+7aCyE5vFhRDST+HU6nZFi yuE7T30ecJVWk+QoPYQF95AvnSRI1NwRacNcVGRbRB6/hL1l6F5RVjA+DSKs6NGgf58L P/XZ+AO3Zi0as5BF2dlIr505u7daNlSen2V7lFYm/be+ksH1T0ysapgpRgzH5FmMMCCP 83+ZAK3jbBlr3puY8ae6kmDUsRmR9CsEXKb4695gIiaALbq7S3Blj/DTlKyZU8nUFApy 4Cbb04vcpZnq9uv9Iw1/+FxCQSJ+17GmXUx4tlijTzRj2gb/SlLlHexYVdivibEjJSgi 7vZA== X-Gm-Message-State: AOJu0Yz5Nb6SmJCWzcuuUjNy+CohIr/M/HO7dLX86idFfMJOjvGGc5kC EX6C/CWaFWcuawwnQiDJdjQiOA== X-Google-Smtp-Source: AGHT+IGZXimiyojbuUxNuuk1VGkDRJdLFXsxDGdJdaB+KvWKkkv0gSbTvGc/MshSE5uuLhksnKyeMA== X-Received: by 2002:a5d:490b:0:b0:31f:fe07:fde7 with SMTP id x11-20020a5d490b000000b0031ffe07fde7mr20606083wrq.1.1697104872571; Thu, 12 Oct 2023 03:01:12 -0700 (PDT) From: Rajnesh Kanwal To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, liweiwei@iscas.ac.cn, dbarboza@ventanamicro.com, zhiwei_liu@linux.alibaba.com, atishp@rivosinc.com, apatel@ventanamicro.com, rkanwal@rivosinc.com Subject: [PATCH v4 1/6] target/riscv: Without H-mode mask all HS mode inturrupts in mie. Date: Thu, 12 Oct 2023 11:00:58 +0100 Message-Id: <20231012100103.28612-2-rkanwal@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231012100103.28612-1-rkanwal@rivosinc.com> References: <20231012100103.28612-1-rkanwal@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=rkanwal@rivosinc.com; helo=mail-wr1-x42d.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @rivosinc-com.20230601.gappssmtp.com) X-ZM-MESSAGEID: 1697104925167100006 Content-Type: text/plain; charset="utf-8" Signed-off-by: Rajnesh Kanwal Reviewed-by: Alistair Francis --- target/riscv/csr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 4b4ab56c40..d99d954ff3 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1525,7 +1525,7 @@ static RISCVException rmw_mie64(CPURISCVState *env, i= nt csrno, env->mie =3D (env->mie & ~mask) | (new_val & mask); =20 if (!riscv_has_ext(env, RVH)) { - env->mie &=3D ~((uint64_t)MIP_SGEIP); + env->mie &=3D ~((uint64_t)HS_MODE_INTERRUPTS); } =20 return RISCV_EXCP_NONE; --=20 2.34.1 From nobody Tue Feb 10 16:25:20 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1697104923; cv=none; d=zohomail.com; s=zohoarc; b=I3ObZ+ijbyXa/TmFv7PZZ6ihKZ+YR1tkKM1iUKDS2yQMd2ZJabV0iiuThRC2TYA+g4tzCsoxrfKmc5tV2dCUX29mIR3XF3NKUw0jo+efYAyLAdX9Mit6hhFRZNa+eSPakEpFUKkco1tlf475whqgV67WTQXds06p3cQ8qkfPQZw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1697104923; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=9XGMvvJZUGfMnQ/1RecN9n7QRTY4rets8V/xDm2EU20=; b=TQ4uDIwWb1vzgyV7twced3S7AtnYh26SHTi8pVGviUf0sjfdwGoERWp3SzpzVYiac81CdwAqeGB/bBzEsnMhpZr8Lwan3oq1ouIlD6MZYfALwvzV6m5veL9sSjpEj4USVSaAuL+tAIhJLGkbShS6UTi+/zTY5nIzugT44lsh48k= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1697104923106309.2169171099297; Thu, 12 Oct 2023 03:02:03 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qqsVO-0007Bc-TQ; Thu, 12 Oct 2023 06:01:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qqsVJ-000780-EJ for qemu-devel@nongnu.org; Thu, 12 Oct 2023 06:01:20 -0400 Received: from mail-wr1-x42f.google.com ([2a00:1450:4864:20::42f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qqsVH-0006yX-JK for qemu-devel@nongnu.org; Thu, 12 Oct 2023 06:01:17 -0400 Received: by mail-wr1-x42f.google.com with SMTP id ffacd0b85a97d-32483535e51so755625f8f.0 for ; Thu, 12 Oct 2023 03:01:15 -0700 (PDT) Received: from localhost.localdomain (cpc91760-watf12-2-0-cust235.15-2.cable.virginm.net. [81.111.69.236]) by smtp.gmail.com with ESMTPSA id m12-20020a056000024c00b0032d88e370basm3803122wrz.34.2023.10.12.03.01.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Oct 2023 03:01:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1697104874; x=1697709674; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=9XGMvvJZUGfMnQ/1RecN9n7QRTY4rets8V/xDm2EU20=; b=Juj5EbWp8nPuSQeTxDP6atjL9e6BnIGYosHgvD5mw+60+bbVLOit5s2gWpQGsr4q6j M04ggvzTLZFuP0GvsKsJ76wan0JpoElcFUOz8C5DdV7x0EvP5HQ47bhZTV0DRd8wjl8V xjNtz1OVHEvmgk2+P7X4HifI7qR+4GajeazMBFoARqnZYNBXLOx8Wd7s2ztXi9J9UQP3 Co0XYMN9MSwhv4Vf1h3Cq8rXYudyVWO+Zxgk9RNY/EuDobit4dwaY6JTtPOOTzSJaJLC tyR/72rXMlzkIlkbeJEvdWYZxkzoEdRTKdiqgRDX5HfIU+B2I5vHA0g0c2nhQwaqZTdX Nodg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697104874; x=1697709674; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=9XGMvvJZUGfMnQ/1RecN9n7QRTY4rets8V/xDm2EU20=; b=OGkcwh3Om2YingfsDZFCM2MU91F89TOlNZdUvpjziF/51MD0B+vFcbC2ti828r3EbB 4tqDovWkSm06aFXWUdF7H/P35vKQhOMCPBCzMiHxAz6sbSax3b1NHdVvqjoRm3fWUgWB 3Qqn4f2okm/NYIczjEvJ513hj0LRhdujlWWPwjWRKR+jd4SxBQCdQurwxsSNeit9RU6/ ofF4Gzl9Sn0f/PVXKEubZU6C7lo9jguo5w2fya26ZEiA6Y7gYqY0K7XJc1gO+n7OSJzx MJeZv8akhW08M839u9D0MfWI+szYUXqnSs86U0S/AIm63mIylne80lUAnQM4WO/uZgHp 6jrA== X-Gm-Message-State: AOJu0YyGL7v78GuIuIbLHHckFyy155S1S6xZyy2VupWJK0soH659De+k /ONs1bIVjlgmLXFVXbyVv171DQ== X-Google-Smtp-Source: AGHT+IHwKcwdmJri4A7SR9ovdcCDDHw2MjnX2rBdgbYCjJgsGomg6Wg0FdfDGEoB3/JqsqOPMwiOjQ== X-Received: by 2002:a5d:4f85:0:b0:31a:ea9a:b602 with SMTP id d5-20020a5d4f85000000b0031aea9ab602mr23493717wru.1.1697104873739; Thu, 12 Oct 2023 03:01:13 -0700 (PDT) From: Rajnesh Kanwal To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, liweiwei@iscas.ac.cn, dbarboza@ventanamicro.com, zhiwei_liu@linux.alibaba.com, atishp@rivosinc.com, apatel@ventanamicro.com, rkanwal@rivosinc.com Subject: [PATCH v4 2/6] target/riscv: Check for async flag in case of RISCV_EXCP_SEMIHOST. Date: Thu, 12 Oct 2023 11:00:59 +0100 Message-Id: <20231012100103.28612-3-rkanwal@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231012100103.28612-1-rkanwal@rivosinc.com> References: <20231012100103.28612-1-rkanwal@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=rkanwal@rivosinc.com; helo=mail-wr1-x42f.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @rivosinc-com.20230601.gappssmtp.com) X-ZM-MESSAGEID: 1697104925147100005 Content-Type: text/plain; charset="utf-8" RISCV_EXCP_SEMIHOST is set to 0x10, which can be a local interrupt id as well. This change moves RISCV_EXCP_SEMIHOST to switch case so that async flag check is performed before invoking semihosting logic. Signed-off-by: Rajnesh Kanwal Reviewed-by: Alistair Francis --- target/riscv/cpu_helper.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 8c28241c18..aaeb1d0d5c 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -1605,15 +1605,13 @@ void riscv_cpu_do_interrupt(CPUState *cs) target_ulong htval =3D 0; target_ulong mtval2 =3D 0; =20 - if (cause =3D=3D RISCV_EXCP_SEMIHOST) { - do_common_semihosting(cs); - env->pc +=3D 4; - return; - } - if (!async) { /* set tval to badaddr for traps with address information */ switch (cause) { + case RISCV_EXCP_SEMIHOST: + do_common_semihosting(cs); + env->pc +=3D 4; + return; case RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT: case RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT: case RISCV_EXCP_LOAD_ADDR_MIS: --=20 2.34.1 From nobody Tue Feb 10 16:25:20 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1697104976; cv=none; d=zohomail.com; s=zohoarc; b=JWxVDQ9eGNFb34dcZ5kLlSCb/PkzGvrpBgRIqQjQAFcqwips8SMo82PirOr5vP9FQsgisAolz2+kDdhj0eYHhw7cns7Twp5NITtbYHAp1A2TeL2uXDo5WiJc4ew91gqMn8hrz2ROYcL3JUP3LMyRFxAyAvt6P2HSr3jKdmvpWts= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1697104976; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=xCYl2ITD4wBOSdR+ouSLn64FfrgWlxT7ZNZhf+YF/cY=; b=jW9ROQzBv8/v0Ne7biY4xMLVQYevcrFSsTsnMeoOI/C3RuNIPvUGaB1pTeVkBOc2lEs/5Qs7Jnsqeo3QiMgYRWBVW1CqUp18E2FzKCrWHiuPIZ2DAO/LLYjoNcpTkNeoulCIJd8tyhHZRJjbH4AvdZ4UAfLoN7vAIB+63CuJTq0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1697104976212672.9765434132254; Thu, 12 Oct 2023 03:02:56 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qqsVO-00079v-3J; Thu, 12 Oct 2023 06:01:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qqsVK-000789-Tr for qemu-devel@nongnu.org; Thu, 12 Oct 2023 06:01:20 -0400 Received: from mail-wr1-x434.google.com ([2a00:1450:4864:20::434]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qqsVI-0006z1-Pl for qemu-devel@nongnu.org; Thu, 12 Oct 2023 06:01:18 -0400 Received: by mail-wr1-x434.google.com with SMTP id ffacd0b85a97d-3296b49c546so636702f8f.3 for ; Thu, 12 Oct 2023 03:01:16 -0700 (PDT) Received: from localhost.localdomain (cpc91760-watf12-2-0-cust235.15-2.cable.virginm.net. [81.111.69.236]) by smtp.gmail.com with ESMTPSA id m12-20020a056000024c00b0032d88e370basm3803122wrz.34.2023.10.12.03.01.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Oct 2023 03:01:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1697104875; x=1697709675; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=xCYl2ITD4wBOSdR+ouSLn64FfrgWlxT7ZNZhf+YF/cY=; b=woNO6CBhHoLe0p/NTlTHcO16ZDJBrpM9MScLOjzmOhBljQXeHEzEqijeDVbT8OazSF 4PS+9RVVSWUWVAZ6Mp5vUtsfS68LykNmG49MznLt4KVBiVSocqUHzvqb4H4Jx/ZMRdx9 RMM42xD2u0xQ1rqVRj8mQ6xs/GcDxpyMgqipyBN58Pu5MpwYcYAW8hr7yNoZWm89LJcF CtZY+fI3a/rk2YKcE+xr1unhyLhLYEqm0EvHRv9u5Hpuq8KbR6PILmwHneY0c9UzJd0T b8bbmmecSIrX8K+GO7N4zeATkXNlaTLfKISegSxOxxS02CXTKgTNZaW61Sk1Z4XKgwkp gm4A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697104875; x=1697709675; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=xCYl2ITD4wBOSdR+ouSLn64FfrgWlxT7ZNZhf+YF/cY=; b=ocLpsmYH+PMwiodcA1UnV64n3DAkaohJAdu0kNVsEWR+ZqpaL7zw2n8QPK+GBnjr4K H/KL/4ALg5bwB0ITIuNTg/VG7NuX2gYwOeokmsOee4o/PfX18OB4/5MTn33LYYqCJ+sn 3jfqvCwrfEttjOEAeUlbXZk4272tZgB7/oKtPgXMzZAfPj1vr2WER7uDjLXAmOctLMiS 0NslJ0Gf4T+hDPFSYowUg5iA7Xwkg2auDhwrw8a39CELflEjkwPDavNLty+r/hbt/cSU pla011dMByJtXZea7fhrRyoNS68M4BNHImjbYbPHRCZDfp7FnS5wI4EKmGKLxauATm4m k7Pw== X-Gm-Message-State: AOJu0YxFUeBR+a8wkg69T/o4jp3hmLE0hk+rc3Z4NaeESzpxr5lNtBlZ I5eWqUnNqxfEErZ+WFIlO8tAMA== X-Google-Smtp-Source: AGHT+IFfI9o1IKSKwDw2npe/u9/rNys0e/h6DSPXioXPAT/NHZDT34YNbrPNHHxIx2KhBPU7BJbj1g== X-Received: by 2002:a5d:58ca:0:b0:31f:9b4f:1910 with SMTP id o10-20020a5d58ca000000b0031f9b4f1910mr20831327wrf.63.1697104874892; Thu, 12 Oct 2023 03:01:14 -0700 (PDT) From: Rajnesh Kanwal To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, liweiwei@iscas.ac.cn, dbarboza@ventanamicro.com, zhiwei_liu@linux.alibaba.com, atishp@rivosinc.com, apatel@ventanamicro.com, rkanwal@rivosinc.com Subject: [PATCH v4 3/6] target/riscv: Set VS* bits to one in mideleg when H-Ext is enabled Date: Thu, 12 Oct 2023 11:01:00 +0100 Message-Id: <20231012100103.28612-4-rkanwal@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231012100103.28612-1-rkanwal@rivosinc.com> References: <20231012100103.28612-1-rkanwal@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=rkanwal@rivosinc.com; helo=mail-wr1-x434.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @rivosinc-com.20230601.gappssmtp.com) X-ZM-MESSAGEID: 1697104978517100001 Content-Type: text/plain; charset="utf-8" With H-Ext supported, VS bits are all hardwired to one in MIDELEG denoting always delegated interrupts. This is being done in rmw_mideleg but given mideleg is used in other places when routing interrupts this change initializes it in riscv_cpu_realize to be on the safe side. Signed-off-by: Rajnesh Kanwal Reviewed-by: Alistair Francis --- target/riscv/tcg/tcg-cpu.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index a28918ab30..34e034b9f3 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -618,7 +618,12 @@ static bool tcg_cpu_realize(CPUState *cs, Error **errp) cpu->pmu_timer =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, riscv_pmu_timer_cb, cpu); } - } + } + + /* With H-Ext, VSSIP, VSTIP, VSEIP and SGEIP are hardwired to one. */ + if (riscv_has_ext(env, RVH)) { + env->mideleg =3D MIP_VSSIP | MIP_VSTIP | MIP_VSEIP | MIP_SGEIP; + } #endif =20 return true; --=20 2.34.1 From nobody Tue Feb 10 16:25:20 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1697105009; cv=none; d=zohomail.com; s=zohoarc; b=Bp7vZ2yfQmvNe4U76jJ09HMzh6gdeSI+pkf9MSs/FSn46gHV87LhiG1KAXATOgPAApDrKIQBLOSD4Isr1Y70+a9xWg87DXiv1s1uscgUifpDrKOWP4sRcYTXU+qbwM0KePLzRtleMTqaHUeaxU5alZfnJzKxG6IFRid89Zh9JpM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1697105009; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=+SYRUUfZD0yW8fyiOdJqWLzmAtXsCBoAuBwPooPofNs=; b=is4vlgqS1e/I2S8bbfQ/fQusVTEZVYF2VYPbxlfVg/1PF2F8PnzS+P7SPeP1WiNEvMrK6hAp/yRbPZO4QIcLMpBC7NPdJmvhLvj4o0AKurqW0CM6hMGzvKt3oOGMyWfxz7GH/mayY9/77ejuo3E5HQx3B/JahlLoq076UsRYU1c= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1697105009043455.3846770071008; Thu, 12 Oct 2023 03:03:29 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qqsVQ-0007CI-Jq; Thu, 12 Oct 2023 06:01:24 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qqsVM-00078I-7J for qemu-devel@nongnu.org; Thu, 12 Oct 2023 06:01:20 -0400 Received: from mail-wm1-x332.google.com ([2a00:1450:4864:20::332]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qqsVJ-0006zk-Fi for qemu-devel@nongnu.org; Thu, 12 Oct 2023 06:01:19 -0400 Received: by mail-wm1-x332.google.com with SMTP id 5b1f17b1804b1-4060b623e64so4516805e9.0 for ; Thu, 12 Oct 2023 03:01:17 -0700 (PDT) Received: from localhost.localdomain (cpc91760-watf12-2-0-cust235.15-2.cable.virginm.net. [81.111.69.236]) by smtp.gmail.com with ESMTPSA id m12-20020a056000024c00b0032d88e370basm3803122wrz.34.2023.10.12.03.01.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Oct 2023 03:01:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1697104876; x=1697709676; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=+SYRUUfZD0yW8fyiOdJqWLzmAtXsCBoAuBwPooPofNs=; b=tlf1Bb9V685xA20BRANylS0DwOOYw4XbqgUe1d2kSKg0azDsDtF9A78eGn5FNeyZYh yVHUFWawZtqRgaI51sTB9UpD4NrpykRFvRpA7CamMJ363byKYsXtHS//l4nljHuHWbMD vpkgkXcjneXaLUtomky6lvf6CCbgfyrbQeM57i0xwqVff2mTSIaF/ZQLwWwtp3uTj/wH VqwCdn3gblqBy9OkauR2pUO+2QD3D5o7cf/NI0xH6Fw8NuwDmQRKkSR0Vsj/5vBzoUg0 1+HxAqJvSM0jBUkkFKyH4wpul1JVqHd6PWqRfkTFb1LTcEVo079JuXDLLKZBxV+w8xWe 5HHg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697104876; x=1697709676; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+SYRUUfZD0yW8fyiOdJqWLzmAtXsCBoAuBwPooPofNs=; b=w3e8CY4UVHE0DOZY8SN4/24OP7Y5vQXqfrnBf8fh9Owyz7OQg7AZmAJY0GIS/7A5m8 c+6Dj3+DZd/rEjJ5oc1OMmUqKYNFeQojBHaTbzzS4tnAZFOS5r9i09I/UVPEuBDLHX4b XUcqNd5tslwTrQU8lzmX4VYuwAnVFbtaBO8Tr21YnwfM5u39H/ewMJ0x4vkgIlogd9Fa gXWkoWg46sHD8hSqGFkETSjMp3eWehyQzR/YMqIm6n+TkUvjisNf4p2JkLNWI3kAN188 +y3yZ6sPGIDRJ/liLJ0VcSX9HanqyTxk+uZogG1LXA7JxyHKGVzHp4jVaPcXYdoG0sI2 DBZQ== X-Gm-Message-State: AOJu0YxOKJl6zGX+RCxeMGeSuXnPubihWo5vkvl1PXpCm0AbL0tpOG/F TU3f9y80o352Q5+E5s+qaE/HRw== X-Google-Smtp-Source: AGHT+IF7M2GKw9BeeMCDGoF2r5Kuoy40bCiRiPWJYXm3PIf5suV26OfwYAjsD9Ya2AAQdJfqCKfEZw== X-Received: by 2002:a05:600c:3657:b0:406:44fc:65c9 with SMTP id y23-20020a05600c365700b0040644fc65c9mr19138765wmq.8.1697104876023; Thu, 12 Oct 2023 03:01:16 -0700 (PDT) From: Rajnesh Kanwal To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, liweiwei@iscas.ac.cn, dbarboza@ventanamicro.com, zhiwei_liu@linux.alibaba.com, atishp@rivosinc.com, apatel@ventanamicro.com, rkanwal@rivosinc.com Subject: [PATCH v4 4/6] target/riscv: Split interrupt logic from riscv_cpu_update_mip. Date: Thu, 12 Oct 2023 11:01:01 +0100 Message-Id: <20231012100103.28612-5-rkanwal@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231012100103.28612-1-rkanwal@rivosinc.com> References: <20231012100103.28612-1-rkanwal@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=rkanwal@rivosinc.com; helo=mail-wm1-x332.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @rivosinc-com.20230601.gappssmtp.com) X-ZM-MESSAGEID: 1697105010600100001 Content-Type: text/plain; charset="utf-8" This is to allow virtual interrupts to be inserted into S and VS modes. Given virtual interrupts will be maintained in separate mvip and hvip CSRs, riscv_cpu_update_mip will no longer be in the path and interrupts need to be triggered for these cases from rmw_hvip64 and rmw_mvip64 functions. Signed-off-by: Rajnesh Kanwal Reviewed-by: Alistair Francis --- target/riscv/cpu.h | 1 + target/riscv/cpu_helper.c | 25 ++++++++++++++++++------- 2 files changed, 19 insertions(+), 7 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index f8ffa5ee38..6fe32e6b38 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -463,6 +463,7 @@ void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env); int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts); uint64_t riscv_cpu_update_mip(CPURISCVState *env, uint64_t mask, uint64_t value); +void riscv_cpu_interrupt(CPURISCVState *env); #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value = */ void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void *), void *arg); diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index aaeb1d0d5c..581b8c6380 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -620,11 +620,12 @@ int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_= t interrupts) } } =20 -uint64_t riscv_cpu_update_mip(CPURISCVState *env, uint64_t mask, - uint64_t value) +void riscv_cpu_interrupt(CPURISCVState *env) { + uint64_t gein, vsgein =3D 0, vstip =3D 0; CPUState *cs =3D env_cpu(env); - uint64_t gein, vsgein =3D 0, vstip =3D 0, old =3D env->mip; + + QEMU_IOTHREAD_LOCK_GUARD(); =20 if (env->virt_enabled) { gein =3D get_field(env->hstatus, HSTATUS_VGEIN); @@ -633,15 +634,25 @@ uint64_t riscv_cpu_update_mip(CPURISCVState *env, uin= t64_t mask, =20 vstip =3D env->vstime_irq ? MIP_VSTIP : 0; =20 - QEMU_IOTHREAD_LOCK_GUARD(); - - env->mip =3D (env->mip & ~mask) | (value & mask); - if (env->mip | vsgein | vstip) { cpu_interrupt(cs, CPU_INTERRUPT_HARD); } else { cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); } +} + +uint64_t riscv_cpu_update_mip(CPURISCVState *env, uint64_t mask, uint64_t = value) +{ + uint64_t old =3D env->mip; + + /* No need to update mip for VSTIP */ + mask =3D ((mask =3D=3D MIP_VSTIP) && env->vstime_irq) ? 0 : mask; + + QEMU_IOTHREAD_LOCK_GUARD(); + + env->mip =3D (env->mip & ~mask) | (value & mask); + + riscv_cpu_interrupt(env); =20 return old; } --=20 2.34.1 From nobody Tue Feb 10 16:25:20 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1697104984; cv=none; d=zohomail.com; s=zohoarc; b=gqxCx2VAGpyjoeuKZ4wcFI7rNjkvYNQRmybObr9I/YJ4H+p1fJySo2WcaKzQjLaEZmFHah6UGS1PLlcKy4/QJPF8pBLjccbKYz7VgrrkZNzZQuupLXzzPnJTAHAjLSfV3buvbayXbxBHSJXh1+vxKE03CmmhdMBI6FIVgRkVOqk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1697104984; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=5w9+f4ErNHtmd44BWdyY/ya4296m20wEz5uowJRL+kM=; b=Drb2W0BgYrswg9DFYOGOfxMBS9EAjwTIxfWgIZkBgw+jtJq46l6rvnO1CqtMQxAOY56Ly3Le7H7q5qrLEGpvGPuwhE9bCZMRscyu5BQCKMQxeDOx59OoKFAOU530yJhI5Y1bkN4Jtept2w5PCL5f066DzICJgceDeVvTo7sJqdE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1697104984540586.1629316617089; Thu, 12 Oct 2023 03:03:04 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qqsVQ-0007CC-0f; Thu, 12 Oct 2023 06:01:24 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qqsVO-0007An-EI for qemu-devel@nongnu.org; Thu, 12 Oct 2023 06:01:22 -0400 Received: from mail-wm1-x342.google.com ([2a00:1450:4864:20::342]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qqsVL-00070T-0S for qemu-devel@nongnu.org; Thu, 12 Oct 2023 06:01:22 -0400 Received: by mail-wm1-x342.google.com with SMTP id 5b1f17b1804b1-405417465aaso8571625e9.1 for ; Thu, 12 Oct 2023 03:01:18 -0700 (PDT) Received: from localhost.localdomain (cpc91760-watf12-2-0-cust235.15-2.cable.virginm.net. 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Date: Thu, 12 Oct 2023 11:01:02 +0100 Message-Id: <20231012100103.28612-6-rkanwal@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231012100103.28612-1-rkanwal@rivosinc.com> References: <20231012100103.28612-1-rkanwal@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::342; envelope-from=rkanwal@rivosinc.com; helo=mail-wm1-x342.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @rivosinc-com.20230601.gappssmtp.com) X-ZM-MESSAGEID: 1697104986697100003 Content-Type: text/plain; charset="utf-8" This change adds support for inserting virtual interrupts from M-mode into S-mode using mvien and mvip csrs. IRQ filtering is a use case of this change, i-e M-mode can stop delegating an interrupt to S-mode and instead enable it in MIE and receive those interrupts in M-mode and then selectively inject the interrupt using mvien and mvip. Also, the spec doesn't mandate the interrupt to be actually supported in hardware. Which allows M-mode to assert virtual interrupts to S-mode that have no connection to any real interrupt events. This is defined as part of the AIA specification [0], "5.3 Interrupt filtering and virtual interrupts for supervisor level". [0]: https://github.com/riscv/riscv-aia/releases/download/1.0-RC4/riscv-int= errupts-1.0-RC4.pdf Signed-off-by: Rajnesh Kanwal Reviewed-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 3 +- target/riscv/cpu.h | 8 ++ target/riscv/cpu_bits.h | 6 + target/riscv/cpu_helper.c | 26 +++- target/riscv/csr.c | 279 ++++++++++++++++++++++++++++++++++---- target/riscv/machine.c | 3 + 6 files changed, 289 insertions(+), 36 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index ac4a6c7eec..6546634f9d 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -813,7 +813,8 @@ static bool riscv_cpu_has_work(CPUState *cs) * Definition of the WFI instruction requires it to ignore the privile= ge * mode and delegation registers, but respect individual enables */ - return riscv_cpu_all_pending(env) !=3D 0; + return riscv_cpu_all_pending(env) !=3D 0 || + riscv_cpu_sirq_pending(env) !=3D RISCV_EXCP_NONE; #else return true; #endif diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 6fe32e6b38..30f9481f45 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -202,6 +202,12 @@ struct CPUArchState { uint64_t mie; uint64_t mideleg; =20 + /* + * When mideleg[i]=3D0 and mvien[i]=3D1, sie[i] is no more + * alias of mie[i] and needs to be maintained separatly. + */ + uint64_t sie; + target_ulong satp; /* since: priv-1.10.0 */ target_ulong stval; target_ulong medeleg; @@ -222,6 +228,8 @@ struct CPUArchState { /* AIA CSRs */ target_ulong miselect; target_ulong siselect; + uint64_t mvien; + uint64_t mvip; =20 /* Hypervisor CSRs */ target_ulong hstatus; diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 3d6ffaabc7..ebd7917d49 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -735,6 +735,12 @@ typedef enum RISCVException { #define MIE_SSIE (1 << IRQ_S_SOFT) #define MIE_USIE (1 << IRQ_U_SOFT) =20 +/* Machine constants */ +#define M_MODE_INTERRUPTS ((uint64_t)(MIP_MSIP | MIP_MTIP | MIP_MEIP)) +#define S_MODE_INTERRUPTS ((uint64_t)(MIP_SSIP | MIP_STIP | MIP_SEIP)) +#define VS_MODE_INTERRUPTS ((uint64_t)(MIP_VSSIP | MIP_VSTIP | MIP_VSEIP)) +#define HS_MODE_INTERRUPTS ((uint64_t)(MIP_SGEIP | VS_MODE_INTERRUPTS)) + /* General PointerMasking CSR bits */ #define PM_ENABLE 0x00000001ULL #define PM_CURRENT 0x00000002ULL diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 581b8c6380..b36161708a 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -376,6 +376,10 @@ static int riscv_cpu_pending_to_irq(CPURISCVState *env, return best_irq; } =20 +/* + * Doesn't report interrupts inserted using mvip from M-mode firmware. Tho= se + * are returned in riscv_cpu_sirq_pending(). + */ uint64_t riscv_cpu_all_pending(CPURISCVState *env) { uint32_t gein =3D get_field(env->hstatus, HSTATUS_VGEIN); @@ -398,9 +402,10 @@ int riscv_cpu_sirq_pending(CPURISCVState *env) { uint64_t irqs =3D riscv_cpu_all_pending(env) & env->mideleg & ~(MIP_VSSIP | MIP_VSTIP | MIP_VSEIP); + uint64_t irqs_f =3D env->mvip & env->mvien & ~env->mideleg & env->sie; =20 return riscv_cpu_pending_to_irq(env, IRQ_S_EXT, IPRIO_DEFAULT_S, - irqs, env->siprio); + irqs | irqs_f, env->siprio); } =20 int riscv_cpu_vsirq_pending(CPURISCVState *env) @@ -414,8 +419,8 @@ int riscv_cpu_vsirq_pending(CPURISCVState *env) =20 static int riscv_cpu_local_irq_pending(CPURISCVState *env) { + uint64_t irqs, pending, mie, hsie, vsie, irqs_f; int virq; - uint64_t irqs, pending, mie, hsie, vsie; =20 /* Determine interrupt enable state of all privilege modes */ if (env->virt_enabled) { @@ -441,8 +446,11 @@ static int riscv_cpu_local_irq_pending(CPURISCVState *= env) irqs, env->miprio); } =20 + /* Check for virtual S-mode interrupts. */ + irqs_f =3D env->mvip & (env->mvien & ~env->mideleg) & env->sie; + /* Check HS-mode interrupts */ - irqs =3D pending & env->mideleg & ~env->hideleg & -hsie; + irqs =3D ((pending & env->mideleg & ~env->hideleg) | irqs_f) & -hsie; if (irqs) { return riscv_cpu_pending_to_irq(env, IRQ_S_EXT, IPRIO_DEFAULT_S, irqs, env->siprio); @@ -622,7 +630,7 @@ int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t = interrupts) =20 void riscv_cpu_interrupt(CPURISCVState *env) { - uint64_t gein, vsgein =3D 0, vstip =3D 0; + uint64_t gein, vsgein =3D 0, vstip =3D 0, irqf =3D 0; CPUState *cs =3D env_cpu(env); =20 QEMU_IOTHREAD_LOCK_GUARD(); @@ -630,11 +638,13 @@ void riscv_cpu_interrupt(CPURISCVState *env) if (env->virt_enabled) { gein =3D get_field(env->hstatus, HSTATUS_VGEIN); vsgein =3D (env->hgeip & (1ULL << gein)) ? MIP_VSEIP : 0; + } else { + irqf =3D env->mvien & env->mvip & env->sie; } =20 vstip =3D env->vstime_irq ? MIP_VSTIP : 0; =20 - if (env->mip | vsgein | vstip) { + if (env->mip | vsgein | vstip | irqf) { cpu_interrupt(cs, CPU_INTERRUPT_HARD); } else { cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); @@ -1611,6 +1621,8 @@ void riscv_cpu_do_interrupt(CPUState *cs) bool async =3D !!(cs->exception_index & RISCV_EXCP_INT_FLAG); target_ulong cause =3D cs->exception_index & RISCV_EXCP_INT_MASK; uint64_t deleg =3D async ? env->mideleg : env->medeleg; + bool s_injected =3D env->mvip & (1 << cause) & env->mvien && + !(env->mip & (1 << cause)); target_ulong tval =3D 0; target_ulong tinst =3D 0; target_ulong htval =3D 0; @@ -1699,8 +1711,8 @@ void riscv_cpu_do_interrupt(CPUState *cs) __func__, env->mhartid, async, cause, env->pc, tval, riscv_cpu_get_trap_name(cause, async)); =20 - if (env->priv <=3D PRV_S && - cause < TARGET_LONG_BITS && ((deleg >> cause) & 1)) { + if (env->priv <=3D PRV_S && cause < 64 && + (((deleg >> cause) & 1) || s_injected)) { /* handle the trap in S-mode */ if (riscv_has_ext(env, RVH)) { uint64_t hdeleg =3D async ? env->hideleg : env->hedeleg; diff --git a/target/riscv/csr.c b/target/riscv/csr.c index d99d954ff3..db2b06905b 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1117,21 +1117,16 @@ static RISCVException write_stimecmph(CPURISCVState= *env, int csrno, return RISCV_EXCP_NONE; } =20 -/* Machine constants */ - -#define M_MODE_INTERRUPTS ((uint64_t)(MIP_MSIP | MIP_MTIP | MIP_MEIP)) -#define S_MODE_INTERRUPTS ((uint64_t)(MIP_SSIP | MIP_STIP | MIP_SEIP | \ - MIP_LCOFIP)) -#define VS_MODE_INTERRUPTS ((uint64_t)(MIP_VSSIP | MIP_VSTIP | MIP_VSEIP)) -#define HS_MODE_INTERRUPTS ((uint64_t)(MIP_SGEIP | VS_MODE_INTERRUPTS)) - #define VSTOPI_NUM_SRCS 5 =20 -static const uint64_t delegable_ints =3D S_MODE_INTERRUPTS | - VS_MODE_INTERRUPTS; -static const uint64_t vs_delegable_ints =3D VS_MODE_INTERRUPTS; +#define LOCAL_INTERRUPTS (~0x1FFF) + +static const uint64_t delegable_ints =3D + S_MODE_INTERRUPTS | VS_MODE_INTERRUPTS | MIP_LCOFIP; +static const uint64_t vs_delegable_ints =3D + (VS_MODE_INTERRUPTS | LOCAL_INTERRUPTS) & ~MIP_LCOFIP; static const uint64_t all_ints =3D M_MODE_INTERRUPTS | S_MODE_INTERRUPTS | - HS_MODE_INTERRUPTS; + HS_MODE_INTERRUPTS | LOCAL_INTERRUPTS; #define DELEGABLE_EXCPS ((1ULL << (RISCV_EXCP_INST_ADDR_MIS)) | \ (1ULL << (RISCV_EXCP_INST_ACCESS_FAULT)) | \ (1ULL << (RISCV_EXCP_ILLEGAL_INST)) | \ @@ -1162,12 +1157,30 @@ static const target_ulong vs_delegable_excps =3D DE= LEGABLE_EXCPS & static const target_ulong sstatus_v1_10_mask =3D SSTATUS_SIE | SSTATUS_SPI= E | SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS | SSTATUS_SUM | SSTATUS_MXR | SSTATUS_VS; -static const target_ulong sip_writable_mask =3D SIP_SSIP | MIP_USIP | MIP_= UEIP | - SIP_LCOFIP; + +/* + * Spec allows for bits 13:63 to be either read-only or writable. + * So far we have interrupt LCOFIP in that region which is writable. + * + * Also, spec allows to inject virtual interrupts in this region even + * without any hardware interrupts for that interrupt number. + * + * For now interrupt in 13:63 region are all kept writable. 13 being + * LCOFIP and 14:63 being virtual only. Change this in future if we + * introduce more interrupts that are not writable. + */ + +/* Bit STIP can be an alias of mip.STIP that's why it's writable in mvip. = */ +static const target_ulong mvip_writable_mask =3D MIP_SSIP | MIP_STIP | MIP= _SEIP | + LOCAL_INTERRUPTS; +static const target_ulong mvien_writable_mask =3D MIP_SSIP | MIP_SEIP | + LOCAL_INTERRUPTS; + +static const target_ulong sip_writable_mask =3D SIP_SSIP | LOCAL_INTERRUPT= S; static const target_ulong hip_writable_mask =3D MIP_VSSIP; static const target_ulong hvip_writable_mask =3D MIP_VSSIP | MIP_VSTIP | - MIP_VSEIP; -static const target_ulong vsip_writable_mask =3D MIP_VSSIP; + MIP_VSEIP | LOCAL_INTERRUPTS; +static const target_ulong vsip_writable_mask =3D MIP_VSSIP | LOCAL_INTERRU= PTS; =20 const bool valid_vm_1_10_32[16] =3D { [VM_1_10_MBARE] =3D true, @@ -1562,6 +1575,52 @@ static RISCVException rmw_mieh(CPURISCVState *env, i= nt csrno, return ret; } =20 +static RISCVException rmw_mvien64(CPURISCVState *env, int csrno, + uint64_t *ret_val, + uint64_t new_val, uint64_t wr_mask) +{ + uint64_t mask =3D wr_mask & mvien_writable_mask; + + if (ret_val) { + *ret_val =3D env->mvien; + } + + env->mvien =3D (env->mvien & ~mask) | (new_val & mask); + + return RISCV_EXCP_NONE; +} + +static RISCVException rmw_mvien(CPURISCVState *env, int csrno, + target_ulong *ret_val, + target_ulong new_val, target_ulong wr_mask) +{ + uint64_t rval; + RISCVException ret; + + ret =3D rmw_mvien64(env, csrno, &rval, new_val, wr_mask); + if (ret_val) { + *ret_val =3D rval; + } + + return ret; +} + +static RISCVException rmw_mvienh(CPURISCVState *env, int csrno, + target_ulong *ret_val, + target_ulong new_val, target_ulong wr_mask) +{ + uint64_t rval; + RISCVException ret; + + ret =3D rmw_mvien64(env, csrno, &rval, + ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32); + if (ret_val) { + *ret_val =3D rval >> 32; + } + + return ret; +} + static int read_mtopi(CPURISCVState *env, int csrno, target_ulong *val) { int irq; @@ -1703,6 +1762,11 @@ static int rmw_xireg(CPURISCVState *env, int csrno, = target_ulong *val, priv =3D PRV_M; break; case CSR_SIREG: + if (env->priv =3D=3D PRV_S && env->mvien & MIP_SEIP && + env->siselect >=3D ISELECT_IMSIC_EIDELIVERY && + env->siselect <=3D ISELECT_IMSIC_EIE63) { + goto done; + } iprio =3D env->siprio; isel =3D env->siselect; priv =3D PRV_S; @@ -1769,6 +1833,9 @@ static int rmw_xtopei(CPURISCVState *env, int csrno, = target_ulong *val, priv =3D PRV_M; break; case CSR_STOPEI: + if (env->mvien & MIP_SEIP && env->priv =3D=3D PRV_S) { + goto done; + } priv =3D PRV_S; break; case CSR_VSTOPEI: @@ -2360,6 +2427,143 @@ static RISCVException rmw_miph(CPURISCVState *env, = int csrno, return ret; } =20 +/* + * The function is written for two use-cases: + * 1- To access mvip csr as is for m-mode access. + * 2- To access sip as a combination of mip and mvip for s-mode. + * + * Both report bits 1, 5, 9 and 13:63 but with the exception of + * STIP being read-only zero in case of mvip when sstc extension + * is present. + * Also, sip needs to be read-only zero when both mideleg[i] and + * mvien[i] are zero but mvip needs to be an alias of mip. + */ +static RISCVException rmw_mvip64(CPURISCVState *env, int csrno, + uint64_t *ret_val, + uint64_t new_val, uint64_t wr_mask) +{ + RISCVCPU *cpu =3D env_archcpu(env); + target_ulong ret_mip =3D 0; + RISCVException ret; + uint64_t old_mvip; + + /* + * mideleg[i] mvien[i] + * 0 0 No delegation. mvip[i] is alias of mip[i]. + * 0 1 mvip[i] becomes source of interrupt, mip bypas= sed. + * 1 X mip[i] is source of interrupt and mvip[i] alia= ses + * mip[i]. + * + * So alias condition would be for bits: + * ((S_MODE_INTERRUPTS | LOCAL_INTERRUPTS) & (mideleg | ~mvien)) | + * (!sstc & MIP_STIP) + * + * Non-alias condition will be for bits: + * (S_MODE_INTERRUPTS | LOCAL_INTERRUPTS) & (~mideleg & mvien) + * + * alias_mask denotes the bits that come from mip nalias_mask denotes= bits + * that come from hvip. + */ + uint64_t alias_mask =3D ((S_MODE_INTERRUPTS | LOCAL_INTERRUPTS) & + (env->mideleg | ~env->mvien)) | MIP_STIP; + uint64_t nalias_mask =3D (S_MODE_INTERRUPTS | LOCAL_INTERRUPTS) & + (~env->mideleg & env->mvien); + uint64_t wr_mask_mvip; + uint64_t wr_mask_mip; + + /* + * mideleg[i] mvien[i] + * 0 0 sip[i] read-only zero. + * 0 1 sip[i] alias of mvip[i]. + * 1 X sip[i] alias of mip[i]. + * + * Both alias and non-alias mask remain same for sip except for bits + * which are zero in both mideleg and mvien. + */ + if (csrno =3D=3D CSR_SIP) { + /* Remove bits that are zero in both mideleg and mvien. */ + alias_mask &=3D (env->mideleg | env->mvien); + nalias_mask &=3D (env->mideleg | env->mvien); + } + + /* + * If sstc is present, mvip.STIP is not an alias of mip.STIP so clear + * that our in mip returned value. + */ + if (cpu->cfg.ext_sstc && (env->priv =3D=3D PRV_M) && + get_field(env->menvcfg, MENVCFG_STCE)) { + alias_mask &=3D ~MIP_STIP; + } + + wr_mask_mip =3D wr_mask & alias_mask & mvip_writable_mask; + wr_mask_mvip =3D wr_mask & nalias_mask & mvip_writable_mask; + + /* + * For bits set in alias_mask, mvip needs to be alias of mip, so forwa= rd + * this to rmw_mip. + */ + ret =3D rmw_mip(env, CSR_MIP, &ret_mip, new_val, wr_mask_mip); + if (ret !=3D RISCV_EXCP_NONE) { + return ret; + } + + old_mvip =3D env->mvip; + + /* + * Write to mvip. Update only non-alias bits. Alias bits were updated + * in mip in rmw_mip above. + */ + if (wr_mask_mvip) { + env->mvip =3D (env->mvip & ~wr_mask_mvip) | (new_val & wr_mask_mvi= p); + + /* + * Given mvip is separate source from mip, we need to trigger inte= rrupt + * from here separately. Normally this happen from riscv_cpu_updat= e_mip. + */ + riscv_cpu_interrupt(env); + } + + if (ret_val) { + ret_mip &=3D alias_mask; + old_mvip &=3D nalias_mask; + + *ret_val =3D old_mvip | ret_mip; + } + + return RISCV_EXCP_NONE; +} + +static RISCVException rmw_mvip(CPURISCVState *env, int csrno, + target_ulong *ret_val, + target_ulong new_val, target_ulong wr_mask) +{ + uint64_t rval; + RISCVException ret; + + ret =3D rmw_mvip64(env, csrno, &rval, new_val, wr_mask); + if (ret_val) { + *ret_val =3D rval; + } + + return ret; +} + +static RISCVException rmw_mviph(CPURISCVState *env, int csrno, + target_ulong *ret_val, + target_ulong new_val, target_ulong wr_mask) +{ + uint64_t rval; + RISCVException ret; + + ret =3D rmw_mvip64(env, csrno, &rval, + ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32); + if (ret_val) { + *ret_val =3D rval >> 32; + } + + return ret; +} + /* Supervisor Trap Setup */ static RISCVException read_sstatus_i128(CPURISCVState *env, int csrno, Int128 *val) @@ -2454,20 +2658,37 @@ static RISCVException rmw_sie64(CPURISCVState *env,= int csrno, uint64_t *ret_val, uint64_t new_val, uint64_t wr_mask) { + uint64_t nalias_mask =3D (S_MODE_INTERRUPTS | LOCAL_INTERRUPTS) & + (~env->mideleg & env->mvien); + uint64_t alias_mask =3D (S_MODE_INTERRUPTS | LOCAL_INTERRUPTS) & env->= mideleg; + uint64_t sie_mask =3D wr_mask & nalias_mask; RISCVException ret; - uint64_t mask =3D env->mideleg & S_MODE_INTERRUPTS; =20 + /* + * mideleg[i] mvien[i] + * 0 0 sie[i] read-only zero. + * 0 1 sie[i] is a separate writable bit. + * 1 X sie[i] alias of mie[i]. + * + * Both alias and non-alias mask remain same for sip except for bits + * which are zero in both mideleg and mvien. + */ if (env->virt_enabled) { if (env->hvictl & HVICTL_VTI) { return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; } ret =3D rmw_vsie64(env, CSR_VSIE, ret_val, new_val, wr_mask); + if (ret_val) { + *ret_val &=3D alias_mask; + } } else { - ret =3D rmw_mie64(env, csrno, ret_val, new_val, wr_mask & mask); - } + ret =3D rmw_mie64(env, csrno, ret_val, new_val, wr_mask & alias_ma= sk); + if (ret_val) { + *ret_val &=3D alias_mask; + *ret_val |=3D env->sie & nalias_mask; + } =20 - if (ret_val) { - *ret_val &=3D mask; + env->sie =3D (env->sie & ~sie_mask) | (new_val & sie_mask); } =20 return ret; @@ -2665,7 +2886,7 @@ static RISCVException rmw_sip64(CPURISCVState *env, i= nt csrno, uint64_t new_val, uint64_t wr_mask) { RISCVException ret; - uint64_t mask =3D env->mideleg & sip_writable_mask; + uint64_t mask =3D (env->mideleg | env->mvien) & sip_writable_mask; =20 if (env->virt_enabled) { if (env->hvictl & HVICTL_VTI) { @@ -2673,11 +2894,12 @@ static RISCVException rmw_sip64(CPURISCVState *env,= int csrno, } ret =3D rmw_vsip64(env, CSR_VSIP, ret_val, new_val, wr_mask); } else { - ret =3D rmw_mip64(env, csrno, ret_val, new_val, wr_mask & mask); + ret =3D rmw_mvip64(env, csrno, ret_val, new_val, wr_mask & mask); } =20 if (ret_val) { - *ret_val &=3D env->mideleg & S_MODE_INTERRUPTS; + *ret_val &=3D (env->mideleg | env->mvien) & + (S_MODE_INTERRUPTS | LOCAL_INTERRUPTS); } =20 return ret; @@ -2842,6 +3064,7 @@ static int read_vstopi(CPURISCVState *env, int csrno,= target_ulong *val) =20 *val =3D (iid & TOPI_IID_MASK) << TOPI_IID_SHIFT; *val |=3D iprio; + return RISCV_EXCP_NONE; } =20 @@ -4165,14 +4388,14 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { [CSR_MTOPI] =3D { "mtopi", aia_any, read_mtopi }, =20 /* Virtual Interrupts for Supervisor Level (AIA) */ - [CSR_MVIEN] =3D { "mvien", aia_any, read_zero, write_ignore }, - [CSR_MVIP] =3D { "mvip", aia_any, read_zero, write_ignore }, + [CSR_MVIEN] =3D { "mvien", aia_any, NULL, NULL, rmw_mvien }, + [CSR_MVIP] =3D { "mvip", aia_any, NULL, NULL, rmw_mvip }, =20 /* Machine-Level High-Half CSRs (AIA) */ [CSR_MIDELEGH] =3D { "midelegh", aia_any32, NULL, NULL, rmw_midelegh }, [CSR_MIEH] =3D { "mieh", aia_any32, NULL, NULL, rmw_mieh }, - [CSR_MVIENH] =3D { "mvienh", aia_any32, read_zero, write_ignore }, - [CSR_MVIPH] =3D { "mviph", aia_any32, read_zero, write_ignore }, + [CSR_MVIENH] =3D { "mvienh", aia_any32, NULL, NULL, rmw_mvienh }, + [CSR_MVIPH] =3D { "mviph", aia_any32, NULL, NULL, rmw_mviph }, [CSR_MIPH] =3D { "miph", aia_any32, NULL, NULL, rmw_miph }, =20 /* Execution environment configuration */ diff --git a/target/riscv/machine.c b/target/riscv/machine.c index c7c862cdd3..3175587b0d 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -379,6 +379,9 @@ const VMStateDescription vmstate_riscv_cpu =3D { VMSTATE_UINT64(env.mip, RISCVCPU), VMSTATE_UINT64(env.miclaim, RISCVCPU), VMSTATE_UINT64(env.mie, RISCVCPU), + VMSTATE_UINT64(env.mvien, RISCVCPU), + VMSTATE_UINT64(env.mvip, RISCVCPU), + VMSTATE_UINT64(env.sie, RISCVCPU), VMSTATE_UINT64(env.mideleg, RISCVCPU), VMSTATE_UINTTL(env.satp, RISCVCPU), VMSTATE_UINTTL(env.stval, RISCVCPU), --=20 2.34.1 From nobody Tue Feb 10 16:25:20 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Date: Thu, 12 Oct 2023 11:01:03 +0100 Message-Id: <20231012100103.28612-7-rkanwal@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231012100103.28612-1-rkanwal@rivosinc.com> References: <20231012100103.28612-1-rkanwal@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::344; envelope-from=rkanwal@rivosinc.com; helo=mail-wm1-x344.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @rivosinc-com.20230601.gappssmtp.com) X-ZM-MESSAGEID: 1697104978593100002 Content-Type: text/plain; charset="utf-8" This change adds support for inserting virtual interrupts from HS-mode into VS-mode using hvien and hvip csrs. This also allows for IRQ filtering from HS-mode. Also, the spec doesn't mandate the interrupt to be actually supported in hardware. Which allows HS-mode to assert virtual interrupts to VS-mode that have no connection to any real interrupt events. This is defined as part of the AIA specification [0], "6.3.2 Virtual interrupts for VS level". [0]: https://github.com/riscv/riscv-aia/releases/download/1.0-RC4/riscv-int= errupts-1.0-RC4.pdf Signed-off-by: Rajnesh Kanwal Reviewed-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 3 +- target/riscv/cpu.h | 14 +++ target/riscv/cpu_helper.c | 48 +++++++--- target/riscv/csr.c | 196 ++++++++++++++++++++++++++++++++++---- target/riscv/machine.c | 3 + 5 files changed, 234 insertions(+), 30 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 6546634f9d..dbbea26a87 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -814,7 +814,8 @@ static bool riscv_cpu_has_work(CPUState *cs) * mode and delegation registers, but respect individual enables */ return riscv_cpu_all_pending(env) !=3D 0 || - riscv_cpu_sirq_pending(env) !=3D RISCV_EXCP_NONE; + riscv_cpu_sirq_pending(env) !=3D RISCV_EXCP_NONE || + riscv_cpu_vsirq_pending(env) !=3D RISCV_EXCP_NONE; #else return true; #endif diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 30f9481f45..7f61e17202 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -208,6 +208,12 @@ struct CPUArchState { */ uint64_t sie; =20 + /* + * When hideleg[i]=3D0 and hvien[i]=3D1, vsie[i] is no more + * alias of sie[i] (mie[i]) and needs to be maintained separatly. + */ + uint64_t vsie; + target_ulong satp; /* since: priv-1.10.0 */ target_ulong stval; target_ulong medeleg; @@ -242,6 +248,14 @@ struct CPUArchState { target_ulong hgeie; target_ulong hgeip; uint64_t htimedelta; + uint64_t hvien; + + /* + * Bits VSSIP, VSTIP and VSEIP in hvip are maintained in mip. Other bi= ts + * from 0:12 are reserved. Bits 13:63 are not aliased and must be sepa= rately + * maintain in hvip. + */ + uint64_t hvip; =20 /* Hypervisor controlled virtual interrupt priorities */ target_ulong hvictl; diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index b36161708a..b7af69de53 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -377,8 +377,9 @@ static int riscv_cpu_pending_to_irq(CPURISCVState *env, } =20 /* - * Doesn't report interrupts inserted using mvip from M-mode firmware. Tho= se - * are returned in riscv_cpu_sirq_pending(). + * Doesn't report interrupts inserted using mvip from M-mode firmware or + * using hvip bits 13:63 from HS-mode. Those are returned in + * riscv_cpu_sirq_pending() and riscv_cpu_vsirq_pending(). */ uint64_t riscv_cpu_all_pending(CPURISCVState *env) { @@ -410,16 +411,23 @@ int riscv_cpu_sirq_pending(CPURISCVState *env) =20 int riscv_cpu_vsirq_pending(CPURISCVState *env) { - uint64_t irqs =3D riscv_cpu_all_pending(env) & env->mideleg & - (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP); + uint64_t irqs =3D riscv_cpu_all_pending(env) & env->mideleg & env->hid= eleg; + uint64_t irqs_f_vs =3D env->hvip & env->hvien & ~env->hideleg & env->v= sie; + uint64_t vsbits; + + /* Bring VS-level bits to correct position */ + vsbits =3D irqs & VS_MODE_INTERRUPTS; + irqs &=3D ~VS_MODE_INTERRUPTS; + irqs |=3D vsbits >> 1; =20 return riscv_cpu_pending_to_irq(env, IRQ_S_EXT, IPRIO_DEFAULT_S, - irqs >> 1, env->hviprio); + (irqs | irqs_f_vs), env->hviprio); } =20 static int riscv_cpu_local_irq_pending(CPURISCVState *env) { - uint64_t irqs, pending, mie, hsie, vsie, irqs_f; + uint64_t irqs, pending, mie, hsie, vsie, irqs_f, irqs_f_vs; + uint64_t vsbits, irq_delegated; int virq; =20 /* Determine interrupt enable state of all privilege modes */ @@ -456,12 +464,26 @@ static int riscv_cpu_local_irq_pending(CPURISCVState = *env) irqs, env->siprio); } =20 + /* Check for virtual VS-mode interrupts. */ + irqs_f_vs =3D env->hvip & env->hvien & ~env->hideleg & env->vsie; + /* Check VS-mode interrupts */ - irqs =3D pending & env->mideleg & env->hideleg & -vsie; + irq_delegated =3D pending & env->mideleg & env->hideleg; + + /* Bring VS-level bits to correct position */ + vsbits =3D irq_delegated & VS_MODE_INTERRUPTS; + irq_delegated &=3D ~VS_MODE_INTERRUPTS; + irq_delegated |=3D vsbits >> 1; + + irqs =3D (irq_delegated | irqs_f_vs) & -vsie; if (irqs) { virq =3D riscv_cpu_pending_to_irq(env, IRQ_S_EXT, IPRIO_DEFAULT_S, - irqs >> 1, env->hviprio); - return (virq <=3D 0) ? virq : virq + 1; + irqs, env->hviprio); + if (virq <=3D 0 || (virq > 12 && virq <=3D 63)) { + return virq; + } else { + return virq + 1; + } } =20 /* Indicate no pending interrupt */ @@ -638,6 +660,7 @@ void riscv_cpu_interrupt(CPURISCVState *env) if (env->virt_enabled) { gein =3D get_field(env->hstatus, HSTATUS_VGEIN); vsgein =3D (env->hgeip & (1ULL << gein)) ? MIP_VSEIP : 0; + irqf =3D env->hvien & env->hvip & env->vsie; } else { irqf =3D env->mvien & env->mvip & env->sie; } @@ -1623,6 +1646,8 @@ void riscv_cpu_do_interrupt(CPUState *cs) uint64_t deleg =3D async ? env->mideleg : env->medeleg; bool s_injected =3D env->mvip & (1 << cause) & env->mvien && !(env->mip & (1 << cause)); + bool vs_injected =3D env->hvip & (1 << cause) & env->hvien && + !(env->mip & (1 << cause)); target_ulong tval =3D 0; target_ulong tinst =3D 0; target_ulong htval =3D 0; @@ -1712,12 +1737,13 @@ void riscv_cpu_do_interrupt(CPUState *cs) riscv_cpu_get_trap_name(cause, async)); =20 if (env->priv <=3D PRV_S && cause < 64 && - (((deleg >> cause) & 1) || s_injected)) { + (((deleg >> cause) & 1) || s_injected || vs_injected)) { /* handle the trap in S-mode */ if (riscv_has_ext(env, RVH)) { uint64_t hdeleg =3D async ? env->hideleg : env->hedeleg; =20 - if (env->virt_enabled && ((hdeleg >> cause) & 1)) { + if (env->virt_enabled && + (((hdeleg >> cause) & 1) || vs_injected)) { /* Trap to VS mode */ /* * See if we need to adjust cause. Yes if its VS mode inte= rrupt diff --git a/target/riscv/csr.c b/target/riscv/csr.c index db2b06905b..1dfd072df9 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -30,6 +30,7 @@ #include "qemu/guest-random.h" #include "qapi/error.h" =20 + /* CSR function table public API */ void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops) { @@ -1180,6 +1181,8 @@ static const target_ulong sip_writable_mask =3D SIP_S= SIP | LOCAL_INTERRUPTS; static const target_ulong hip_writable_mask =3D MIP_VSSIP; static const target_ulong hvip_writable_mask =3D MIP_VSSIP | MIP_VSTIP | MIP_VSEIP | LOCAL_INTERRUPTS; +static const target_ulong hvien_writable_mask =3D LOCAL_INTERRUPTS; + static const target_ulong vsip_writable_mask =3D MIP_VSSIP | LOCAL_INTERRU= PTS; =20 const bool valid_vm_1_10_32[16] =3D { @@ -2608,16 +2611,36 @@ static RISCVException rmw_vsie64(CPURISCVState *env= , int csrno, uint64_t *ret_val, uint64_t new_val, uint64_t wr_mask) { + uint64_t alias_mask =3D (LOCAL_INTERRUPTS | VS_MODE_INTERRUPTS) & + env->hideleg; + uint64_t nalias_mask =3D LOCAL_INTERRUPTS & (~env->hideleg & env->hvie= n); + uint64_t rval, rval_vs, vsbits; + uint64_t wr_mask_vsie; + uint64_t wr_mask_mie; RISCVException ret; - uint64_t rval, mask =3D env->hideleg & VS_MODE_INTERRUPTS; =20 /* Bring VS-level bits to correct position */ - new_val =3D (new_val & (VS_MODE_INTERRUPTS >> 1)) << 1; - wr_mask =3D (wr_mask & (VS_MODE_INTERRUPTS >> 1)) << 1; + vsbits =3D new_val & (VS_MODE_INTERRUPTS >> 1); + new_val &=3D ~(VS_MODE_INTERRUPTS >> 1); + new_val |=3D vsbits << 1; + + vsbits =3D wr_mask & (VS_MODE_INTERRUPTS >> 1); + wr_mask &=3D ~(VS_MODE_INTERRUPTS >> 1); + wr_mask |=3D vsbits << 1; + + wr_mask_mie =3D wr_mask & alias_mask; + wr_mask_vsie =3D wr_mask & nalias_mask; + + ret =3D rmw_mie64(env, csrno, &rval, new_val, wr_mask_mie); + + rval_vs =3D env->vsie & nalias_mask; + env->vsie =3D (env->vsie & ~wr_mask_vsie) | (new_val & wr_mask_vsie); =20 - ret =3D rmw_mie64(env, csrno, &rval, new_val, wr_mask & mask); if (ret_val) { - *ret_val =3D (rval & mask) >> 1; + rval &=3D alias_mask; + vsbits =3D rval & VS_MODE_INTERRUPTS; + rval &=3D ~VS_MODE_INTERRUPTS; + *ret_val =3D rval | (vsbits >> 1) | rval_vs; } =20 return ret; @@ -2830,21 +2853,36 @@ static RISCVException write_stval(CPURISCVState *en= v, int csrno, return RISCV_EXCP_NONE; } =20 +static RISCVException rmw_hvip64(CPURISCVState *env, int csrno, + uint64_t *ret_val, + uint64_t new_val, uint64_t wr_mask); + static RISCVException rmw_vsip64(CPURISCVState *env, int csrno, uint64_t *ret_val, uint64_t new_val, uint64_t wr_mask) { RISCVException ret; uint64_t rval, mask =3D env->hideleg & VS_MODE_INTERRUPTS; + uint64_t vsbits; =20 - /* Bring VS-level bits to correct position */ - new_val =3D (new_val & (VS_MODE_INTERRUPTS >> 1)) << 1; - wr_mask =3D (wr_mask & (VS_MODE_INTERRUPTS >> 1)) << 1; + /* Add virtualized bits into vsip mask. */ + mask |=3D env->hvien & ~env->hideleg; =20 - ret =3D rmw_mip64(env, csrno, &rval, new_val, - wr_mask & mask & vsip_writable_mask); + /* Bring VS-level bits to correct position */ + vsbits =3D new_val & (VS_MODE_INTERRUPTS >> 1); + new_val &=3D ~(VS_MODE_INTERRUPTS >> 1); + new_val |=3D vsbits << 1; + vsbits =3D wr_mask & (VS_MODE_INTERRUPTS >> 1); + wr_mask &=3D ~(VS_MODE_INTERRUPTS >> 1); + wr_mask |=3D vsbits << 1; + + ret =3D rmw_hvip64(env, csrno, &rval, new_val, + wr_mask & mask & vsip_writable_mask); if (ret_val) { - *ret_val =3D (rval & mask) >> 1; + rval &=3D mask; + vsbits =3D rval & VS_MODE_INTERRUPTS; + rval &=3D ~VS_MODE_INTERRUPTS; + *ret_val =3D rval | (vsbits >> 1); } =20 return ret; @@ -3136,6 +3174,52 @@ static RISCVException write_hedeleg(CPURISCVState *e= nv, int csrno, return RISCV_EXCP_NONE; } =20 +static RISCVException rmw_hvien64(CPURISCVState *env, int csrno, + uint64_t *ret_val, + uint64_t new_val, uint64_t wr_mask) +{ + uint64_t mask =3D wr_mask & hvien_writable_mask; + + if (ret_val) { + *ret_val =3D env->hvien; + } + + env->hvien =3D (env->hvien & ~mask) | (new_val & mask); + + return RISCV_EXCP_NONE; +} + +static RISCVException rmw_hvien(CPURISCVState *env, int csrno, + target_ulong *ret_val, + target_ulong new_val, target_ulong wr_mask) +{ + uint64_t rval; + RISCVException ret; + + ret =3D rmw_hvien64(env, csrno, &rval, new_val, wr_mask); + if (ret_val) { + *ret_val =3D rval; + } + + return ret; +} + +static RISCVException rmw_hvienh(CPURISCVState *env, int csrno, + target_ulong *ret_val, + target_ulong new_val, target_ulong wr_m= ask) +{ + uint64_t rval; + RISCVException ret; + + ret =3D rmw_hvien64(env, csrno, &rval, + ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32); + if (ret_val) { + *ret_val =3D rval >> 32; + } + + return ret; +} + static RISCVException rmw_hideleg64(CPURISCVState *env, int csrno, uint64_t *ret_val, uint64_t new_val, uint64_t wr_mask) @@ -3181,16 +3265,94 @@ static RISCVException rmw_hidelegh(CPURISCVState *e= nv, int csrno, return ret; } =20 +/* + * The function is written for two use-cases: + * 1- To access hvip csr as is for HS-mode access. + * 2- To access vsip as a combination of hvip, and mip for vs-mode. + * + * Both report bits 2, 6, 10 and 13:63. + * vsip needs to be read-only zero when both hideleg[i] and + * hvien[i] are zero. + */ static RISCVException rmw_hvip64(CPURISCVState *env, int csrno, uint64_t *ret_val, uint64_t new_val, uint64_t wr_mask) { RISCVException ret; + uint64_t old_hvip; + uint64_t ret_mip; + + /* + * For bits 10, 6 and 2, vsip[i] is an alias of hip[i]. These bits are + * present in hip, hvip and mip. Where mip[i] is alias of hip[i] and h= vip[i] + * is OR'ed in hip[i] to inject virtual interrupts from hypervisor. Th= ese + * bits are actually being maintained in mip so we read them from ther= e. + * This way we have a single source of truth and allows for easier + * implementation. + * + * For bits 13:63 we have: + * + * hideleg[i] hvien[i] + * 0 0 No delegation. vsip[i] readonly zero. + * 0 1 vsip[i] is alias of hvip[i], sip bypassed. + * 1 X vsip[i] is alias of sip[i], hvip bypassed. + * + * alias_mask denotes the bits that come from sip (mip here given we + * maintain all bits there). nalias_mask denotes bits that come from + * hvip. + */ + uint64_t alias_mask =3D (env->hideleg | ~env->hvien) | VS_MODE_INTERRU= PTS; + uint64_t nalias_mask =3D (~env->hideleg & env->hvien); + uint64_t wr_mask_hvip; + uint64_t wr_mask_mip; + + /* + * Both alias and non-alias mask remain same for vsip except: + * 1- For VS* bits if they are zero in hideleg. + * 2- For 13:63 bits if they are zero in both hideleg and hvien. + */ + if (csrno =3D=3D CSR_VSIP) { + /* zero-out VS* bits that are not delegated to VS mode. */ + alias_mask &=3D (env->hideleg | ~VS_MODE_INTERRUPTS); + + /* + * zero-out 13:63 bits that are zero in both hideleg and hvien. + * nalias_mask mask can not contain any VS* bits so only second + * condition applies on it. + */ + nalias_mask &=3D (env->hideleg | env->hvien); + alias_mask &=3D (env->hideleg | env->hvien); + } + + wr_mask_hvip =3D wr_mask & nalias_mask & hvip_writable_mask; + wr_mask_mip =3D wr_mask & alias_mask & hvip_writable_mask; + + /* Aliased bits, bits 10, 6, 2 need to come from mip. */ + ret =3D rmw_mip64(env, csrno, &ret_mip, new_val, wr_mask_mip); + if (ret !=3D RISCV_EXCP_NONE) { + return ret; + } + + old_hvip =3D env->hvip; + + if (wr_mask_hvip) { + env->hvip =3D (env->hvip & ~wr_mask_hvip) | (new_val & wr_mask_hvi= p); + + /* + * Given hvip is separate source from mip, we need to trigger inte= rrupt + * from here separately. Normally this happen from riscv_cpu_updat= e_mip. + */ + riscv_cpu_interrupt(env); + } =20 - ret =3D rmw_mip64(env, csrno, ret_val, new_val, - wr_mask & hvip_writable_mask); if (ret_val) { - *ret_val &=3D VS_MODE_INTERRUPTS; + /* Only take VS* bits from mip. */ + ret_mip &=3D alias_mask; + + /* Take in non-delegated 13:63 bits from hvip. */ + old_hvip &=3D nalias_mask; + + *ret_val =3D ret_mip | old_hvip; } =20 return ret; @@ -4569,14 +4731,13 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { .min_priv_ver =3D PRIV_VERSION_1_12_0 = }, =20 /* Virtual Interrupts and Interrupt Priorities (H-extension with AIA) = */ - [CSR_HVIEN] =3D { "hvien", aia_hmode, read_zero, write_ign= ore }, + [CSR_HVIEN] =3D { "hvien", aia_hmode, NULL, NULL, rmw_hvie= n }, [CSR_HVICTL] =3D { "hvictl", aia_hmode, read_hvictl, write_hvictl = }, [CSR_HVIPRIO1] =3D { "hviprio1", aia_hmode, read_hviprio1, write_hviprio1 = }, [CSR_HVIPRIO2] =3D { "hviprio2", aia_hmode, read_hviprio2, write_hviprio2 = }, - /* * VS-Level Window to Indirectly Accessed Registers (H-extension with = AIA) */ @@ -4591,8 +4752,7 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { /* Hypervisor and VS-Level High-Half CSRs (H-extension with AIA) */ [CSR_HIDELEGH] =3D { "hidelegh", aia_hmode32, NULL, NULL, rmw_hidelegh = }, - [CSR_HVIENH] =3D { "hvienh", aia_hmode32, read_zero, - write_ignore = }, + [CSR_HVIENH] =3D { "hvienh", aia_hmode32, NULL, NULL, rmw_hv= ienh }, [CSR_HVIPH] =3D { "hviph", aia_hmode32, NULL, NULL, rmw_hv= iph }, [CSR_HVIPRIO1H] =3D { "hviprio1h", aia_hmode32, read_hviprio1h, write_hviprio1h = }, diff --git a/target/riscv/machine.c b/target/riscv/machine.c index 3175587b0d..97e79d333f 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -92,6 +92,8 @@ static const VMStateDescription vmstate_hyper =3D { VMSTATE_UINTTL(env.hgatp, RISCVCPU), VMSTATE_UINTTL(env.hgeie, RISCVCPU), VMSTATE_UINTTL(env.hgeip, RISCVCPU), + VMSTATE_UINT64(env.hvien, RISCVCPU), + VMSTATE_UINT64(env.hvip, RISCVCPU), VMSTATE_UINT64(env.htimedelta, RISCVCPU), VMSTATE_UINT64(env.vstimecmp, RISCVCPU), =20 @@ -106,6 +108,7 @@ static const VMStateDescription vmstate_hyper =3D { VMSTATE_UINTTL(env.vstval, RISCVCPU), VMSTATE_UINTTL(env.vsatp, RISCVCPU), VMSTATE_UINTTL(env.vsiselect, RISCVCPU), + VMSTATE_UINT64(env.vsie, RISCVCPU), =20 VMSTATE_UINTTL(env.mtval2, RISCVCPU), VMSTATE_UINTTL(env.mtinst, RISCVCPU), --=20 2.34.1