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[2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id ja20-20020a170902efd400b001c1f4edfb9csm726348plb.173.2023.10.11.21.13.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Oct 2023 21:13:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1697084004; x=1697688804; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Y+SVeuJDU73Mhx2ICBj7Pvm9Vz0EkZFqrjLXREeYNGk=; b=GSLxj++KpgRNQPTNpOpVZlUHlRIs6xJpLfHUh61YoClxnRkVD6gLJCv/VCEM2/JnBN EHhPgS94reLa8mb5IkO7tLGKiXjEBueOIEh1cErCbLm3qmbLYH/52+ekRN3cm1beaEuE +7S0nJDDzSPsgtwJrhkosnVu/2SC3FjEX1Qf4sM/g078o7MOeOPrZjJW/vze+7Rh4FjV en5tvsubVwm2twlXiq/KBNhQMOIpnmJeJiomm8UnpMIydHofQdu6wnJ+CRpSdCBCa/me W9XPq2kSHaf8Zgxu9NiT9yDGHSFkpviJ8k6CySIXDuugYU2dCrEe5rjxj/0ZhsDZmZ7n taDw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697084004; x=1697688804; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Y+SVeuJDU73Mhx2ICBj7Pvm9Vz0EkZFqrjLXREeYNGk=; b=JIrfj1xmcRYCThEU8Cuft2oGptI2/+app+syeVFVMQNANdkrHsrUsnc+zEqjA8xp+8 Shf0Y93x7lnvWVtuX0ZWn9cn9Y4U3gMLDwC5Odaghn8TtYnnMe5bYjyXxaazdh6ak/OG 0HLwlICgrMvPhssk+6Wc6Kd+b6E37AhglXoCeii8RYyQr8uQiYvRmMaLDyfflDaCSv2f bwyXqrPycSVstv8l/avlynr1L+l3TqPAQzpwOAYiuEGF+QfmMCLyg//2f7wR65+apcu0 KmheJs5OK3rClKmfgvfBSk0lWD+obnDxMlfR+0sHQEM/iQbJ/SU5UN7K7sN9q4WbxYsO cd0w== X-Gm-Message-State: AOJu0YytwR/+7jJ1GdONBfDESAUKPYwCOkYaV2F5JEL1Ijhv5tCK0pFv PWh74NO99PnrfdM86F3xmiaf6juwl6YssA== X-Google-Smtp-Source: AGHT+IGugfHvitBDVcdwWdWA4Y+5gbFlke4dCYRxruvjA7epmdkpM2HIhULrpuLmRxA8U/zGqG0GMw== X-Received: by 2002:a05:6a20:9188:b0:14c:d494:77c5 with SMTP id v8-20020a056a20918800b0014cd49477c5mr28001298pzd.13.1697084004600; Wed, 11 Oct 2023 21:13:24 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Daniel Henrique Barboza , Andrew Jones , Alistair Francis Subject: [PULL 40/54] target/riscv/cpu.c: export isa_edata_arr[] Date: Thu, 12 Oct 2023 14:10:37 +1000 Message-ID: <20231012041051.2572507-41-alistair.francis@wdc.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231012041051.2572507-1-alistair.francis@wdc.com> References: <20231012041051.2572507-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52a; envelope-from=alistair23@gmail.com; helo=mail-pg1-x52a.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1697084407516100001 Content-Type: text/plain; charset="utf-8" From: Daniel Henrique Barboza This array will be read by the TCG accel class, allowing it to handle priv spec verifications on its own. The array will remain here in cpu.c because it's also used by the riscv,isa string function. To export it we'll finish it with an empty element since ARRAY_SIZE() won't work outside of cpu.c. Get rid of its ARRAY_SIZE() usage now to alleviate the changes for the next patch. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones Reviewed-by: Alistair Francis Message-ID: <20230925175709.35696-19-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 7 +++++++ target/riscv/cpu.c | 47 +++++++++++++++++++++------------------------- 2 files changed, 28 insertions(+), 26 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 089c7e6d95..6eef1f697e 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -726,6 +726,13 @@ extern const RISCVCPUMultiExtConfig riscv_cpu_vendor_e= xts[]; extern const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[]; extern Property riscv_cpu_options[]; =20 +typedef struct isa_ext_data { + const char *name; + int min_version; + int ext_enable_offset; +} RISCVIsaExtData; +extern const RISCVIsaExtData isa_edata_arr[]; + void riscv_add_satp_mode_properties(Object *obj); =20 /* CSR function table */ diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index d758d61ff8..989610ff90 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -41,15 +41,6 @@ static const char riscv_single_letter_exts[] =3D "IEMAFD= QCPVH"; const uint32_t misa_bits[] =3D {RVI, RVE, RVM, RVA, RVF, RVD, RVV, RVC, RVS, RVU, RVH, RVJ, RVG, 0}; =20 -struct isa_ext_data { - const char *name; - int min_version; - int ext_enable_offset; -}; - -#define ISA_EXT_DATA_ENTRY(_name, _min_ver, _prop) \ - {#_name, _min_ver, CPU_CFG_OFFSET(_prop)} - /* * From vector_helper.c * Note that vector data is stored in host-endian 64-bit chunks, @@ -61,6 +52,9 @@ struct isa_ext_data { #define BYTE(x) (x) #endif =20 +#define ISA_EXT_DATA_ENTRY(_name, _min_ver, _prop) \ + {#_name, _min_ver, CPU_CFG_OFFSET(_prop)} + /* * Here are the ordering rules of extension naming defined by RISC-V * specification : @@ -81,7 +75,7 @@ struct isa_ext_data { * Single letter extensions are checked in riscv_cpu_validate_misa_priv() * instead. */ -static const struct isa_ext_data isa_edata_arr[] =3D { +const RISCVIsaExtData isa_edata_arr[] =3D { ISA_EXT_DATA_ENTRY(zicbom, PRIV_VERSION_1_12_0, ext_icbom), ISA_EXT_DATA_ENTRY(zicboz, PRIV_VERSION_1_12_0, ext_icboz), ISA_EXT_DATA_ENTRY(zicond, PRIV_VERSION_1_12_0, ext_zicond), @@ -160,6 +154,8 @@ static const struct isa_ext_data isa_edata_arr[] =3D { ISA_EXT_DATA_ENTRY(xtheadmempair, PRIV_VERSION_1_11_0, ext_xtheadmempa= ir), ISA_EXT_DATA_ENTRY(xtheadsync, PRIV_VERSION_1_11_0, ext_xtheadsync), ISA_EXT_DATA_ENTRY(xventanacondops, PRIV_VERSION_1_12_0, ext_XVentanaC= ondOps), + + DEFINE_PROP_END_OF_LIST(), }; =20 bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset) @@ -178,14 +174,14 @@ void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t e= xt_offset, bool en) =20 int cpu_cfg_ext_get_min_version(uint32_t ext_offset) { - int i; + const RISCVIsaExtData *edata; =20 - for (i =3D 0; i < ARRAY_SIZE(isa_edata_arr); i++) { - if (isa_edata_arr[i].ext_enable_offset !=3D ext_offset) { + for (edata =3D isa_edata_arr; edata && edata->name; edata++) { + if (edata->ext_enable_offset !=3D ext_offset) { continue; } =20 - return isa_edata_arr[i].min_version; + return edata->min_version; } =20 g_assert_not_reached(); @@ -932,22 +928,21 @@ static void riscv_cpu_disas_set_info(CPUState *s, dis= assemble_info *info) void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu) { CPURISCVState *env =3D &cpu->env; - int i; + const RISCVIsaExtData *edata; =20 /* Force disable extensions if priv spec version does not match */ - for (i =3D 0; i < ARRAY_SIZE(isa_edata_arr); i++) { - if (isa_ext_is_enabled(cpu, isa_edata_arr[i].ext_enable_offset) && - (env->priv_ver < isa_edata_arr[i].min_version)) { - isa_ext_update_enabled(cpu, isa_edata_arr[i].ext_enable_offset, - false); + for (edata =3D isa_edata_arr; edata && edata->name; edata++) { + if (isa_ext_is_enabled(cpu, edata->ext_enable_offset) && + (env->priv_ver < edata->min_version)) { + isa_ext_update_enabled(cpu, edata->ext_enable_offset, false); #ifndef CONFIG_USER_ONLY warn_report("disabling %s extension for hart 0x" TARGET_FMT_lx " because privilege spec version does not match", - isa_edata_arr[i].name, env->mhartid); + edata->name, env->mhartid); #else warn_report("disabling %s extension because " "privilege spec version does not match", - isa_edata_arr[i].name); + edata->name); #endif } } @@ -1615,13 +1610,13 @@ static void riscv_cpu_class_init(ObjectClass *c, vo= id *data) static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str, int max_str_len) { + const RISCVIsaExtData *edata; char *old =3D *isa_str; char *new =3D *isa_str; - int i; =20 - for (i =3D 0; i < ARRAY_SIZE(isa_edata_arr); i++) { - if (isa_ext_is_enabled(cpu, isa_edata_arr[i].ext_enable_offset)) { - new =3D g_strconcat(old, "_", isa_edata_arr[i].name, NULL); + for (edata =3D isa_edata_arr; edata && edata->name; edata++) { + if (isa_ext_is_enabled(cpu, edata->ext_enable_offset)) { + new =3D g_strconcat(old, "_", edata->name, NULL); g_free(old); old =3D new; } --=20 2.41.0