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[2403:580b:97e8:0:321:6fb2:58f1:a1b1]) by smtp.gmail.com with ESMTPSA id ja20-20020a170902efd400b001c1f4edfb9csm726348plb.173.2023.10.11.21.12.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Oct 2023 21:12:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1697083956; x=1697688756; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=c4BVdCjnj+Z4kisD+3OOaEmdvW6l047A1hJ8j4wHdEE=; b=MiVmhWgLFeMp5+GOUWpoe6liKg+jeXzFuDsXIr+6eQMwi1XXCRD4NXTcEf+XxaH0wL eDs9t2e3RmFQ6apY8RtYF7GiTOjJLZoz8D8ARmBtztqgoP70szRtRa41pl/Mhj4z5Qdn 2ty36xCDL36/t1eQ8TSG7yhvUj138KdvA7u3ZVcHUKpAWbULjStCNhZtlXjxU8BdibDs amH2hx/NPtcXhsXGRhX0k6L5m6bk/r+702rPEB/QBIt1YrmkdmqsHeWQ2IkZLgSmufL5 kffheBJR1g7Tcei2BBrUyELkAfti9p7WDhsXFTY//FenlhWV/oW9nYS4lwyVRfP2h70N BA+Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697083956; x=1697688756; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=c4BVdCjnj+Z4kisD+3OOaEmdvW6l047A1hJ8j4wHdEE=; b=DNj6aXlwNQ+7G/IRwk1bbbHkZ/SBOaIUmy6eTMh/SZzxmYLqOcHe+goJcbP2WuX40i rSCwobwRKfph8G0DsC6E/onX+npiHOkXA81bsCoydPt26gPX1Hp0a0b7vHd3uxoGrGmA WEpUwDsqGweOT0WAmMi0qEAef9wJy0aMyUKg8YNiq2vsxE47AZ9hS7DmYaRj+utvtZHm PEkh1eMNIFUymKZWzwQjkMQewKhVe2ncRT17JlR+wlZOB/If0FNt6YmnxWoBXQaRgyms Al/6tbnJQzw7KJ8zwz5iSMynhewekzjzxoJFRgcSymgMpJ5I/5m3qwBaAoQq8HNHGITP UzEw== X-Gm-Message-State: AOJu0YxFvxeoU2TUZ/m3BsYftVNfGPsQkOqD9OOmS/TsBmIFUNl/B6Aq 8MPOBUb26t8s3wKzLuJ4tdjVhZJIzZOztw== X-Google-Smtp-Source: AGHT+IGgCRPrk2Pim+9nZJ0YRUrJlo6Gl0hr+zj611KrIw5bjsITOqeqgoEd5GGEkrUtUGH6uG0JuQ== X-Received: by 2002:a05:6a20:938b:b0:15a:2c0b:6c73 with SMTP id x11-20020a056a20938b00b0015a2c0b6c73mr28993986pzh.12.1697083955883; Wed, 11 Oct 2023 21:12:35 -0700 (PDT) From: Alistair Francis X-Google-Original-From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Daniel Henrique Barboza , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Andrew Jones , LIU Zhiwei , Alistair Francis Subject: [PULL 26/54] target/riscv: move riscv_tcg_ops to tcg-cpu.c Date: Thu, 12 Oct 2023 14:10:23 +1000 Message-ID: <20231012041051.2572507-27-alistair.francis@wdc.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231012041051.2572507-1-alistair.francis@wdc.com> References: <20231012041051.2572507-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::434; envelope-from=alistair23@gmail.com; helo=mail-pf1-x434.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1697084447621100001 From: Daniel Henrique Barboza Move the remaining of riscv_tcg_ops now that we have a working realize() implementation. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Andrew Jones Reviewed-by: LIU Zhiwei Reviewed-by: Alistair Francis Message-ID: <20230925175709.35696-5-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 4 --- target/riscv/cpu.c | 58 ------------------------------------ target/riscv/tcg/tcg-cpu.c | 60 +++++++++++++++++++++++++++++++++++++- 3 files changed, 59 insertions(+), 63 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index e1e47d7509..3055d741c5 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -706,10 +706,6 @@ enum riscv_pmu_event_idx { RISCV_PMU_EVENT_CACHE_ITLB_PREFETCH_MISS =3D 0x10021, }; =20 -/* Export tcg_ops until we move everything to tcg/tcg-cpu.c */ -#include "hw/core/tcg-cpu-ops.h" -extern const struct TCGCPUOps riscv_tcg_ops; - /* used by tcg/tcg-cpu.c*/ void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t ext_offset, bool en); bool cpu_cfg_ext_is_user_set(uint32_t ext_offset); diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 943aca2c20..08cbd51ea1 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -838,24 +838,6 @@ static vaddr riscv_cpu_get_pc(CPUState *cs) return env->pc; } =20 -static void riscv_cpu_synchronize_from_tb(CPUState *cs, - const TranslationBlock *tb) -{ - if (!(tb_cflags(tb) & CF_PCREL)) { - RISCVCPU *cpu =3D RISCV_CPU(cs); - CPURISCVState *env =3D &cpu->env; - RISCVMXL xl =3D FIELD_EX32(tb->flags, TB_FLAGS, XL); - - tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL)); - - if (xl =3D=3D MXL_RV32) { - env->pc =3D (int32_t) tb->pc; - } else { - env->pc =3D tb->pc; - } - } -} - static bool riscv_cpu_has_work(CPUState *cs) { #ifndef CONFIG_USER_ONLY @@ -871,29 +853,6 @@ static bool riscv_cpu_has_work(CPUState *cs) #endif } =20 -static void riscv_restore_state_to_opc(CPUState *cs, - const TranslationBlock *tb, - const uint64_t *data) -{ - RISCVCPU *cpu =3D RISCV_CPU(cs); - CPURISCVState *env =3D &cpu->env; - RISCVMXL xl =3D FIELD_EX32(tb->flags, TB_FLAGS, XL); - target_ulong pc; - - if (tb_cflags(tb) & CF_PCREL) { - pc =3D (env->pc & TARGET_PAGE_MASK) | data[0]; - } else { - pc =3D data[0]; - } - - if (xl =3D=3D MXL_RV32) { - env->pc =3D (int32_t)pc; - } else { - env->pc =3D pc; - } - env->bins =3D data[1]; -} - static void riscv_cpu_reset_hold(Object *obj) { #ifndef CONFIG_USER_ONLY @@ -1805,23 +1764,6 @@ static const struct SysemuCPUOps riscv_sysemu_ops = =3D { }; #endif =20 -const struct TCGCPUOps riscv_tcg_ops =3D { - .initialize =3D riscv_translate_init, - .synchronize_from_tb =3D riscv_cpu_synchronize_from_tb, - .restore_state_to_opc =3D riscv_restore_state_to_opc, - -#ifndef CONFIG_USER_ONLY - .tlb_fill =3D riscv_cpu_tlb_fill, - .cpu_exec_interrupt =3D riscv_cpu_exec_interrupt, - .do_interrupt =3D riscv_cpu_do_interrupt, - .do_transaction_failed =3D riscv_cpu_do_transaction_failed, - .do_unaligned_access =3D riscv_cpu_do_unaligned_access, - .debug_excp_handler =3D riscv_cpu_debug_excp_handler, - .debug_check_breakpoint =3D riscv_cpu_debug_check_breakpoint, - .debug_check_watchpoint =3D riscv_cpu_debug_check_watchpoint, -#endif /* !CONFIG_USER_ONLY */ -}; - static bool riscv_cpu_is_dynamic(Object *cpu_obj) { return object_dynamic_cast(cpu_obj, TYPE_RISCV_DYNAMIC_CPU) !=3D NULL; diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 0ea691fbba..c92dfc20cb 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -28,7 +28,66 @@ #include "qemu/error-report.h" #include "qemu/log.h" #include "hw/core/accel-cpu.h" +#include "hw/core/tcg-cpu-ops.h" +#include "tcg/tcg.h" =20 +static void riscv_cpu_synchronize_from_tb(CPUState *cs, + const TranslationBlock *tb) +{ + if (!(tb_cflags(tb) & CF_PCREL)) { + RISCVCPU *cpu =3D RISCV_CPU(cs); + CPURISCVState *env =3D &cpu->env; + RISCVMXL xl =3D FIELD_EX32(tb->flags, TB_FLAGS, XL); + + tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL)); + + if (xl =3D=3D MXL_RV32) { + env->pc =3D (int32_t) tb->pc; + } else { + env->pc =3D tb->pc; + } + } +} + +static void riscv_restore_state_to_opc(CPUState *cs, + const TranslationBlock *tb, + const uint64_t *data) +{ + RISCVCPU *cpu =3D RISCV_CPU(cs); + CPURISCVState *env =3D &cpu->env; + RISCVMXL xl =3D FIELD_EX32(tb->flags, TB_FLAGS, XL); + target_ulong pc; + + if (tb_cflags(tb) & CF_PCREL) { + pc =3D (env->pc & TARGET_PAGE_MASK) | data[0]; + } else { + pc =3D data[0]; + } + + if (xl =3D=3D MXL_RV32) { + env->pc =3D (int32_t)pc; + } else { + env->pc =3D pc; + } + env->bins =3D data[1]; +} + +static const struct TCGCPUOps riscv_tcg_ops =3D { + .initialize =3D riscv_translate_init, + .synchronize_from_tb =3D riscv_cpu_synchronize_from_tb, + .restore_state_to_opc =3D riscv_restore_state_to_opc, + +#ifndef CONFIG_USER_ONLY + .tlb_fill =3D riscv_cpu_tlb_fill, + .cpu_exec_interrupt =3D riscv_cpu_exec_interrupt, + .do_interrupt =3D riscv_cpu_do_interrupt, + .do_transaction_failed =3D riscv_cpu_do_transaction_failed, + .do_unaligned_access =3D riscv_cpu_do_unaligned_access, + .debug_excp_handler =3D riscv_cpu_debug_excp_handler, + .debug_check_breakpoint =3D riscv_cpu_debug_check_breakpoint, + .debug_check_watchpoint =3D riscv_cpu_debug_check_watchpoint, +#endif /* !CONFIG_USER_ONLY */ +}; =20 static void cpu_cfg_ext_auto_update(RISCVCPU *cpu, uint32_t ext_offset, bool value) @@ -515,7 +574,6 @@ static void tcg_cpu_init_ops(AccelCPUClass *accel_cpu, = CPUClass *cc) { /* * All cpus use the same set of operations. - * riscv_tcg_ops is being imported from cpu.c for now. */ cc->tcg_ops =3D &riscv_tcg_ops; } --=20 2.41.0