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Iglesias" , Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Yoshinori Sato , Richard Henderson , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , qemu-arm@nongnu.org (open list:ARM TCG CPUs), qemu-riscv@nongnu.org (open list:RISC-V TCG CPUs), qemu-s390x@nongnu.org (open list:S390 TCG CPUs) Subject: [PATCH v9 14/23] gdbstub: Infer number of core registers from XML Date: Wed, 11 Oct 2023 16:03:00 +0900 Message-ID: <20231011070335.14398-15-akihiko.odaki@daynix.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231011070335.14398-1-akihiko.odaki@daynix.com> References: <20231011070335.14398-1-akihiko.odaki@daynix.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=2607:f8b0:4864:20::534; envelope-from=akihiko.odaki@daynix.com; helo=mail-pg1-x534.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @daynix-com.20230601.gappssmtp.com) X-ZM-MESSAGEID: 1697008134818100001 Content-Type: text/plain; charset="utf-8" GDBFeature has the num_regs member so use it where applicable to remove magic numbers. Signed-off-by: Akihiko Odaki --- include/hw/core/cpu.h | 3 ++- target/s390x/cpu.h | 2 -- gdbstub/gdbstub.c | 5 ++++- target/arm/cpu.c | 1 - target/arm/cpu64.c | 1 - target/avr/cpu.c | 1 - target/hexagon/cpu.c | 1 - target/i386/cpu.c | 2 -- target/loongarch/cpu.c | 2 -- target/m68k/cpu.c | 1 - target/microblaze/cpu.c | 1 - target/riscv/cpu.c | 1 - target/rx/cpu.c | 1 - target/s390x/cpu.c | 1 - 14 files changed, 6 insertions(+), 17 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 3968369554..11d4b5cd0c 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -127,7 +127,8 @@ struct SysemuCPUOps; * @gdb_adjust_breakpoint: Callback for adjusting the address of a * breakpoint. Used by AVR to handle a gdb mis-feature with * its Harvard architecture split code and data. - * @gdb_num_core_regs: Number of core registers accessible to GDB. + * @gdb_num_core_regs: Number of core registers accessible to GDB or 0 to = infer + * from @gdb_core_xml_file. * @gdb_core_xml_file: File name for core registers GDB XML description. * @gdb_stop_before_watchpoint: Indicates whether GDB expects the CPU to s= top * before the insn which triggers a watchpoint rather than after= it. diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h index 7bea7075e1..83eafbe4b1 100644 --- a/target/s390x/cpu.h +++ b/target/s390x/cpu.h @@ -452,8 +452,6 @@ static inline void cpu_get_tb_cpu_state(CPUS390XState *= env, vaddr *pc, #define S390_R13_REGNUM 15 #define S390_R14_REGNUM 16 #define S390_R15_REGNUM 17 -/* Total Core Registers. */ -#define S390_NUM_CORE_REGS 18 =20 static inline void setcc(S390CPU *cpu, uint64_t cc) { diff --git a/gdbstub/gdbstub.c b/gdbstub/gdbstub.c index 49fb23a68a..c19f1785e4 100644 --- a/gdbstub/gdbstub.c +++ b/gdbstub/gdbstub.c @@ -541,9 +541,12 @@ void gdb_init_cpu(CPUState *cpu) gdb_register_feature(cpu, 0, cc->gdb_read_register, cc->gdb_write_register, feature); + cpu->gdb_num_regs =3D cpu->gdb_num_g_regs =3D feature->num_regs; } =20 - cpu->gdb_num_regs =3D cpu->gdb_num_g_regs =3D cc->gdb_num_core_regs; + if (cc->gdb_num_core_regs) { + cpu->gdb_num_regs =3D cpu->gdb_num_g_regs =3D cc->gdb_num_core_reg= s; + } } =20 void gdb_register_coprocessor(CPUState *cpu, diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 6c6c551573..6d9bf6a14e 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2391,7 +2391,6 @@ static void arm_cpu_class_init(ObjectClass *oc, void = *data) #ifndef CONFIG_USER_ONLY cc->sysemu_ops =3D &arm_sysemu_ops; #endif - cc->gdb_num_core_regs =3D 26; cc->gdb_arch_name =3D arm_gdb_arch_name; cc->gdb_get_dynamic_xml =3D arm_gdb_get_dynamic_xml; cc->gdb_stop_before_watchpoint =3D true; diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 1cb9d5b81a..5c7a4a0bf7 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -792,7 +792,6 @@ static void aarch64_cpu_class_init(ObjectClass *oc, voi= d *data) =20 cc->gdb_read_register =3D aarch64_cpu_gdb_read_register; cc->gdb_write_register =3D aarch64_cpu_gdb_write_register; - cc->gdb_num_core_regs =3D 34; cc->gdb_core_xml_file =3D "aarch64-core.xml"; cc->gdb_arch_name =3D aarch64_gdb_arch_name; =20 diff --git a/target/avr/cpu.c b/target/avr/cpu.c index 14d8b9d1f0..01adfb5089 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -244,7 +244,6 @@ static void avr_cpu_class_init(ObjectClass *oc, void *d= ata) cc->gdb_read_register =3D avr_cpu_gdb_read_register; cc->gdb_write_register =3D avr_cpu_gdb_write_register; cc->gdb_adjust_breakpoint =3D avr_cpu_gdb_adjust_breakpoint; - cc->gdb_num_core_regs =3D 35; cc->gdb_core_xml_file =3D "avr-cpu.xml"; cc->tcg_ops =3D &avr_tcg_ops; } diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index 60d52e1e9d..7c1426f70c 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -385,7 +385,6 @@ static void hexagon_cpu_class_init(ObjectClass *c, void= *data) cc->get_pc =3D hexagon_cpu_get_pc; cc->gdb_read_register =3D hexagon_gdb_read_register; cc->gdb_write_register =3D hexagon_gdb_write_register; - cc->gdb_num_core_regs =3D TOTAL_PER_THREAD_REGS; cc->gdb_stop_before_watchpoint =3D true; cc->gdb_core_xml_file =3D "hexagon-core.xml"; cc->disas_set_info =3D hexagon_cpu_disas_set_info; diff --git a/target/i386/cpu.c b/target/i386/cpu.c index c09bab4281..6452b5439d 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -7967,10 +7967,8 @@ static void x86_cpu_common_class_init(ObjectClass *o= c, void *data) cc->gdb_arch_name =3D x86_gdb_arch_name; #ifdef TARGET_X86_64 cc->gdb_core_xml_file =3D "i386-64bit.xml"; - cc->gdb_num_core_regs =3D 66; #else cc->gdb_core_xml_file =3D "i386-32bit.xml"; - cc->gdb_num_core_regs =3D 50; #endif cc->disas_set_info =3D x86_disas_set_info; =20 diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index ef1bf89dac..1b25920895 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -775,7 +775,6 @@ static void loongarch32_cpu_class_init(ObjectClass *c, = void *data) { CPUClass *cc =3D CPU_CLASS(c); =20 - cc->gdb_num_core_regs =3D 35; cc->gdb_core_xml_file =3D "loongarch-base32.xml"; cc->gdb_arch_name =3D loongarch32_gdb_arch_name; } @@ -789,7 +788,6 @@ static void loongarch64_cpu_class_init(ObjectClass *c, = void *data) { CPUClass *cc =3D CPU_CLASS(c); =20 - cc->gdb_num_core_regs =3D 35; cc->gdb_core_xml_file =3D "loongarch-base64.xml"; cc->gdb_arch_name =3D loongarch64_gdb_arch_name; } diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index 538d9473c2..5fdbe5602b 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -565,7 +565,6 @@ static void m68k_cpu_class_init(ObjectClass *c, void *d= ata) #endif cc->disas_set_info =3D m68k_cpu_disas_set_info; =20 - cc->gdb_num_core_regs =3D 18; cc->tcg_ops =3D &m68k_tcg_ops; } =20 diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 1998f69828..9d3fbfe159 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -428,7 +428,6 @@ static void mb_cpu_class_init(ObjectClass *oc, void *da= ta) cc->sysemu_ops =3D &mb_sysemu_ops; #endif device_class_set_props(dc, mb_properties); - cc->gdb_num_core_regs =3D 32 + 25; cc->gdb_core_xml_file =3D "microblaze-core.xml"; =20 cc->disas_set_info =3D mb_disas_set_info; diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index ce31308366..753d79b70c 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -2244,7 +2244,6 @@ static void riscv_cpu_common_class_init(ObjectClass *= c, void *data) cc->get_pc =3D riscv_cpu_get_pc; cc->gdb_read_register =3D riscv_cpu_gdb_read_register; cc->gdb_write_register =3D riscv_cpu_gdb_write_register; - cc->gdb_num_core_regs =3D 33; cc->gdb_stop_before_watchpoint =3D true; cc->disas_set_info =3D riscv_cpu_disas_set_info; #ifndef CONFIG_USER_ONLY diff --git a/target/rx/cpu.c b/target/rx/cpu.c index 4d0d3a0c8c..7b9e46d1bc 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -235,7 +235,6 @@ static void rx_cpu_class_init(ObjectClass *klass, void = *data) cc->gdb_write_register =3D rx_cpu_gdb_write_register; cc->disas_set_info =3D rx_cpu_disas_set_info; =20 - cc->gdb_num_core_regs =3D 26; cc->gdb_core_xml_file =3D "rx-core.xml"; cc->tcg_ops =3D &rx_tcg_ops; } diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index 6093ab0a12..f49ee0bb46 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -346,7 +346,6 @@ static void s390_cpu_class_init(ObjectClass *oc, void *= data) s390_cpu_class_init_sysemu(cc); #endif cc->disas_set_info =3D s390_cpu_disas_set_info; - cc->gdb_num_core_regs =3D S390_NUM_CORE_REGS; cc->gdb_core_xml_file =3D "s390x-core64.xml"; cc->gdb_arch_name =3D s390_gdb_arch_name; =20 --=20 2.42.0