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[176.170.217.185]) by smtp.gmail.com with ESMTPSA id f22-20020a056402151600b0052febc781bfsm6010828edw.36.2023.10.09.04.03.19 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 09 Oct 2023 04:03:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1696849402; x=1697454202; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=w1sigiR4LmduP3UlaMwnqexR3h3qqvWr4C29unZHhf0=; b=feS1yhHpaN/5U+Bw8svx9lFsQu4zG4Pk9bQtg/uP6dh6UWQQbueHoO6WjIxoXKQ81m UotfSriSUVNh4pHFndcupqUB0qFSKe96CO6xYrC03V5P4kKiReO60S2jNbUYHaXDQw/H Uq1kT5HS0H6BG07jmpq0AVTLaQog1A7f1LeeCgdwQHfVf0PUmPKwZEt7FQvNqaY9hdb0 /9mA+acRi0JETuSmZlyvhhAe+PKZq5IgLo0Hw5OBYO2B2Est2VQOCntJ0+9YK7jXimdC MrBxW+SKhurn2E2p4M328xMIM+Bm5TXoWKOOU+PS74+Js4VJS2BPzxmK27l4737L0ZJO 6tRA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1696849402; x=1697454202; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=w1sigiR4LmduP3UlaMwnqexR3h3qqvWr4C29unZHhf0=; b=aWh9tqG/KlZQnEb0Y1U/IGYJb83cydniLvEscwnMxnC9jbs8d8jAcOdptpOVWngchN xlG/0aNzypv9aPEEzj/rYOjRmH3Xhj98GZkKM0Glo2WquTIIveWV6PmzgFFpAP4C5RjZ ZKk3RYhLkgCUky/pTT/7OfPNRGJz1IC8+FUPJoqEAxnPSpqwAmIpdOk78AJmYrjMwj3P mrn7OX+96IEccsKMJlx8vLzB7PLqalPUtGUsQ1D4TxGZKzI/0O/HzqKoLbcAJ4ECQ0Rl u+zhAdhEqiIgS6lez446kGvDPIxqOXdpiE4Ap2VeGQ0dIT5g/RScCwSXew3mEi4HbU15 DuhQ== X-Gm-Message-State: AOJu0YwVS50p8CRAmwOW5p6TlCXn84wwWydWCHs3I5mX3l863Sp7LMpx FlD5F0Q+v3uaQ+J3Ch+H35JKU/QQqqfnzW13LeM= X-Google-Smtp-Source: AGHT+IGTB5TvG49uVveL5d3xAMI/z69k2NeO2JEO2Qp2YaFn1vMnclHMmnkxW7Dx7nIMpam3RZLDhQ== X-Received: by 2002:a05:6402:1adb:b0:538:7787:2d62 with SMTP id ba27-20020a0564021adb00b0053877872d62mr14085875edb.1.1696849401649; Mon, 09 Oct 2023 04:03:21 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: David Hildenbrand , Weiwei Li , qemu-s390x@nongnu.org, Ilya Leoshkevich , Bin Meng , Alistair Francis , Cameron Esfahani , qemu-ppc@nongnu.org, Daniel Henrique Barboza , qemu-riscv@nongnu.org, Max Filippov , Daniel Henrique Barboza , Palmer Dabbelt , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Liu Zhiwei , Richard Henderson , Thomas Huth , Roman Bolshakov , Nicholas Piggin , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 6/6] target/i386: Use env_archcpu() in simulate_[rdmsr/wrmsr]() Date: Mon, 9 Oct 2023 13:02:39 +0200 Message-ID: <20231009110239.66778-7-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231009110239.66778-1-philmd@linaro.org> References: <20231009110239.66778-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::529; envelope-from=philmd@linaro.org; helo=mail-ed1-x529.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1696849480121100003 When CPUArchState* is available (here CPUX86State*), we can use the fast env_archcpu() macro to get ArchCPU* (here X86CPU*). The QOM cast X86_CPU() macro will be slower when building with --enable-qom-cast-debug. Pass CPUX86State* as argument to simulate_rdmsr / simulate_wrmsr instead of a CPUState* to avoid an extra cast. simulate_rdmsr/simulate_rdmsr(CPUX86State Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Roman Bolshakov Reviewed-by: Zhao Liu Tested-by: Roman Bolshakov --- RFC: Not even build-tested. --- target/i386/hvf/x86_emu.h | 4 ++-- target/i386/hvf/hvf.c | 4 ++-- target/i386/hvf/x86_emu.c | 21 ++++++++++----------- 3 files changed, 14 insertions(+), 15 deletions(-) diff --git a/target/i386/hvf/x86_emu.h b/target/i386/hvf/x86_emu.h index 640da90b30..4b846ba80e 100644 --- a/target/i386/hvf/x86_emu.h +++ b/target/i386/hvf/x86_emu.h @@ -29,8 +29,8 @@ bool exec_instruction(CPUX86State *env, struct x86_decode= *ins); void load_regs(struct CPUState *cpu); void store_regs(struct CPUState *cpu); =20 -void simulate_rdmsr(struct CPUState *cpu); -void simulate_wrmsr(struct CPUState *cpu); +void simulate_rdmsr(CPUX86State *env); +void simulate_wrmsr(CPUX86State *env); =20 target_ulong read_reg(CPUX86State *env, int reg, int size); void write_reg(CPUX86State *env, int reg, target_ulong val, int size); diff --git a/target/i386/hvf/hvf.c b/target/i386/hvf/hvf.c index cb2cd0b02f..20b9ca3ef5 100644 --- a/target/i386/hvf/hvf.c +++ b/target/i386/hvf/hvf.c @@ -591,9 +591,9 @@ int hvf_vcpu_exec(CPUState *cpu) { load_regs(cpu); if (exit_reason =3D=3D EXIT_REASON_RDMSR) { - simulate_rdmsr(cpu); + simulate_rdmsr(env); } else { - simulate_wrmsr(cpu); + simulate_wrmsr(env); } env->eip +=3D ins_len; store_regs(cpu); diff --git a/target/i386/hvf/x86_emu.c b/target/i386/hvf/x86_emu.c index af1f205ecf..b1f8a685d1 100644 --- a/target/i386/hvf/x86_emu.c +++ b/target/i386/hvf/x86_emu.c @@ -663,11 +663,10 @@ static void exec_lods(CPUX86State *env, struct x86_de= code *decode) env->eip +=3D decode->len; } =20 -void simulate_rdmsr(struct CPUState *cpu) +void simulate_rdmsr(CPUX86State *env) { - X86CPU *x86_cpu =3D X86_CPU(cpu); - CPUX86State *env =3D &x86_cpu->env; - CPUState *cs =3D env_cpu(env); + X86CPU *x86_cpu =3D env_archcpu(env); + CPUState *cpu =3D env_cpu(env); uint32_t msr =3D ECX(env); uint64_t val =3D 0; =20 @@ -746,8 +745,8 @@ void simulate_rdmsr(struct CPUState *cpu) val =3D env->mtrr_deftype; break; case MSR_CORE_THREAD_COUNT: - val =3D cs->nr_threads * cs->nr_cores; /* thread count, bits 15..0= */ - val |=3D ((uint32_t)cs->nr_cores << 16); /* core count, bits 31..1= 6 */ + val =3D cpu->nr_threads * cpu->nr_cores; /* thread count, bits 15= ..0 */ + val |=3D ((uint32_t)cpu->nr_cores << 16); /* core count, bits 31..= 16 */ break; default: /* fprintf(stderr, "%s: unknown msr 0x%x\n", __func__, msr); */ @@ -761,14 +760,14 @@ void simulate_rdmsr(struct CPUState *cpu) =20 static void exec_rdmsr(CPUX86State *env, struct x86_decode *decode) { - simulate_rdmsr(env_cpu(env)); + simulate_rdmsr(env); env->eip +=3D decode->len; } =20 -void simulate_wrmsr(struct CPUState *cpu) +void simulate_wrmsr(CPUX86State *env) { - X86CPU *x86_cpu =3D X86_CPU(cpu); - CPUX86State *env =3D &x86_cpu->env; + X86CPU *x86_cpu =3D env_archcpu(env); + CPUState *cpu =3D env_cpu(env); uint32_t msr =3D ECX(env); uint64_t data =3D ((uint64_t)EDX(env) << 32) | EAX(env); =20 @@ -856,7 +855,7 @@ void simulate_wrmsr(struct CPUState *cpu) =20 static void exec_wrmsr(CPUX86State *env, struct x86_decode *decode) { - simulate_wrmsr(env_cpu(env)); + simulate_wrmsr(env); env->eip +=3D decode->len; } =20 --=20 2.41.0