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Tsirkin" , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Paolo Bonzini , Richard Henderson , Bernhard Beschow Subject: [PATCH v8 03/29] hw/i386/pc_piix: Assign PIIX3's ISA interrupts before its realize() Date: Sat, 7 Oct 2023 14:38:11 +0200 Message-ID: <20231007123843.127151-4-shentey@gmail.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231007123843.127151-1-shentey@gmail.com> References: <20231007123843.127151-1-shentey@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::52c; envelope-from=shentey@gmail.com; helo=mail-ed1-x52c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1696682359539100003 Content-Type: text/plain; charset="utf-8" Unlike its PIIX4 counterpart, TYPE_PIIX3_DEVICE doesn't instantiate a PIC itself. Instead, it relies on the board to do so. This means that the board needs to wire the ISA IRQs to the PIIX3 device model. As long as the board assigns the ISA IRQs after PIIX3's realize(), internal devices can't be wir= ed in pci_piix3_realize() since the qemu_irqs are still NULL. Fix that by assigni= ng the ISA interrupts before realize(). This will allow for embedding child de= vices into the host device as already done for PIIX4. Signed-off-by: Bernhard Beschow --- Note that this avoids the "PIC proxy" of previous iterations of the PIIX consolidation series. Assigning the IRQs before realize() has been agreed u= pon at KVM forum 2023. --- hw/i386/pc_piix.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index 6d2f5509e6..a003923788 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -265,6 +265,8 @@ static void pc_init1(MachineState *machine, PCIDevice *pci_dev; =20 pci_dev =3D pci_new_multifunction(-1, TYPE_PIIX3_DEVICE); + piix3 =3D PIIX3_PCI_DEVICE(pci_dev); + piix3->pic =3D x86ms->gsi; pci_realize_and_unref(pci_dev, pci_bus, &error_fatal); =20 if (xen_enabled()) { @@ -281,8 +283,6 @@ static void pc_init1(MachineState *machine, XEN_IOAPIC_NUM_PIRQS); } =20 - piix3 =3D PIIX3_PCI_DEVICE(pci_dev); - piix3->pic =3D x86ms->gsi; piix3_devfn =3D piix3->dev.devfn; isa_bus =3D ISA_BUS(qdev_get_child_bus(DEVICE(piix3), "isa.0")); rtc_state =3D ISA_DEVICE(object_resolve_path_component(OBJECT(pci_= dev), --=20 2.42.0