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[217.94.218.97]) by smtp.gmail.com with ESMTPSA id e27-20020a170906045b00b009b655c43710sm4241401eja.24.2023.10.07.05.39.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 07 Oct 2023 05:39:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1696682362; x=1697287162; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=sPVC6CusdReMTR+Bx+nim29dqNlS7Ej2hd85y0nMUPw=; b=nOxJIX/KVapcRU102tSlluI3G3+7AfZQ2gwoZLEfskUXuhoRUG3XkLNqnIzSxvxjdS 4FRhvi3Pyn9ktLLb8nYE3RIFtLgYGQUF0JoWXwqYYievENmJgXsSlgGIHjaKdRd0eBEv Lv20CunFRGtbSPCFBYCrvU/oCeiLxd6G0su7QghgTphNZiDpaoDOi4vN+2jRPNeAQIqi qLGWKSb3jdWWJUvUOz+ytpjOVfy6vpSOFiRZhWf4akklja0UfIeABZsaZAYFh1Nx+YJk sYambEmVImVETsp29hh/mUhBXNl3vMHUz2GoD0tn3A2iMa6p/BUpGE+jHTbbxkvh2gAl SeUA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1696682362; x=1697287162; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=sPVC6CusdReMTR+Bx+nim29dqNlS7Ej2hd85y0nMUPw=; b=O20JGIAsPO8ju1NW7WxFcILkEWu/GKnLEArK+sIfCUINcDge/EUITJkLwXjQ8eNJBv FXwJHSoa5/MzAAv1N3ekSXpdZvTQWsJ/fhcuTzbEZMID9dunSr4P0JT4sx1mpbmqr9iY wA7rrZ8oE+7pb5toDO17/lQsVyqxS6HURUw3SK98eZMniy7zoDmpmCFKbJS1CRwpvT6/ DJd7HfCTQMpXJ7uMIeXv6F8KeQK64fUKBwshdLgbcOWu1mnQakDlbhbr4jgQFAAvIPEG mjv5OJVbAdwUQ6lZBm2gi7h5vrKssZizYDj/We2thHmX33jbfWmMIn343+kEwnEmUWWP mGsQ== X-Gm-Message-State: AOJu0YyeKhIEqGxxutMDUVsAHnL63UhSxBQ9hY0rKGPDj7D8BLYcYU4P jnW8bede8w2DOdR76gY4mV80WzfvIAI= X-Google-Smtp-Source: AGHT+IGJ6duLZ0GK7DxR7/QmPE3yPkcS36ykB9zSUKXLGNWTCUDO7eIjc1RH/CzCQfWXuRbAJqcsfg== X-Received: by 2002:a17:906:8a43:b0:9ad:be8a:a582 with SMTP id gx3-20020a1709068a4300b009adbe8aa582mr8891389ejc.21.1696682362518; Sat, 07 Oct 2023 05:39:22 -0700 (PDT) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: Chuck Zmudzinski , Marcel Apfelbaum , =?UTF-8?q?Herv=C3=A9=20Poussineau?= , Eduardo Habkost , Aurelien Jarno , "Michael S. Tsirkin" , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Paolo Bonzini , Richard Henderson , Bernhard Beschow Subject: [PATCH v8 26/29] hw/isa/piix: Reuse PIIX3's PCI interrupt triggering in PIIX4 Date: Sat, 7 Oct 2023 14:38:34 +0200 Message-ID: <20231007123843.127151-27-shentey@gmail.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231007123843.127151-1-shentey@gmail.com> References: <20231007123843.127151-1-shentey@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::631; envelope-from=shentey@gmail.com; helo=mail-ej1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1696682491437100004 Content-Type: text/plain; charset="utf-8" Speeds up PIIX4 which resolves an old TODO. Also makes PIIX4 compatible wit= h Xen which relies on pci_bus_fire_intx_routing_notifier() to be fired. Signed-off-by: Bernhard Beschow Reviewed-by: Michael S. Tsirkin --- hw/isa/piix.c | 27 +++------------------------ 1 file changed, 3 insertions(+), 24 deletions(-) diff --git a/hw/isa/piix.c b/hw/isa/piix.c index 449c1baaab..17677c2126 100644 --- a/hw/isa/piix.c +++ b/hw/isa/piix.c @@ -81,27 +81,6 @@ static void piix_set_pci_irq(void *opaque, int pirq, int= level) piix_set_pci_irq_level(s, pirq, level); } =20 -static void piix4_set_irq(void *opaque, int irq_num, int level) -{ - int i, pic_irq, pic_level; - PIIXState *s =3D opaque; - PCIBus *bus =3D pci_get_bus(&s->dev); - - /* now we change the pic irq level according to the piix irq mappings = */ - /* XXX: optimize */ - pic_irq =3D s->dev.config[PIIX_PIRQCA + irq_num]; - if (pic_irq < ISA_NUM_IRQS) { - /* The pic level is the logical OR of all the PCI irqs mapped to i= t. */ - pic_level =3D 0; - for (i =3D 0; i < PIIX_NUM_PIRQS; i++) { - if (pic_irq =3D=3D s->dev.config[PIIX_PIRQCA + i]) { - pic_level |=3D pci_bus_get_irq_level(bus, i); - } - } - qemu_set_irq(s->isa_irqs_in[pic_irq], pic_level); - } -} - static void piix_request_i8259_irq(void *opaque, int irq, int level) { PIIXState *s =3D opaque; @@ -223,7 +202,7 @@ static int piix4_post_load(void *opaque, int version_id) s->rcr =3D 0; } =20 - return 0; + return piix_post_load(opaque, version_id); } =20 static int piix3_pre_save(void *opaque) @@ -442,6 +421,7 @@ static void pci_piix_class_init(ObjectClass *klass, voi= d *data) PCIDeviceClass *k =3D PCI_DEVICE_CLASS(klass); AcpiDevAmlIfClass *adevc =3D ACPI_DEV_AML_IF_CLASS(klass); =20 + k->config_write =3D piix_write_config; dc->reset =3D piix_reset; dc->desc =3D "ISA bridge"; dc->hotpluggable =3D false; @@ -497,7 +477,6 @@ static void piix3_class_init(ObjectClass *klass, void *= data) DeviceClass *dc =3D DEVICE_CLASS(klass); PCIDeviceClass *k =3D PCI_DEVICE_CLASS(klass); =20 - k->config_write =3D piix_write_config; k->realize =3D piix3_realize; /* 82371SB PIIX3 PCI-to-ISA bridge (Step A1) */ k->device_id =3D PCI_DEVICE_ID_INTEL_82371SB_0; @@ -522,7 +501,7 @@ static void piix4_realize(PCIDevice *dev, Error **errp) return; } =20 - pci_bus_irqs(pci_bus, piix4_set_irq, s, PIIX_NUM_PIRQS); + pci_bus_irqs(pci_bus, piix_set_pci_irq, s, PIIX_NUM_PIRQS); } =20 static void piix4_init(Object *obj) --=20 2.42.0