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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: gaosong <gaosong@loongson.cn>
Subject: [PULL 47/47] tcg/loongarch64: Fix buid error
Date: Tue, 3 Oct 2023 10:30:52 -0700
Message-Id: <20231003173052.1601813-48-richard.henderson@linaro.org>
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From: gaosong <gaosong@loongson.cn>
Fix:
In file included from ../tcg/tcg.c:735:
/home1/gaosong/bugfix/qemu/tcg/loongarch64/tcg-target.c.inc: In function =
=E2=80=98tcg_out_vec_op=E2=80=99:
/home1/gaosong/bugfix/qemu/tcg/loongarch64/tcg-target.c.inc:1855:9: error=
: a label can only be part of a statement and a declaration is not a statem=
ent
TCGCond cond =3D args[3];
^~~~~~~
Signed-off-by: gaosong <gaosong@loongson.cn>
Message-Id: <20230926075819.3602537-1-gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/loongarch64/tcg-target.c.inc | 68 ++++++++++++++++----------------
1 file changed, 35 insertions(+), 33 deletions(-)
diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.=
c.inc
index b701df50db..8f7091002b 100644
--- a/tcg/loongarch64/tcg-target.c.inc
+++ b/tcg/loongarch64/tcg-target.c.inc
@@ -1852,43 +1852,45 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode=
opc,
tcg_out_opc_vnor_v(s, a0, a1, a1);
break;
case INDEX_op_cmp_vec:
- TCGCond cond =3D args[3];
- if (const_args[2]) {
- /*
- * cmp_vec dest, src, value
- * Try vseqi/vslei/vslti
- */
- int64_t value =3D sextract64(a2, 0, 8 << vece);
- if ((cond =3D=3D TCG_COND_EQ || cond =3D=3D TCG_COND_LE || \
- cond =3D=3D TCG_COND_LT) && (-0x10 <=3D value && value <=
=3D 0x0f)) {
- tcg_out32(s, encode_vdvjsk5_insn(cmp_vec_imm_insn[cond][ve=
ce], \
- a0, a1, value));
- break;
- } else if ((cond =3D=3D TCG_COND_LEU || cond =3D=3D TCG_COND_L=
TU) &&
- (0x00 <=3D value && value <=3D 0x1f)) {
- tcg_out32(s, encode_vdvjuk5_insn(cmp_vec_imm_insn[cond][ve=
ce], \
- a0, a1, value));
- break;
+ {
+ TCGCond cond =3D args[3];
+ if (const_args[2]) {
+ /*
+ * cmp_vec dest, src, value
+ * Try vseqi/vslei/vslti
+ */
+ int64_t value =3D sextract64(a2, 0, 8 << vece);
+ if ((cond =3D=3D TCG_COND_EQ || cond =3D=3D TCG_COND_LE ||=
\
+ cond =3D=3D TCG_COND_LT) && (-0x10 <=3D value && valu=
e <=3D 0x0f)) {
+ tcg_out32(s, encode_vdvjsk5_insn(cmp_vec_imm_insn[cond=
][vece], \
+ a0, a1, value));
+ break;
+ } else if ((cond =3D=3D TCG_COND_LEU || cond =3D=3D TCG_CO=
ND_LTU) &&
+ (0x00 <=3D value && value <=3D 0x1f)) {
+ tcg_out32(s, encode_vdvjuk5_insn(cmp_vec_imm_insn[cond=
][vece], \
+ a0, a1, value));
+ break;
+ }
+
+ /*
+ * Fallback to:
+ * dupi_vec temp, a2
+ * cmp_vec a0, a1, temp, cond
+ */
+ tcg_out_dupi_vec(s, type, vece, temp_vec, a2);
+ a2 =3D temp_vec;
}
=20
- /*
- * Fallback to:
- * dupi_vec temp, a2
- * cmp_vec a0, a1, temp, cond
- */
- tcg_out_dupi_vec(s, type, vece, temp_vec, a2);
- a2 =3D temp_vec;
- }
-
- insn =3D cmp_vec_insn[cond][vece];
- if (insn =3D=3D 0) {
- TCGArg t;
- t =3D a1, a1 =3D a2, a2 =3D t;
- cond =3D tcg_swap_cond(cond);
insn =3D cmp_vec_insn[cond][vece];
- tcg_debug_assert(insn !=3D 0);
+ if (insn =3D=3D 0) {
+ TCGArg t;
+ t =3D a1, a1 =3D a2, a2 =3D t;
+ cond =3D tcg_swap_cond(cond);
+ insn =3D cmp_vec_insn[cond][vece];
+ tcg_debug_assert(insn !=3D 0);
+ }
+ tcg_out32(s, encode_vdvjvk_insn(insn, a0, a1, a2));
}
- tcg_out32(s, encode_vdvjvk_insn(insn, a0, a1, a2));
break;
case INDEX_op_add_vec:
tcg_out_addsub_vec(s, vece, a0, a1, a2, const_args[2], true);
--=20
2.34.1