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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: Anton Johansson <anjo@rev.ng>,
=?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= <philmd@linaro.org>
Subject: [PULL 24/47] accel/tcg: Modify probe_access_internal() to use
CPUState
Date: Tue, 3 Oct 2023 10:30:29 -0700
Message-Id: <20231003173052.1601813-25-richard.henderson@linaro.org>
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From: Anton Johansson <anjo@rev.ng>
probe_access_internal() is changed to instead take the generic CPUState
over CPUArchState, in order to lessen the target-specific coupling of
cputlb.c. Note: probe_access*() also don't need the full CPUArchState,
but aren't touched in this patch as they are target-facing.
Signed-off-by: Anton Johansson <anjo@rev.ng>
Message-Id: <20230912153428.17816-5-anjo@rev.ng>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daud=C3=A9 <philmd@linaro.org>
[rth: Use cpu->neg.tlb instead of cpu_tlb()]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
accel/tcg/cputlb.c | 46 +++++++++++++++++++++++-----------------------
1 file changed, 23 insertions(+), 23 deletions(-)
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index f88c394594..ab52afb3f3 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -1432,27 +1432,24 @@ static void notdirty_write(CPUState *cpu, vaddr mem=
_vaddr, unsigned size,
}
}
=20
-static int probe_access_internal(CPUArchState *env, vaddr addr,
+static int probe_access_internal(CPUState *cpu, vaddr addr,
int fault_size, MMUAccessType access_type,
int mmu_idx, bool nonfault,
void **phost, CPUTLBEntryFull **pfull,
uintptr_t retaddr, bool check_mem_cbs)
{
- uintptr_t index =3D tlb_index(env_cpu(env), mmu_idx, addr);
- CPUTLBEntry *entry =3D tlb_entry(env_cpu(env), mmu_idx, addr);
+ uintptr_t index =3D tlb_index(cpu, mmu_idx, addr);
+ CPUTLBEntry *entry =3D tlb_entry(cpu, mmu_idx, addr);
uint64_t tlb_addr =3D tlb_read_idx(entry, access_type);
vaddr page_addr =3D addr & TARGET_PAGE_MASK;
int flags =3D TLB_FLAGS_MASK & ~TLB_FORCE_SLOW;
- bool force_mmio =3D check_mem_cbs && cpu_plugin_mem_cbs_enabled(env_cp=
u(env));
+ bool force_mmio =3D check_mem_cbs && cpu_plugin_mem_cbs_enabled(cpu);
CPUTLBEntryFull *full;
=20
if (!tlb_hit_page(tlb_addr, page_addr)) {
- if (!victim_tlb_hit(env_cpu(env), mmu_idx, index,
- access_type, page_addr)) {
- CPUState *cs =3D env_cpu(env);
-
- if (!cs->cc->tcg_ops->tlb_fill(cs, addr, fault_size, access_ty=
pe,
- mmu_idx, nonfault, retaddr)) {
+ if (!victim_tlb_hit(cpu, mmu_idx, index, access_type, page_addr)) {
+ if (!cpu->cc->tcg_ops->tlb_fill(cpu, addr, fault_size, access_=
type,
+ mmu_idx, nonfault, retaddr)) {
/* Non-faulting page table read failed. */
*phost =3D NULL;
*pfull =3D NULL;
@@ -1460,8 +1457,8 @@ static int probe_access_internal(CPUArchState *env, v=
addr addr,
}
=20
/* TLB resize via tlb_fill may have moved the entry. */
- index =3D tlb_index(env_cpu(env), mmu_idx, addr);
- entry =3D tlb_entry(env_cpu(env), mmu_idx, addr);
+ index =3D tlb_index(cpu, mmu_idx, addr);
+ entry =3D tlb_entry(cpu, mmu_idx, addr);
=20
/*
* With PAGE_WRITE_INV, we set TLB_INVALID_MASK immediately,
@@ -1474,7 +1471,7 @@ static int probe_access_internal(CPUArchState *env, v=
addr addr,
}
flags &=3D tlb_addr;
=20
- *pfull =3D full =3D &env_tlb(env)->d[mmu_idx].fulltlb[index];
+ *pfull =3D full =3D &cpu->neg.tlb.d[mmu_idx].fulltlb[index];
flags |=3D full->slow_flags[access_type];
=20
/* Fold all "mmio-like" bits into TLB_MMIO. This is not RAM. */
@@ -1495,8 +1492,9 @@ int probe_access_full(CPUArchState *env, vaddr addr, =
int size,
bool nonfault, void **phost, CPUTLBEntryFull **pfull,
uintptr_t retaddr)
{
- int flags =3D probe_access_internal(env, addr, size, access_type, mmu_=
idx,
- nonfault, phost, pfull, retaddr, tru=
e);
+ int flags =3D probe_access_internal(env_cpu(env), addr, size, access_t=
ype,
+ mmu_idx, nonfault, phost, pfull, ret=
addr,
+ true);
=20
/* Handle clean RAM pages. */
if (unlikely(flags & TLB_NOTDIRTY)) {
@@ -1518,8 +1516,8 @@ int probe_access_full_mmu(CPUArchState *env, vaddr ad=
dr, int size,
phost =3D phost ? phost : &discard_phost;
pfull =3D pfull ? pfull : &discard_tlb;
=20
- int flags =3D probe_access_internal(env, addr, size, access_type, mmu_=
idx,
- true, phost, pfull, 0, false);
+ int flags =3D probe_access_internal(env_cpu(env), addr, size, access_t=
ype,
+ mmu_idx, true, phost, pfull, 0, fals=
e);
=20
/* Handle clean RAM pages. */
if (unlikely(flags & TLB_NOTDIRTY)) {
@@ -1539,8 +1537,9 @@ int probe_access_flags(CPUArchState *env, vaddr addr,=
int size,
=20
g_assert(-(addr | TARGET_PAGE_MASK) >=3D size);
=20
- flags =3D probe_access_internal(env, addr, size, access_type, mmu_idx,
- nonfault, phost, &full, retaddr, true);
+ flags =3D probe_access_internal(env_cpu(env), addr, size, access_type,
+ mmu_idx, nonfault, phost, &full, retaddr,
+ true);
=20
/* Handle clean RAM pages. */
if (unlikely(flags & TLB_NOTDIRTY)) {
@@ -1560,8 +1559,9 @@ void *probe_access(CPUArchState *env, vaddr addr, int=
size,
=20
g_assert(-(addr | TARGET_PAGE_MASK) >=3D size);
=20
- flags =3D probe_access_internal(env, addr, size, access_type, mmu_idx,
- false, &host, &full, retaddr, true);
+ flags =3D probe_access_internal(env_cpu(env), addr, size, access_type,
+ mmu_idx, false, &host, &full, retaddr,
+ true);
=20
/* Per the interface, size =3D=3D 0 merely faults the access. */
if (size =3D=3D 0) {
@@ -1593,7 +1593,7 @@ void *tlb_vaddr_to_host(CPUArchState *env, abi_ptr ad=
dr,
void *host;
int flags;
=20
- flags =3D probe_access_internal(env, addr, 0, access_type,
+ flags =3D probe_access_internal(env_cpu(env), addr, 0, access_type,
mmu_idx, true, &host, &full, 0, false);
=20
/* No combination of flags are expected by the caller. */
@@ -1616,7 +1616,7 @@ tb_page_addr_t get_page_addr_code_hostp(CPUArchState =
*env, vaddr addr,
CPUTLBEntryFull *full;
void *p;
=20
- (void)probe_access_internal(env, addr, 1, MMU_INST_FETCH,
+ (void)probe_access_internal(env_cpu(env), addr, 1, MMU_INST_FETCH,
cpu_mmu_index(env, true), false,
&p, &full, 0, false);
if (p =3D=3D NULL) {
--=20
2.34.1