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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= <philmd@linaro.org>
Subject: [PULL 12/47] target/*: Add instance_align to all cpu base classes
Date: Tue, 3 Oct 2023 10:30:17 -0700
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The omission of alignment has technically been wrong since
269bd5d8f61, where QEMU_ALIGNED was added to CPUTLBDescFast.
Reviewed-by: Philippe Mathieu-Daud=C3=A9 <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/alpha/cpu.c | 1 +
target/avr/cpu.c | 1 +
target/cris/cpu.c | 1 +
target/hexagon/cpu.c | 1 +
target/hppa/cpu.c | 1 +
target/i386/cpu.c | 1 +
target/loongarch/cpu.c | 1 +
target/m68k/cpu.c | 1 +
target/microblaze/cpu.c | 1 +
target/mips/cpu.c | 1 +
target/nios2/cpu.c | 1 +
target/openrisc/cpu.c | 1 +
target/riscv/cpu.c | 2 +-
target/rx/cpu.c | 1 +
target/sh4/cpu.c | 1 +
target/sparc/cpu.c | 1 +
target/tricore/cpu.c | 1 +
target/xtensa/cpu.c | 1 +
18 files changed, 18 insertions(+), 1 deletion(-)
diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c
index 270ae787b1..e2156fcb41 100644
--- a/target/alpha/cpu.c
+++ b/target/alpha/cpu.c
@@ -286,6 +286,7 @@ static const TypeInfo alpha_cpu_type_infos[] =3D {
.name =3D TYPE_ALPHA_CPU,
.parent =3D TYPE_CPU,
.instance_size =3D sizeof(AlphaCPU),
+ .instance_align =3D __alignof(AlphaCPU),
.instance_init =3D alpha_cpu_initfn,
.abstract =3D true,
.class_size =3D sizeof(AlphaCPUClass),
diff --git a/target/avr/cpu.c b/target/avr/cpu.c
index 8f741f258c..c5a6436336 100644
--- a/target/avr/cpu.c
+++ b/target/avr/cpu.c
@@ -390,6 +390,7 @@ static const TypeInfo avr_cpu_type_info[] =3D {
.name =3D TYPE_AVR_CPU,
.parent =3D TYPE_CPU,
.instance_size =3D sizeof(AVRCPU),
+ .instance_align =3D __alignof(AVRCPU),
.instance_init =3D avr_cpu_initfn,
.class_size =3D sizeof(AVRCPUClass),
.class_init =3D avr_cpu_class_init,
diff --git a/target/cris/cpu.c b/target/cris/cpu.c
index a6a93c2359..8ab8a30b8d 100644
--- a/target/cris/cpu.c
+++ b/target/cris/cpu.c
@@ -345,6 +345,7 @@ static const TypeInfo cris_cpu_model_type_infos[] =3D {
.name =3D TYPE_CRIS_CPU,
.parent =3D TYPE_CPU,
.instance_size =3D sizeof(CRISCPU),
+ .instance_align =3D __alignof(CRISCPU),
.instance_init =3D cris_cpu_initfn,
.abstract =3D true,
.class_size =3D sizeof(CRISCPUClass),
diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c
index f155936289..65f198b956 100644
--- a/target/hexagon/cpu.c
+++ b/target/hexagon/cpu.c
@@ -408,6 +408,7 @@ static const TypeInfo hexagon_cpu_type_infos[] =3D {
.name =3D TYPE_HEXAGON_CPU,
.parent =3D TYPE_CPU,
.instance_size =3D sizeof(HexagonCPU),
+ .instance_align =3D __alignof(HexagonCPU),
.instance_init =3D hexagon_cpu_init,
.abstract =3D true,
.class_size =3D sizeof(HexagonCPUClass),
diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c
index 11022f9c99..17fa901f6a 100644
--- a/target/hppa/cpu.c
+++ b/target/hppa/cpu.c
@@ -212,6 +212,7 @@ static const TypeInfo hppa_cpu_type_info =3D {
.name =3D TYPE_HPPA_CPU,
.parent =3D TYPE_CPU,
.instance_size =3D sizeof(HPPACPU),
+ .instance_align =3D __alignof(HPPACPU),
.instance_init =3D hppa_cpu_initfn,
.abstract =3D false,
.class_size =3D sizeof(HPPACPUClass),
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index ed72883bf3..187ebb0dbc 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -8022,6 +8022,7 @@ static const TypeInfo x86_cpu_type_info =3D {
.name =3D TYPE_X86_CPU,
.parent =3D TYPE_CPU,
.instance_size =3D sizeof(X86CPU),
+ .instance_align =3D __alignof(X86CPU),
.instance_init =3D x86_cpu_initfn,
.instance_post_init =3D x86_cpu_post_initfn,
=20
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index fc7f70fbe5..d5e403bbb7 100644
--- a/target/loongarch/cpu.c
+++ b/target/loongarch/cpu.c
@@ -808,6 +808,7 @@ static const TypeInfo loongarch_cpu_type_infos[] =3D {
.name =3D TYPE_LOONGARCH_CPU,
.parent =3D TYPE_CPU,
.instance_size =3D sizeof(LoongArchCPU),
+ .instance_align =3D __alignof(LoongArchCPU),
.instance_init =3D loongarch_cpu_init,
=20
.abstract =3D true,
diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c
index 70d58471dc..d34d1b57d0 100644
--- a/target/m68k/cpu.c
+++ b/target/m68k/cpu.c
@@ -611,6 +611,7 @@ static const TypeInfo m68k_cpus_type_infos[] =3D {
.name =3D TYPE_M68K_CPU,
.parent =3D TYPE_CPU,
.instance_size =3D sizeof(M68kCPU),
+ .instance_align =3D __alignof(M68kCPU),
.instance_init =3D m68k_cpu_initfn,
.abstract =3D true,
.class_size =3D sizeof(M68kCPUClass),
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
index 03c2c4db1f..c53711da52 100644
--- a/target/microblaze/cpu.c
+++ b/target/microblaze/cpu.c
@@ -439,6 +439,7 @@ static const TypeInfo mb_cpu_type_info =3D {
.name =3D TYPE_MICROBLAZE_CPU,
.parent =3D TYPE_CPU,
.instance_size =3D sizeof(MicroBlazeCPU),
+ .instance_align =3D __alignof(MicroBlazeCPU),
.instance_init =3D mb_cpu_initfn,
.class_size =3D sizeof(MicroBlazeCPUClass),
.class_init =3D mb_cpu_class_init,
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index 63da1948fd..fee791aa44 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -600,6 +600,7 @@ static const TypeInfo mips_cpu_type_info =3D {
.name =3D TYPE_MIPS_CPU,
.parent =3D TYPE_CPU,
.instance_size =3D sizeof(MIPSCPU),
+ .instance_align =3D __alignof(MIPSCPU),
.instance_init =3D mips_cpu_initfn,
.abstract =3D true,
.class_size =3D sizeof(MIPSCPUClass),
diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c
index bc5cbf81c2..598976305f 100644
--- a/target/nios2/cpu.c
+++ b/target/nios2/cpu.c
@@ -400,6 +400,7 @@ static const TypeInfo nios2_cpu_type_info =3D {
.name =3D TYPE_NIOS2_CPU,
.parent =3D TYPE_CPU,
.instance_size =3D sizeof(Nios2CPU),
+ .instance_align =3D __alignof(Nios2CPU),
.instance_init =3D nios2_cpu_initfn,
.class_size =3D sizeof(Nios2CPUClass),
.class_init =3D nios2_cpu_class_init,
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c
index 61d748cfdc..be067709b8 100644
--- a/target/openrisc/cpu.c
+++ b/target/openrisc/cpu.c
@@ -314,6 +314,7 @@ static const TypeInfo openrisc_cpus_type_infos[] =3D {
.name =3D TYPE_OPENRISC_CPU,
.parent =3D TYPE_CPU,
.instance_size =3D sizeof(OpenRISCCPU),
+ .instance_align =3D __alignof(OpenRISCCPU),
.instance_init =3D openrisc_cpu_initfn,
.abstract =3D true,
.class_size =3D sizeof(OpenRISCCPUClass),
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 4140899c52..d69c40d380 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -2314,7 +2314,7 @@ static const TypeInfo riscv_cpu_type_infos[] =3D {
.name =3D TYPE_RISCV_CPU,
.parent =3D TYPE_CPU,
.instance_size =3D sizeof(RISCVCPU),
- .instance_align =3D __alignof__(RISCVCPU),
+ .instance_align =3D __alignof(RISCVCPU),
.instance_init =3D riscv_cpu_init,
.abstract =3D true,
.class_size =3D sizeof(RISCVCPUClass),
diff --git a/target/rx/cpu.c b/target/rx/cpu.c
index 157e57da0f..51559943fb 100644
--- a/target/rx/cpu.c
+++ b/target/rx/cpu.c
@@ -248,6 +248,7 @@ static const TypeInfo rx_cpu_info =3D {
.name =3D TYPE_RX_CPU,
.parent =3D TYPE_CPU,
.instance_size =3D sizeof(RXCPU),
+ .instance_align =3D __alignof(RXCPU),
.instance_init =3D rx_cpu_init,
.abstract =3D true,
.class_size =3D sizeof(RXCPUClass),
diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c
index 61769ffdfa..a90e41c4ec 100644
--- a/target/sh4/cpu.c
+++ b/target/sh4/cpu.c
@@ -315,6 +315,7 @@ static const TypeInfo superh_cpu_type_infos[] =3D {
.name =3D TYPE_SUPERH_CPU,
.parent =3D TYPE_CPU,
.instance_size =3D sizeof(SuperHCPU),
+ .instance_align =3D __alignof(SuperHCPU),
.instance_init =3D superh_cpu_initfn,
.abstract =3D true,
.class_size =3D sizeof(SuperHCPUClass),
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
index 130ab8f578..d6d3c4b031 100644
--- a/target/sparc/cpu.c
+++ b/target/sparc/cpu.c
@@ -930,6 +930,7 @@ static const TypeInfo sparc_cpu_type_info =3D {
.name =3D TYPE_SPARC_CPU,
.parent =3D TYPE_CPU,
.instance_size =3D sizeof(SPARCCPU),
+ .instance_align =3D __alignof(SPARCCPU),
.instance_init =3D sparc_cpu_initfn,
.abstract =3D true,
.class_size =3D sizeof(SPARCCPUClass),
diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c
index 133a9ac70e..50aec6cf10 100644
--- a/target/tricore/cpu.c
+++ b/target/tricore/cpu.c
@@ -230,6 +230,7 @@ static const TypeInfo tricore_cpu_type_infos[] =3D {
.name =3D TYPE_TRICORE_CPU,
.parent =3D TYPE_CPU,
.instance_size =3D sizeof(TriCoreCPU),
+ .instance_align =3D __alignof(TriCoreCPU),
.instance_init =3D tricore_cpu_initfn,
.abstract =3D true,
.class_size =3D sizeof(TriCoreCPUClass),
diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c
index acaf8c905f..281872d7ca 100644
--- a/target/xtensa/cpu.c
+++ b/target/xtensa/cpu.c
@@ -273,6 +273,7 @@ static const TypeInfo xtensa_cpu_type_info =3D {
.name =3D TYPE_XTENSA_CPU,
.parent =3D TYPE_CPU,
.instance_size =3D sizeof(XtensaCPU),
+ .instance_align =3D __alignof(XtensaCPU),
.instance_init =3D xtensa_cpu_initfn,
.abstract =3D true,
.class_size =3D sizeof(XtensaCPUClass),
--=20
2.34.1