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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= <philmd@linaro.org>
Subject: [PULL 11/47] target/arm: Remove size and alignment for cpu subclasses
Date: Tue, 3 Oct 2023 10:30:16 -0700
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Inherit the size and alignment from TYPE_ARM_CPU.
Reviewed-by: Philippe Mathieu-Daud=C3=A9 <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/cpu.c | 3 ---
target/arm/cpu64.c | 4 ----
2 files changed, 7 deletions(-)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index b9e09a702d..d48a70c039 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -2423,10 +2423,7 @@ void arm_cpu_register(const ARMCPUInfo *info)
{
TypeInfo type_info =3D {
.parent =3D TYPE_ARM_CPU,
- .instance_size =3D sizeof(ARMCPU),
- .instance_align =3D __alignof__(ARMCPU),
.instance_init =3D arm_cpu_instance_init,
- .class_size =3D sizeof(ARMCPUClass),
.class_init =3D info->class_init ?: cpu_register_class_init,
.class_data =3D (void *)info,
};
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index f3d87e001f..811f3b38c2 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -822,9 +822,7 @@ void aarch64_cpu_register(const ARMCPUInfo *info)
{
TypeInfo type_info =3D {
.parent =3D TYPE_AARCH64_CPU,
- .instance_size =3D sizeof(ARMCPU),
.instance_init =3D aarch64_cpu_instance_init,
- .class_size =3D sizeof(ARMCPUClass),
.class_init =3D info->class_init ?: cpu_register_class_init,
.class_data =3D (void *)info,
};
@@ -837,10 +835,8 @@ void aarch64_cpu_register(const ARMCPUInfo *info)
static const TypeInfo aarch64_cpu_type_info =3D {
.name =3D TYPE_AARCH64_CPU,
.parent =3D TYPE_ARM_CPU,
- .instance_size =3D sizeof(ARMCPU),
.instance_finalize =3D aarch64_cpu_finalizefn,
.abstract =3D true,
- .class_size =3D sizeof(AArch64CPUClass),
.class_init =3D aarch64_cpu_class_init,
};
=20
--=20
2.34.1