From nobody Fri May 17 10:34:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1695646719003131.3732641887908; Mon, 25 Sep 2023 05:58:39 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qkl8t-0008Mq-Ay; Mon, 25 Sep 2023 08:56:51 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qkdju-0001eS-5e for qemu-devel@nongnu.org; Mon, 25 Sep 2023 01:02:35 -0400 Received: from mta01.start.ca ([162.250.196.97]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qkdjq-0004mY-Us for qemu-devel@nongnu.org; Mon, 25 Sep 2023 01:02:33 -0400 Received: from mta01.start.ca (localhost [127.0.0.1]) by mta01.start.ca (Postfix) with ESMTP id 7784E20763; Mon, 25 Sep 2023 01:02:29 -0400 (EDT) Received: from localhost (dhcp-24-53-241-2.cable.user.start.ca [24.53.241.2]) by mta01.start.ca (Postfix) with ESMTPS id 51C9C20712; Mon, 25 Sep 2023 01:02:29 -0400 (EDT) From: Nick Bowler To: qemu-devel@nongnu.org Cc: Mark Cave-Ayland , Artyom Tarasenko Subject: [PATCH 1/8] target/sparc: Fix VIS fmul8x16 input register. Date: Mon, 25 Sep 2023 01:03:50 -0400 Message-ID: <20230925050545.30912-2-nbowler@draconx.ca> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230925050545.30912-1-nbowler@draconx.ca> References: <20230925050545.30912-1-nbowler@draconx.ca> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Virus-Scanned: ClamAV using ClamSMTP Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=162.250.196.97; envelope-from=nbowler@draconx.ca; helo=mta01.start.ca X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Mon, 25 Sep 2023 08:56:43 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1695646720893100004 Content-Type: text/plain; charset="utf-8" On a real UltraSparc II CPU, the fmul8x16 instruction reads its first input from any of the single-precision floating point registers. But the emulator is reading the input as if the first operand encodes a double-precision register, which in most cases will not contain the right data and therefore the output of the emulated instruction is just garbage. Signed-off-by: Nick Bowler Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1901 Acked-by: Mark Cave-Ayland Reviewed-by: Richard Henderson --- target/sparc/helper.h | 2 +- target/sparc/translate.c | 6 +++++- target/sparc/vis_helper.c | 9 +++++---- 3 files changed, 11 insertions(+), 6 deletions(-) diff --git a/target/sparc/helper.h b/target/sparc/helper.h index b8f1e78c75..ace731a22c 100644 --- a/target/sparc/helper.h +++ b/target/sparc/helper.h @@ -126,7 +126,7 @@ DEF_HELPER_FLAGS_2(fdtox, TCG_CALL_NO_RWG, s64, env, f6= 4) DEF_HELPER_FLAGS_1(fqtox, TCG_CALL_NO_RWG, s64, env) =20 DEF_HELPER_FLAGS_2(fpmerge, TCG_CALL_NO_RWG_SE, i64, i64, i64) -DEF_HELPER_FLAGS_2(fmul8x16, TCG_CALL_NO_RWG_SE, i64, i64, i64) +DEF_HELPER_FLAGS_2(fmul8x16, TCG_CALL_NO_RWG_SE, i64, i32, i64) DEF_HELPER_FLAGS_2(fmul8x16al, TCG_CALL_NO_RWG_SE, i64, i64, i64) DEF_HELPER_FLAGS_2(fmul8x16au, TCG_CALL_NO_RWG_SE, i64, i64, i64) DEF_HELPER_FLAGS_2(fmul8sux16, TCG_CALL_NO_RWG_SE, i64, i64, i64) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 3bf0ab8135..bb65b8daf8 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -4750,7 +4750,11 @@ static void disas_sparc_insn(DisasContext * dc, unsi= gned int insn) break; case 0x031: /* VIS I fmul8x16 */ CHECK_FPU_FEATURE(dc, VIS1); - gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmul8x16); + cpu_src1_32 =3D gen_load_fpr_F(dc, rs1); + cpu_src2_64 =3D gen_load_fpr_D(dc, rs2); + cpu_dst_64 =3D gen_dest_fpr_D(dc, rd); + gen_helper_fmul8x16(cpu_dst_64, cpu_src1_32, cpu_src2_= 64); + gen_store_fpr_D(dc, rd, cpu_dst_64); break; case 0x033: /* VIS I fmul8x16au */ CHECK_FPU_FEATURE(dc, VIS1); diff --git a/target/sparc/vis_helper.c b/target/sparc/vis_helper.c index 3afdc6975c..d158b39b85 100644 --- a/target/sparc/vis_helper.c +++ b/target/sparc/vis_helper.c @@ -94,16 +94,17 @@ uint64_t helper_fpmerge(uint64_t src1, uint64_t src2) return d.ll; } =20 -uint64_t helper_fmul8x16(uint64_t src1, uint64_t src2) +uint64_t helper_fmul8x16(uint32_t src1, uint64_t src2) { - VIS64 s, d; + VIS32 s; + VIS64 d; uint32_t tmp; =20 - s.ll =3D src1; + s.l =3D src1; d.ll =3D src2; =20 #define PMUL(r) \ - tmp =3D (int32_t)d.VIS_SW64(r) * (int32_t)s.VIS_B64(r); \ + tmp =3D (int32_t)d.VIS_SW64(r) * (int32_t)s.VIS_B32(r); \ if ((tmp & 0xff) > 0x7f) { \ tmp +=3D 0x100; \ } \ --=20 2.41.0 From nobody Fri May 17 10:34:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1695646706793188.81260672835595; Mon, 25 Sep 2023 05:58:26 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qkl8n-0008K7-Il; Mon, 25 Sep 2023 08:56:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qkdjs-0001e7-7x for qemu-devel@nongnu.org; Mon, 25 Sep 2023 01:02:32 -0400 Received: from mta01.start.ca ([162.250.196.97]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qkdjq-0004mi-O0 for qemu-devel@nongnu.org; Mon, 25 Sep 2023 01:02:32 -0400 Received: from mta01.start.ca (localhost [127.0.0.1]) by mta01.start.ca (Postfix) with ESMTP id D654C20764; Mon, 25 Sep 2023 01:02:29 -0400 (EDT) Received: from localhost (dhcp-24-53-241-2.cable.user.start.ca [24.53.241.2]) by mta01.start.ca (Postfix) with ESMTPS id B14F620712; Mon, 25 Sep 2023 01:02:29 -0400 (EDT) From: Nick Bowler To: qemu-devel@nongnu.org Cc: Mark Cave-Ayland , Artyom Tarasenko Subject: [PATCH 2/8] target/sparc: Fix VIS fmul8x16au instruction. Date: Mon, 25 Sep 2023 01:03:51 -0400 Message-ID: <20230925050545.30912-3-nbowler@draconx.ca> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230925050545.30912-1-nbowler@draconx.ca> References: <20230925050545.30912-1-nbowler@draconx.ca> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Virus-Scanned: ClamAV using ClamSMTP Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=162.250.196.97; envelope-from=nbowler@draconx.ca; helo=mta01.start.ca X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Mon, 25 Sep 2023 08:56:43 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1695646707128100005 Content-Type: text/plain; charset="utf-8" On a real UltraSparc II, the fmul8x16au instruction takes two single- precision input operands and returns a double-precision result. For the second operand, bits 31:16 are used, and bits 15:0 are ignored. However, the emulation is taking two double-precision input operands, and furthermore it is using bits 15:0 of the second operand (ignoring bits 31:16). These are unlikely to contain the correct values. Even still, the emulator overwrites the second input before all outputs are calculated, so even if by chance the data loaded in happens to be correct, the results are just garbage except in trivial cases. Signed-off-by: Nick Bowler Acked-by: Mark Cave-Ayland Reviewed-by: Richard Henderson --- target/sparc/helper.h | 2 +- target/sparc/translate.c | 19 ++++++++++++++++++- target/sparc/vis_helper.c | 14 +++++++++----- 3 files changed, 28 insertions(+), 7 deletions(-) diff --git a/target/sparc/helper.h b/target/sparc/helper.h index ace731a22c..76e06b8ea5 100644 --- a/target/sparc/helper.h +++ b/target/sparc/helper.h @@ -128,7 +128,7 @@ DEF_HELPER_FLAGS_1(fqtox, TCG_CALL_NO_RWG, s64, env) DEF_HELPER_FLAGS_2(fpmerge, TCG_CALL_NO_RWG_SE, i64, i64, i64) DEF_HELPER_FLAGS_2(fmul8x16, TCG_CALL_NO_RWG_SE, i64, i32, i64) DEF_HELPER_FLAGS_2(fmul8x16al, TCG_CALL_NO_RWG_SE, i64, i64, i64) -DEF_HELPER_FLAGS_2(fmul8x16au, TCG_CALL_NO_RWG_SE, i64, i64, i64) +DEF_HELPER_FLAGS_2(fmul8x16au, TCG_CALL_NO_RWG_SE, i64, i32, i32) DEF_HELPER_FLAGS_2(fmul8sux16, TCG_CALL_NO_RWG_SE, i64, i64, i64) DEF_HELPER_FLAGS_2(fmul8ulx16, TCG_CALL_NO_RWG_SE, i64, i64, i64) DEF_HELPER_FLAGS_2(fmuld8sux16, TCG_CALL_NO_RWG_SE, i64, i64, i64) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index bb65b8daf8..ca81b35a25 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -1786,6 +1786,23 @@ static void gen_fop_DFF(DisasContext *dc, int rd, in= t rs1, int rs2, gen_store_fpr_D(dc, rd, dst); } =20 +#ifdef TARGET_SPARC64 +static void gen_ne_fop_DFF(DisasContext *dc, int rd, int rs1, int rs2, + void (*gen)(TCGv_i64, TCGv_i32, TCGv_i32)) +{ + TCGv_i64 dst; + TCGv_i32 src1, src2; + + src1 =3D gen_load_fpr_F(dc, rs1); + src2 =3D gen_load_fpr_F(dc, rs2); + dst =3D gen_dest_fpr_D(dc, rd); + + gen(dst, src1, src2); + + gen_store_fpr_D(dc, rd, dst); +} +#endif + static void gen_fop_QDD(DisasContext *dc, int rd, int rs1, int rs2, void (*gen)(TCGv_ptr, TCGv_i64, TCGv_i64)) { @@ -4758,7 +4775,7 @@ static void disas_sparc_insn(DisasContext * dc, unsig= ned int insn) break; case 0x033: /* VIS I fmul8x16au */ CHECK_FPU_FEATURE(dc, VIS1); - gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmul8x16au= ); + gen_ne_fop_DFF(dc, rd, rs1, rs2, gen_helper_fmul8x16au= ); break; case 0x035: /* VIS I fmul8x16al */ CHECK_FPU_FEATURE(dc, VIS1); diff --git a/target/sparc/vis_helper.c b/target/sparc/vis_helper.c index d158b39b85..2fc783a054 100644 --- a/target/sparc/vis_helper.c +++ b/target/sparc/vis_helper.c @@ -49,6 +49,7 @@ target_ulong helper_array8(target_ulong pixel_addr, targe= t_ulong cubesize) #define VIS_L64(n) l[1 - (n)] #define VIS_B32(n) b[3 - (n)] #define VIS_W32(n) w[1 - (n)] +#define VIS_SW32(n) sw[1 - (n)] #else #define VIS_B64(n) b[n] #define VIS_W64(n) w[n] @@ -56,6 +57,7 @@ target_ulong helper_array8(target_ulong pixel_addr, targe= t_ulong cubesize) #define VIS_L64(n) l[n] #define VIS_B32(n) b[n] #define VIS_W32(n) w[n] +#define VIS_SW32(n) sw[n] #endif =20 typedef union { @@ -70,6 +72,7 @@ typedef union { typedef union { uint8_t b[4]; uint16_t w[2]; + int16_t sw[2]; uint32_t l; float32 f; } VIS32; @@ -143,16 +146,17 @@ uint64_t helper_fmul8x16al(uint64_t src1, uint64_t sr= c2) return d.ll; } =20 -uint64_t helper_fmul8x16au(uint64_t src1, uint64_t src2) +uint64_t helper_fmul8x16au(uint32_t src1, uint32_t src2) { - VIS64 s, d; + VIS32 s1, s2; + VIS64 d; uint32_t tmp; =20 - s.ll =3D src1; - d.ll =3D src2; + s1.l =3D src1; + s2.l =3D src2; =20 #define PMUL(r) \ - tmp =3D (int32_t)d.VIS_SW64(0) * (int32_t)s.VIS_B64(r); \ + tmp =3D (int32_t)s2.VIS_SW32(1) * (int32_t)s1.VIS_B64(r); \ if ((tmp & 0xff) > 0x7f) { \ tmp +=3D 0x100; \ } \ --=20 2.41.0 From nobody Fri May 17 10:34:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1695646672070116.2300287153065; Mon, 25 Sep 2023 05:57:52 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qkl8o-0008KS-59; Mon, 25 Sep 2023 08:56:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qkdjt-0001eP-QP for qemu-devel@nongnu.org; Mon, 25 Sep 2023 01:02:35 -0400 Received: from mta01.start.ca ([162.250.196.97]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qkdjq-0004ml-QQ for qemu-devel@nongnu.org; Mon, 25 Sep 2023 01:02:33 -0400 Received: from mta01.start.ca (localhost [127.0.0.1]) by mta01.start.ca (Postfix) with ESMTP id 44CC62076D; Mon, 25 Sep 2023 01:02:30 -0400 (EDT) Received: from localhost (dhcp-24-53-241-2.cable.user.start.ca [24.53.241.2]) by mta01.start.ca (Postfix) with ESMTPS id 1FBDA20712; Mon, 25 Sep 2023 01:02:30 -0400 (EDT) From: Nick Bowler To: qemu-devel@nongnu.org Cc: Mark Cave-Ayland , Artyom Tarasenko Subject: [PATCH 3/8] target/sparc: Fix VIS fmul8x16al instruction. Date: Mon, 25 Sep 2023 01:03:52 -0400 Message-ID: <20230925050545.30912-4-nbowler@draconx.ca> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230925050545.30912-1-nbowler@draconx.ca> References: <20230925050545.30912-1-nbowler@draconx.ca> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Virus-Scanned: ClamAV using ClamSMTP Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=162.250.196.97; envelope-from=nbowler@draconx.ca; helo=mta01.start.ca X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Mon, 25 Sep 2023 08:56:43 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1695646673952100001 Content-Type: text/plain; charset="utf-8" On a real UltraSparc II, the fmul8x16al instruction takes two single- precision input operands and returns a double-precision result. For the second operand, bits 15:0 are used, and bits 31:16 are ignored. However, the emulation is taking two double-precision input operands, and furthermore it is using bits 31:16 of the second operand (ignoring bits 15:0). These are unlikely to contain the correct values. Even still, the emulator overwrites the second input before all outputs are calculated, so even if by chance the data loaded in happens to be correct, the results are just garbage except in trivial cases. Signed-off-by: Nick Bowler Acked-by: Mark Cave-Ayland Reviewed-by: Richard Henderson --- target/sparc/helper.h | 2 +- target/sparc/translate.c | 2 +- target/sparc/vis_helper.c | 11 ++++++----- 3 files changed, 8 insertions(+), 7 deletions(-) diff --git a/target/sparc/helper.h b/target/sparc/helper.h index 76e06b8ea5..25d6178ca5 100644 --- a/target/sparc/helper.h +++ b/target/sparc/helper.h @@ -127,7 +127,7 @@ DEF_HELPER_FLAGS_1(fqtox, TCG_CALL_NO_RWG, s64, env) =20 DEF_HELPER_FLAGS_2(fpmerge, TCG_CALL_NO_RWG_SE, i64, i64, i64) DEF_HELPER_FLAGS_2(fmul8x16, TCG_CALL_NO_RWG_SE, i64, i32, i64) -DEF_HELPER_FLAGS_2(fmul8x16al, TCG_CALL_NO_RWG_SE, i64, i64, i64) +DEF_HELPER_FLAGS_2(fmul8x16al, TCG_CALL_NO_RWG_SE, i64, i32, i32) DEF_HELPER_FLAGS_2(fmul8x16au, TCG_CALL_NO_RWG_SE, i64, i32, i32) DEF_HELPER_FLAGS_2(fmul8sux16, TCG_CALL_NO_RWG_SE, i64, i64, i64) DEF_HELPER_FLAGS_2(fmul8ulx16, TCG_CALL_NO_RWG_SE, i64, i64, i64) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index ca81b35a25..dddee9f974 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -4779,7 +4779,7 @@ static void disas_sparc_insn(DisasContext * dc, unsig= ned int insn) break; case 0x035: /* VIS I fmul8x16al */ CHECK_FPU_FEATURE(dc, VIS1); - gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmul8x16al= ); + gen_ne_fop_DFF(dc, rd, rs1, rs2, gen_helper_fmul8x16al= ); break; case 0x036: /* VIS I fmul8sux16 */ CHECK_FPU_FEATURE(dc, VIS1); diff --git a/target/sparc/vis_helper.c b/target/sparc/vis_helper.c index 2fc783a054..386cfd0706 100644 --- a/target/sparc/vis_helper.c +++ b/target/sparc/vis_helper.c @@ -122,16 +122,17 @@ uint64_t helper_fmul8x16(uint32_t src1, uint64_t src2) return d.ll; } =20 -uint64_t helper_fmul8x16al(uint64_t src1, uint64_t src2) +uint64_t helper_fmul8x16al(uint32_t src1, uint32_t src2) { - VIS64 s, d; + VIS32 s1, s2; + VIS64 d; uint32_t tmp; =20 - s.ll =3D src1; - d.ll =3D src2; + s1.l =3D src1; + s2.l =3D src2; =20 #define PMUL(r) \ - tmp =3D (int32_t)d.VIS_SW64(1) * (int32_t)s.VIS_B64(r); \ + tmp =3D (int32_t)s2.VIS_SW32(0) * (int32_t)s1.VIS_B64(r); \ if ((tmp & 0xff) > 0x7f) { \ tmp +=3D 0x100; \ } \ --=20 2.41.0 From nobody Fri May 17 10:34:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1695646707941126.10157216529512; Mon, 25 Sep 2023 05:58:27 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qkl8p-0008Ko-EI; Mon, 25 Sep 2023 08:56:47 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qkdjt-0001eQ-Qu for qemu-devel@nongnu.org; Mon, 25 Sep 2023 01:02:35 -0400 Received: from mta01.start.ca ([162.250.196.97]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qkdjr-0004mt-6S for qemu-devel@nongnu.org; Mon, 25 Sep 2023 01:02:33 -0400 Received: from mta01.start.ca (localhost [127.0.0.1]) by mta01.start.ca (Postfix) with ESMTP id 9E93720777; Mon, 25 Sep 2023 01:02:30 -0400 (EDT) Received: from localhost (dhcp-24-53-241-2.cable.user.start.ca [24.53.241.2]) by mta01.start.ca (Postfix) with ESMTPS id 77E232076F; Mon, 25 Sep 2023 01:02:30 -0400 (EDT) From: Nick Bowler To: qemu-devel@nongnu.org Cc: Mark Cave-Ayland , Artyom Tarasenko Subject: [PATCH 4/8] target/sparc: Fix VIS fmuld8sux16 instruction. Date: Mon, 25 Sep 2023 01:03:53 -0400 Message-ID: <20230925050545.30912-5-nbowler@draconx.ca> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230925050545.30912-1-nbowler@draconx.ca> References: <20230925050545.30912-1-nbowler@draconx.ca> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Virus-Scanned: ClamAV using ClamSMTP Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=162.250.196.97; envelope-from=nbowler@draconx.ca; helo=mta01.start.ca X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Mon, 25 Sep 2023 08:56:43 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1695646708455100009 Content-Type: text/plain; charset="utf-8" On a real UltraSparc II, the fmuld8sux16 instruction takes two single- precision input operands and returns a double-precision result. However, the emulation is taking two double-precision input operands, which are unlikely to contain the correct values. Even if they did, the emulator is rounding the output, which the real processor does not do. And the real processor shifts both outputs left by 8, which the emulator does not do. So the results are wrong except in trivial cases. Signed-off-by: Nick Bowler Acked-by: Mark Cave-Ayland Reviewed-by: Richard Henderson --- target/sparc/helper.h | 2 +- target/sparc/translate.c | 2 +- target/sparc/vis_helper.c | 19 ++++++++----------- 3 files changed, 10 insertions(+), 13 deletions(-) diff --git a/target/sparc/helper.h b/target/sparc/helper.h index 25d6178ca5..adc1ea6653 100644 --- a/target/sparc/helper.h +++ b/target/sparc/helper.h @@ -131,7 +131,7 @@ DEF_HELPER_FLAGS_2(fmul8x16al, TCG_CALL_NO_RWG_SE, i64,= i32, i32) DEF_HELPER_FLAGS_2(fmul8x16au, TCG_CALL_NO_RWG_SE, i64, i32, i32) DEF_HELPER_FLAGS_2(fmul8sux16, TCG_CALL_NO_RWG_SE, i64, i64, i64) DEF_HELPER_FLAGS_2(fmul8ulx16, TCG_CALL_NO_RWG_SE, i64, i64, i64) -DEF_HELPER_FLAGS_2(fmuld8sux16, TCG_CALL_NO_RWG_SE, i64, i64, i64) +DEF_HELPER_FLAGS_2(fmuld8sux16, TCG_CALL_NO_RWG_SE, i64, i32, i32) DEF_HELPER_FLAGS_2(fmuld8ulx16, TCG_CALL_NO_RWG_SE, i64, i64, i64) DEF_HELPER_FLAGS_2(fexpand, TCG_CALL_NO_RWG_SE, i64, i64, i64) DEF_HELPER_FLAGS_3(pdist, TCG_CALL_NO_RWG_SE, i64, i64, i64, i64) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index dddee9f974..1017d3bca7 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -4791,7 +4791,7 @@ static void disas_sparc_insn(DisasContext * dc, unsig= ned int insn) break; case 0x038: /* VIS I fmuld8sux16 */ CHECK_FPU_FEATURE(dc, VIS1); - gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmuld8sux1= 6); + gen_ne_fop_DFF(dc, rd, rs1, rs2, gen_helper_fmuld8sux1= 6); break; case 0x039: /* VIS I fmuld8ulx16 */ CHECK_FPU_FEATURE(dc, VIS1); diff --git a/target/sparc/vis_helper.c b/target/sparc/vis_helper.c index 386cfd0706..de5ddad39a 100644 --- a/target/sparc/vis_helper.c +++ b/target/sparc/vis_helper.c @@ -220,24 +220,21 @@ uint64_t helper_fmul8ulx16(uint64_t src1, uint64_t sr= c2) return d.ll; } =20 -uint64_t helper_fmuld8sux16(uint64_t src1, uint64_t src2) +uint64_t helper_fmuld8sux16(uint32_t src1, uint32_t src2) { - VIS64 s, d; + VIS32 s1, s2; + VIS64 d; uint32_t tmp; =20 - s.ll =3D src1; - d.ll =3D src2; + s1.l =3D src1; + s2.l =3D src2; =20 #define PMUL(r) \ - tmp =3D (int32_t)d.VIS_SW64(r) * ((int32_t)s.VIS_SW64(r) >> 8); \ - if ((tmp & 0xff) > 0x7f) { \ - tmp +=3D 0x100; \ - } \ - d.VIS_L64(r) =3D tmp; + tmp =3D (int32_t)s2.VIS_SW32(r) * ((int32_t)s1.VIS_SW32(r) >> 8); \ + d.VIS_L64(r) =3D tmp << 8; =20 - /* Reverse calculation order to handle overlap */ - PMUL(1); PMUL(0); + PMUL(1); #undef PMUL =20 return d.ll; --=20 2.41.0 From nobody Fri May 17 10:34:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1695646723683550.9401343779826; Mon, 25 Sep 2023 05:58:43 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qkl8n-0008KA-Qb; Mon, 25 Sep 2023 08:56:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qkdju-0001eR-5W for qemu-devel@nongnu.org; Mon, 25 Sep 2023 01:02:35 -0400 Received: from mta01.start.ca ([162.250.196.97]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qkdjs-0004oV-Fy for qemu-devel@nongnu.org; Mon, 25 Sep 2023 01:02:33 -0400 Received: from mta01.start.ca (localhost [127.0.0.1]) by mta01.start.ca (Postfix) with ESMTP id 0B1E22077C; Mon, 25 Sep 2023 01:02:31 -0400 (EDT) Received: from localhost (dhcp-24-53-241-2.cable.user.start.ca [24.53.241.2]) by mta01.start.ca (Postfix) with ESMTPS id CDCC62076F; Mon, 25 Sep 2023 01:02:30 -0400 (EDT) From: Nick Bowler To: qemu-devel@nongnu.org Cc: Mark Cave-Ayland , Artyom Tarasenko Subject: [PATCH 5/8] target/sparc: Fix VIS fmuld8ulx16 instruction. Date: Mon, 25 Sep 2023 01:03:54 -0400 Message-ID: <20230925050545.30912-6-nbowler@draconx.ca> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230925050545.30912-1-nbowler@draconx.ca> References: <20230925050545.30912-1-nbowler@draconx.ca> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Virus-Scanned: ClamAV using ClamSMTP Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=162.250.196.97; envelope-from=nbowler@draconx.ca; helo=mta01.start.ca X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Mon, 25 Sep 2023 08:56:43 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1695646725378100005 Content-Type: text/plain; charset="utf-8" On a real UltraSparc II, the fmuld8ulx16 instruction takes two single- precision input operands and returns a double-precision result. However, the emulation is taking two double-precision input operands, which are unlikely to contain the correct values, so the results are garbage in most cases. Even if the inputs happen to be correct, the emulator is rounding the output, which the real processor does not do. Signed-off-by: Nick Bowler Acked-by: Mark Cave-Ayland Reviewed-by: Richard Henderson --- target/sparc/helper.h | 2 +- target/sparc/translate.c | 2 +- target/sparc/vis_helper.c | 17 +++++++---------- 3 files changed, 9 insertions(+), 12 deletions(-) diff --git a/target/sparc/helper.h b/target/sparc/helper.h index adc1ea6653..7a588f3068 100644 --- a/target/sparc/helper.h +++ b/target/sparc/helper.h @@ -132,7 +132,7 @@ DEF_HELPER_FLAGS_2(fmul8x16au, TCG_CALL_NO_RWG_SE, i64,= i32, i32) DEF_HELPER_FLAGS_2(fmul8sux16, TCG_CALL_NO_RWG_SE, i64, i64, i64) DEF_HELPER_FLAGS_2(fmul8ulx16, TCG_CALL_NO_RWG_SE, i64, i64, i64) DEF_HELPER_FLAGS_2(fmuld8sux16, TCG_CALL_NO_RWG_SE, i64, i32, i32) -DEF_HELPER_FLAGS_2(fmuld8ulx16, TCG_CALL_NO_RWG_SE, i64, i64, i64) +DEF_HELPER_FLAGS_2(fmuld8ulx16, TCG_CALL_NO_RWG_SE, i64, i32, i32) DEF_HELPER_FLAGS_2(fexpand, TCG_CALL_NO_RWG_SE, i64, i64, i64) DEF_HELPER_FLAGS_3(pdist, TCG_CALL_NO_RWG_SE, i64, i64, i64, i64) DEF_HELPER_FLAGS_2(fpack16, TCG_CALL_NO_RWG_SE, i32, i64, i64) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 1017d3bca7..cfccd95c3a 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -4795,7 +4795,7 @@ static void disas_sparc_insn(DisasContext * dc, unsig= ned int insn) break; case 0x039: /* VIS I fmuld8ulx16 */ CHECK_FPU_FEATURE(dc, VIS1); - gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmuld8ulx1= 6); + gen_ne_fop_DFF(dc, rd, rs1, rs2, gen_helper_fmuld8ulx1= 6); break; case 0x03a: /* VIS I fpack32 */ CHECK_FPU_FEATURE(dc, VIS1); diff --git a/target/sparc/vis_helper.c b/target/sparc/vis_helper.c index de5ddad39a..306383ba60 100644 --- a/target/sparc/vis_helper.c +++ b/target/sparc/vis_helper.c @@ -240,24 +240,21 @@ uint64_t helper_fmuld8sux16(uint32_t src1, uint32_t s= rc2) return d.ll; } =20 -uint64_t helper_fmuld8ulx16(uint64_t src1, uint64_t src2) +uint64_t helper_fmuld8ulx16(uint32_t src1, uint32_t src2) { - VIS64 s, d; + VIS32 s1, s2; + VIS64 d; uint32_t tmp; =20 - s.ll =3D src1; - d.ll =3D src2; + s1.l =3D src1; + s2.l =3D src2; =20 #define PMUL(r) \ - tmp =3D (int32_t)d.VIS_SW64(r) * ((uint32_t)s.VIS_B64(r * 2)); \ - if ((tmp & 0xff) > 0x7f) { \ - tmp +=3D 0x100; \ - } \ + tmp =3D (int32_t)s2.VIS_SW32(r) * ((uint32_t)s1.VIS_B32(r * 2)); \ d.VIS_L64(r) =3D tmp; =20 - /* Reverse calculation order to handle overlap */ - PMUL(1); PMUL(0); + PMUL(1); #undef PMUL =20 return d.ll; --=20 2.41.0 From nobody Fri May 17 10:34:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 16956466608504.354706667593632; Mon, 25 Sep 2023 05:57:40 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qkl8o-0008Km-Rl; Mon, 25 Sep 2023 08:56:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qkdjv-0001eU-Sb for qemu-devel@nongnu.org; Mon, 25 Sep 2023 01:02:35 -0400 Received: from mta01.start.ca ([162.250.196.97]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qkdjt-0004oh-I1 for qemu-devel@nongnu.org; Mon, 25 Sep 2023 01:02:35 -0400 Received: from mta01.start.ca (localhost [127.0.0.1]) by mta01.start.ca (Postfix) with ESMTP id 5849620786; Mon, 25 Sep 2023 01:02:32 -0400 (EDT) Received: from localhost (dhcp-24-53-241-2.cable.user.start.ca [24.53.241.2]) by mta01.start.ca (Postfix) with ESMTPS id 31AE220784; Mon, 25 Sep 2023 01:02:32 -0400 (EDT) From: Nick Bowler To: qemu-devel@nongnu.org Cc: Mark Cave-Ayland , Artyom Tarasenko Subject: [PATCH 6/8] target/sparc: Fix VIS fpmerge input registers. Date: Mon, 25 Sep 2023 01:03:55 -0400 Message-ID: <20230925050545.30912-7-nbowler@draconx.ca> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230925050545.30912-1-nbowler@draconx.ca> References: <20230925050545.30912-1-nbowler@draconx.ca> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Virus-Scanned: ClamAV using ClamSMTP Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=162.250.196.97; envelope-from=nbowler@draconx.ca; helo=mta01.start.ca X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Mon, 25 Sep 2023 08:56:43 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1695646662793100003 Content-Type: text/plain; charset="utf-8" On a real UltraSparc II CPU, the fpmerge instruction reads two single-precision input registers, but the emulator is reading from double-precision input registers instead. These are unlikely to contain the correct data so in most instances the results of the emulation are just garbage in most instances. Signed-off-by: Nick Bowler Acked-by: Mark Cave-Ayland --- target/sparc/helper.h | 2 +- target/sparc/translate.c | 6 +++++- target/sparc/vis_helper.c | 26 +++++++++++++------------- 3 files changed, 19 insertions(+), 15 deletions(-) diff --git a/target/sparc/helper.h b/target/sparc/helper.h index 7a588f3068..b71688079f 100644 --- a/target/sparc/helper.h +++ b/target/sparc/helper.h @@ -125,7 +125,7 @@ DEF_HELPER_FLAGS_2(fstox, TCG_CALL_NO_RWG, s64, env, f3= 2) DEF_HELPER_FLAGS_2(fdtox, TCG_CALL_NO_RWG, s64, env, f64) DEF_HELPER_FLAGS_1(fqtox, TCG_CALL_NO_RWG, s64, env) =20 -DEF_HELPER_FLAGS_2(fpmerge, TCG_CALL_NO_RWG_SE, i64, i64, i64) +DEF_HELPER_FLAGS_2(fpmerge, TCG_CALL_NO_RWG_SE, i64, i32, i32) DEF_HELPER_FLAGS_2(fmul8x16, TCG_CALL_NO_RWG_SE, i64, i32, i64) DEF_HELPER_FLAGS_2(fmul8x16al, TCG_CALL_NO_RWG_SE, i64, i32, i32) DEF_HELPER_FLAGS_2(fmul8x16au, TCG_CALL_NO_RWG_SE, i64, i32, i32) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index cfccd95c3a..241ac429ca 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -4825,7 +4825,11 @@ static void disas_sparc_insn(DisasContext * dc, unsi= gned int insn) break; case 0x04b: /* VIS I fpmerge */ CHECK_FPU_FEATURE(dc, VIS1); - gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpmerge); + cpu_src1_32 =3D gen_load_fpr_F(dc, rs1); + cpu_src2_32 =3D gen_load_fpr_F(dc, rs2); + cpu_dst_64 =3D gen_dest_fpr_D(dc, rd); + gen_helper_fpmerge(cpu_dst_64, cpu_src1_32, cpu_src2_3= 2); + gen_store_fpr_D(dc, rd, cpu_dst_64); break; case 0x04c: /* VIS II bshuffle */ CHECK_FPU_FEATURE(dc, VIS2); diff --git a/target/sparc/vis_helper.c b/target/sparc/vis_helper.c index 306383ba60..029aad3923 100644 --- a/target/sparc/vis_helper.c +++ b/target/sparc/vis_helper.c @@ -77,22 +77,22 @@ typedef union { float32 f; } VIS32; =20 -uint64_t helper_fpmerge(uint64_t src1, uint64_t src2) +uint64_t helper_fpmerge(uint32_t src1, uint32_t src2) { - VIS64 s, d; + VIS32 s1, s2; + VIS64 d; =20 - s.ll =3D src1; - d.ll =3D src2; + s1.l =3D src1; + s2.l =3D src2; =20 - /* Reverse calculation order to handle overlap */ - d.VIS_B64(7) =3D s.VIS_B64(3); - d.VIS_B64(6) =3D d.VIS_B64(3); - d.VIS_B64(5) =3D s.VIS_B64(2); - d.VIS_B64(4) =3D d.VIS_B64(2); - d.VIS_B64(3) =3D s.VIS_B64(1); - d.VIS_B64(2) =3D d.VIS_B64(1); - d.VIS_B64(1) =3D s.VIS_B64(0); - /* d.VIS_B64(0) =3D d.VIS_B64(0); */ + d.VIS_B64(0) =3D s2.VIS_B32(0); + d.VIS_B64(1) =3D s1.VIS_B32(0); + d.VIS_B64(2) =3D s2.VIS_B32(1); + d.VIS_B64(3) =3D s1.VIS_B32(1); + d.VIS_B64(4) =3D s2.VIS_B32(2); + d.VIS_B64(5) =3D s1.VIS_B32(2); + d.VIS_B64(6) =3D s2.VIS_B32(3); + d.VIS_B64(7) =3D s1.VIS_B32(3); =20 return d.ll; } --=20 2.41.0 From nobody Fri May 17 10:34:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1695646724019505.0693411843829; Mon, 25 Sep 2023 05:58:44 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qkl8r-0008M2-1k; Mon, 25 Sep 2023 08:56:49 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qkdjv-0001eT-Q4 for qemu-devel@nongnu.org; Mon, 25 Sep 2023 01:02:35 -0400 Received: from mta01.start.ca ([162.250.196.97]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qkdjt-0004om-Ii for qemu-devel@nongnu.org; Mon, 25 Sep 2023 01:02:35 -0400 Received: from mta01.start.ca (localhost [127.0.0.1]) by mta01.start.ca (Postfix) with ESMTP id B123F2078F; Mon, 25 Sep 2023 01:02:32 -0400 (EDT) Received: from localhost (dhcp-24-53-241-2.cable.user.start.ca [24.53.241.2]) by mta01.start.ca (Postfix) with ESMTPS id 8B3C620784; Mon, 25 Sep 2023 01:02:32 -0400 (EDT) From: Nick Bowler To: qemu-devel@nongnu.org Cc: Mark Cave-Ayland , Artyom Tarasenko Subject: [PATCH 7/8] target/sparc: Fix VIS fexpand input register. Date: Mon, 25 Sep 2023 01:03:56 -0400 Message-ID: <20230925050545.30912-8-nbowler@draconx.ca> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230925050545.30912-1-nbowler@draconx.ca> References: <20230925050545.30912-1-nbowler@draconx.ca> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Virus-Scanned: ClamAV using ClamSMTP Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=162.250.196.97; envelope-from=nbowler@draconx.ca; helo=mta01.start.ca X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Mon, 25 Sep 2023 08:56:43 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1695646725402100006 Content-Type: text/plain; charset="utf-8" This instruction is documented to get its input from the second single-precision input operand; the first operand is ignored. This is exactly what a real UltraSparc II does. Meanwhile, the the emulator uses only the irrelevant first operand, treating it as a double-precision register, and ignores the second. This will not normally contain the correct data so the emulated instruction usually just produces garbage. Signed-off-by: Nick Bowler Acked-by: Mark Cave-Ayland Reviewed-by: Richard Henderson --- target/sparc/helper.h | 2 +- target/sparc/translate.c | 5 ++++- target/sparc/vis_helper.c | 5 ++--- 3 files changed, 7 insertions(+), 5 deletions(-) diff --git a/target/sparc/helper.h b/target/sparc/helper.h index b71688079f..81d44e7618 100644 --- a/target/sparc/helper.h +++ b/target/sparc/helper.h @@ -133,7 +133,7 @@ DEF_HELPER_FLAGS_2(fmul8sux16, TCG_CALL_NO_RWG_SE, i64,= i64, i64) DEF_HELPER_FLAGS_2(fmul8ulx16, TCG_CALL_NO_RWG_SE, i64, i64, i64) DEF_HELPER_FLAGS_2(fmuld8sux16, TCG_CALL_NO_RWG_SE, i64, i32, i32) DEF_HELPER_FLAGS_2(fmuld8ulx16, TCG_CALL_NO_RWG_SE, i64, i32, i32) -DEF_HELPER_FLAGS_2(fexpand, TCG_CALL_NO_RWG_SE, i64, i64, i64) +DEF_HELPER_FLAGS_1(fexpand, TCG_CALL_NO_RWG_SE, i64, i32) DEF_HELPER_FLAGS_3(pdist, TCG_CALL_NO_RWG_SE, i64, i64, i64, i64) DEF_HELPER_FLAGS_2(fpack16, TCG_CALL_NO_RWG_SE, i32, i64, i64) DEF_HELPER_FLAGS_3(fpack32, TCG_CALL_NO_RWG_SE, i64, i64, i64, i64) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 241ac429ca..4e92c27768 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -4837,7 +4837,10 @@ static void disas_sparc_insn(DisasContext * dc, unsi= gned int insn) break; case 0x04d: /* VIS I fexpand */ CHECK_FPU_FEATURE(dc, VIS1); - gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fexpand); + cpu_src2_32 =3D gen_load_fpr_F(dc, rs2); + cpu_dst_64 =3D gen_dest_fpr_D(dc, rd); + gen_helper_fexpand(cpu_dst_64, cpu_src2_32); + gen_store_fpr_D(dc, rd, cpu_dst_64); break; case 0x050: /* VIS I fpadd16 */ CHECK_FPU_FEATURE(dc, VIS1); diff --git a/target/sparc/vis_helper.c b/target/sparc/vis_helper.c index 029aad3923..3903beaf5d 100644 --- a/target/sparc/vis_helper.c +++ b/target/sparc/vis_helper.c @@ -260,13 +260,12 @@ uint64_t helper_fmuld8ulx16(uint32_t src1, uint32_t s= rc2) return d.ll; } =20 -uint64_t helper_fexpand(uint64_t src1, uint64_t src2) +uint64_t helper_fexpand(uint32_t src2) { VIS32 s; VIS64 d; =20 - s.l =3D (uint32_t)src1; - d.ll =3D src2; + s.l =3D src2; d.VIS_W64(0) =3D s.VIS_B32(0) << 4; d.VIS_W64(1) =3D s.VIS_B32(1) << 4; d.VIS_W64(2) =3D s.VIS_B32(2) << 4; --=20 2.41.0 From nobody Fri May 17 10:34:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 169564670464828.2569070339498; Mon, 25 Sep 2023 05:58:24 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qkl8m-0008ID-Ov; Mon, 25 Sep 2023 08:56:44 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qkdjw-0001fH-QA for qemu-devel@nongnu.org; Mon, 25 Sep 2023 01:02:36 -0400 Received: from mta01.start.ca ([162.250.196.97]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qkdjt-0004ot-V0 for qemu-devel@nongnu.org; Mon, 25 Sep 2023 01:02:36 -0400 Received: from mta01.start.ca (localhost [127.0.0.1]) by mta01.start.ca (Postfix) with ESMTP id 27956207A2; Mon, 25 Sep 2023 01:02:33 -0400 (EDT) Received: from localhost (dhcp-24-53-241-2.cable.user.start.ca [24.53.241.2]) by mta01.start.ca (Postfix) with ESMTPS id F0D6D20784; Mon, 25 Sep 2023 01:02:32 -0400 (EDT) From: Nick Bowler To: qemu-devel@nongnu.org Cc: Mark Cave-Ayland , Artyom Tarasenko Subject: [PATCH 8/8] target/sparc: Fix VIS subtraction instructions. Date: Mon, 25 Sep 2023 01:03:57 -0400 Message-ID: <20230925050545.30912-9-nbowler@draconx.ca> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230925050545.30912-1-nbowler@draconx.ca> References: <20230925050545.30912-1-nbowler@draconx.ca> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Virus-Scanned: ClamAV using ClamSMTP Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=162.250.196.97; envelope-from=nbowler@draconx.ca; helo=mta01.start.ca X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Mon, 25 Sep 2023 08:56:43 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1695646705186100001 Content-Type: text/plain; charset="utf-8" All of the VIS subtraction instructions are documented to subtract the second input operand from the first. This is also consistent with how the instructions actually work on a real UltraSparc II. But the emulator is implementing the subtraction in the wrong order, subtracting the first input from the second, so the results are wrong in all nontrivial cases. Signed-off-by: Nick Bowler Acked-by: Mark Cave-Ayland --- target/sparc/vis_helper.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/target/sparc/vis_helper.c b/target/sparc/vis_helper.c index 3903beaf5d..fa97e09ffa 100644 --- a/target/sparc/vis_helper.c +++ b/target/sparc/vis_helper.c @@ -282,10 +282,10 @@ uint64_t helper_fexpand(uint32_t src2) s.ll =3D src1; \ d.ll =3D src2; \ \ - d.VIS_W64(0) =3D F(d.VIS_W64(0), s.VIS_W64(0)); \ - d.VIS_W64(1) =3D F(d.VIS_W64(1), s.VIS_W64(1)); \ - d.VIS_W64(2) =3D F(d.VIS_W64(2), s.VIS_W64(2)); \ - d.VIS_W64(3) =3D F(d.VIS_W64(3), s.VIS_W64(3)); \ + d.VIS_W64(0) =3D F(s.VIS_W64(0), d.VIS_W64(0)); \ + d.VIS_W64(1) =3D F(s.VIS_W64(1), d.VIS_W64(1)); \ + d.VIS_W64(2) =3D F(s.VIS_W64(2), d.VIS_W64(2)); \ + d.VIS_W64(3) =3D F(s.VIS_W64(3), d.VIS_W64(3)); \ \ return d.ll; \ } \ @@ -297,8 +297,8 @@ uint64_t helper_fexpand(uint32_t src2) s.l =3D src1; \ d.l =3D src2; \ \ - d.VIS_W32(0) =3D F(d.VIS_W32(0), s.VIS_W32(0)); \ - d.VIS_W32(1) =3D F(d.VIS_W32(1), s.VIS_W32(1)); \ + d.VIS_W32(0) =3D F(s.VIS_W32(0), d.VIS_W32(0)); \ + d.VIS_W32(1) =3D F(s.VIS_W32(1), d.VIS_W32(1)); \ \ return d.l; \ } \ @@ -310,8 +310,8 @@ uint64_t helper_fexpand(uint32_t src2) s.ll =3D src1; \ d.ll =3D src2; \ \ - d.VIS_L64(0) =3D F(d.VIS_L64(0), s.VIS_L64(0)); \ - d.VIS_L64(1) =3D F(d.VIS_L64(1), s.VIS_L64(1)); \ + d.VIS_L64(0) =3D F(s.VIS_L64(0), d.VIS_L64(0)); \ + d.VIS_L64(1) =3D F(s.VIS_L64(1), d.VIS_L64(1)); \ \ return d.ll; \ } \ @@ -323,7 +323,7 @@ uint64_t helper_fexpand(uint32_t src2) s.l =3D src1; \ d.l =3D src2; \ \ - d.l =3D F(d.l, s.l); \ + d.l =3D F(s.l, d.l); \ \ return d.l; \ } --=20 2.41.0