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Tsirkin" , Marcel Apfelbaum , Paolo Bonzini , Richard Henderson , Eduardo Habkost Cc: philmd@linaro.org, Ani Sinha , qemu-devel@nongnu.org Subject: [PATCH] hw/i386/pc: fix max_used_gpa for 32-bit systems Date: Mon, 18 Sep 2023 19:24:48 +0530 Message-Id: <20230918135448.90963-1-anisinha@redhat.com> X-Mailer: git-send-email 2.39.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=anisinha@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1695046115295100001 Content-Type: text/plain; charset="utf-8" 32-bit systems do not have a reserved memory for hole64 but they may have a reserved memory space for memory hotplug. Since, hole64 starts after the reserved hotplug memory, the unaligned hole64 start address gives us the end address for this memory hotplug region that the processor may use. Fix this. This ensures that the physical address space bound checking works correctly for 32-bit systems as well. Suggested-by: David Hildenbrand Signed-off-by: Ani Sinha --- hw/i386/pc.c | 60 ++++++++++++++++++++++++++++++---------------------- 1 file changed, 35 insertions(+), 25 deletions(-) diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 54838c0c41..c8abcabd53 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -904,13 +904,43 @@ static uint64_t pc_get_cxl_range_end(PCMachineState *= pcms) return start; } =20 +/* + * The 64bit pci hole starts after "above 4G RAM" and + * potentially the space reserved for memory hotplug. + * This function returns unaligned start address. + */ +static uint64_t pc_pci_hole64_start_unaligned(void) +{ + PCMachineState *pcms =3D PC_MACHINE(qdev_get_machine()); + PCMachineClass *pcmc =3D PC_MACHINE_GET_CLASS(pcms); + MachineState *ms =3D MACHINE(pcms); + uint64_t hole64_start =3D 0; + ram_addr_t size =3D 0; + + if (pcms->cxl_devices_state.is_enabled) { + hole64_start =3D pc_get_cxl_range_end(pcms); + } else if (pcmc->has_reserved_memory && (ms->ram_size < ms->maxram_siz= e)) { + pc_get_device_memory_range(pcms, &hole64_start, &size); + if (!pcmc->broken_reserved_end) { + hole64_start +=3D size; + } + } else { + hole64_start =3D pc_above_4g_end(pcms); + } + + return hole64_start; +} + static hwaddr pc_max_used_gpa(PCMachineState *pcms, uint64_t pci_hole64_si= ze) { X86CPU *cpu =3D X86_CPU(first_cpu); =20 - /* 32-bit systems don't have hole64 thus return max CPU address */ - if (cpu->phys_bits <=3D 32) { - return ((hwaddr)1 << cpu->phys_bits) - 1; + /* + * 32-bit systems don't have hole64, but we might have a region for + * memory hotplug. + */ + if (!(cpu->env.features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM)) { + return pc_pci_hole64_start_unaligned() - 1; } =20 return pc_pci_hole64_start() + pci_hole64_size - 1; @@ -1147,30 +1177,10 @@ void pc_memory_init(PCMachineState *pcms, pcms->memhp_io_base =3D ACPI_MEMORY_HOTPLUG_BASE; } =20 -/* - * The 64bit pci hole starts after "above 4G RAM" and - * potentially the space reserved for memory hotplug. - */ +/* returns 1 GiB aligned hole64 start address */ uint64_t pc_pci_hole64_start(void) { - PCMachineState *pcms =3D PC_MACHINE(qdev_get_machine()); - PCMachineClass *pcmc =3D PC_MACHINE_GET_CLASS(pcms); - MachineState *ms =3D MACHINE(pcms); - uint64_t hole64_start =3D 0; - ram_addr_t size =3D 0; - - if (pcms->cxl_devices_state.is_enabled) { - hole64_start =3D pc_get_cxl_range_end(pcms); - } else if (pcmc->has_reserved_memory && (ms->ram_size < ms->maxram_siz= e)) { - pc_get_device_memory_range(pcms, &hole64_start, &size); - if (!pcmc->broken_reserved_end) { - hole64_start +=3D size; - } - } else { - hole64_start =3D pc_above_4g_end(pcms); - } - - return ROUND_UP(hole64_start, 1 * GiB); + return ROUND_UP(pc_pci_hole64_start_unaligned(), 1 * GiB); } =20 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus) --=20 2.39.1