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([71.212.131.115]) by smtp.gmail.com with ESMTPSA id n21-20020aa79055000000b0068fde95aa93sm4871708pfo.135.2023.09.16.14.41.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 16 Sep 2023 14:41:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1694900502; x=1695505302; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=TVqkrTpBkS08OOtc33GfGLABbq/z0dDCKK+SIF9n4BI=; b=xBhSxwBFxtMVxXpESsrhr4sY7V/isHrdnVzr/wuhWM4Ftg9pGipAi4QBNh3Gu/y1pD hY6NAugzDYBEiiozKUKUJob+ZoORPkO7zCQaxwxu85XsGub1zBfQviYDBynECf7AVLhi fynuc4ODWs6iYhN8U6BV6ZJbuIEdZX2hXepE5RgpCWTfLvxeyem0Uxpp6h7lrOvXT9WM Ue0Y1rMjFBnWY4U5jccXer3BYS0gEZi14Gtjir88bz6liuwOA8PuW8kEeelae5/0QS1/ 4n1ChtIehRncTLWOkdTLu+GtKKk1veTzvKK1Znt/g2y5o7K6rGvvLqAQAJI66TwyNMT9 Jzrg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1694900502; x=1695505302; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=TVqkrTpBkS08OOtc33GfGLABbq/z0dDCKK+SIF9n4BI=; b=bCL5CJbaS31YTzvYcTuxI9Hp8Msh9KKDqca13BE0PnGwvPS3QiTI/iJWRngiGV2cd7 ryaQr1equLBP/LCbweInudDWbTp1pQhuKPyPOrcS97AiHDrt5/Y/sMaln9y+56aY2C2m DKRcly2yHzOyn5RvX2A2BRymcaM5cC1onC5scOSaZXEgpjNFtRUCpFsZTyRV5JkZ75L5 ZkkvYjZj1u5zFGOk97V1xJqVu62SCmWi9coKY3SId4AVcI0BWr1NfW/utjyzvJvs678M AEegRAS0QnullGtyrwUqRFgz/Jss61p9XCeWVbjktJOWtR3Xaa5X6RSl5EMD2Qp6Xrjl rx5Q== X-Gm-Message-State: AOJu0YygJTGpzDI2zet9p4F7lbCfT6hQ/YdOY4jAacpXBQNWFFF4Ovox 8J5N88fpnOxOx3SRQU/lz6fpuQ+G66VTGQl2sD0= X-Google-Smtp-Source: AGHT+IHanDw+X59OTMvGbSm548V7cHPuQ2nar0uTOAzAUC/wAYOMJieVpkafANx29dQt6jSMj6H3wA== X-Received: by 2002:a05:6a00:1250:b0:68c:69c8:e0f0 with SMTP id u16-20020a056a00125000b0068c69c8e0f0mr6434709pfi.18.1694900502660; Sat, 16 Sep 2023 14:41:42 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: philmd@linaro.org, anjo@rev.ng Subject: [PATCH v3 17/39] accel/tcg: Modify probe_access_internal() to use CPUState Date: Sat, 16 Sep 2023 14:41:01 -0700 Message-Id: <20230916214123.525796-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230916214123.525796-1-richard.henderson@linaro.org> References: <20230916214123.525796-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::431; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1694900690894100001 From: Anton Johansson probe_access_internal() is changed to instead take the generic CPUState over CPUArchState, in order to lessen the target-specific coupling of cputlb.c. Note: probe_access*() also don't need the full CPUArchState, but aren't touched in this patch as they are target-facing. Signed-off-by: Anton Johansson Message-Id: <20230912153428.17816-5-anjo@rev.ng> Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 [rth: Use cpu->neg.tlb instead of cpu_tlb()] Signed-off-by: Richard Henderson --- accel/tcg/cputlb.c | 46 +++++++++++++++++++++++----------------------- 1 file changed, 23 insertions(+), 23 deletions(-) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index f88c394594..ab52afb3f3 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1432,27 +1432,24 @@ static void notdirty_write(CPUState *cpu, vaddr mem= _vaddr, unsigned size, } } =20 -static int probe_access_internal(CPUArchState *env, vaddr addr, +static int probe_access_internal(CPUState *cpu, vaddr addr, int fault_size, MMUAccessType access_type, int mmu_idx, bool nonfault, void **phost, CPUTLBEntryFull **pfull, uintptr_t retaddr, bool check_mem_cbs) { - uintptr_t index =3D tlb_index(env_cpu(env), mmu_idx, addr); - CPUTLBEntry *entry =3D tlb_entry(env_cpu(env), mmu_idx, addr); + uintptr_t index =3D tlb_index(cpu, mmu_idx, addr); + CPUTLBEntry *entry =3D tlb_entry(cpu, mmu_idx, addr); uint64_t tlb_addr =3D tlb_read_idx(entry, access_type); vaddr page_addr =3D addr & TARGET_PAGE_MASK; int flags =3D TLB_FLAGS_MASK & ~TLB_FORCE_SLOW; - bool force_mmio =3D check_mem_cbs && cpu_plugin_mem_cbs_enabled(env_cp= u(env)); + bool force_mmio =3D check_mem_cbs && cpu_plugin_mem_cbs_enabled(cpu); CPUTLBEntryFull *full; =20 if (!tlb_hit_page(tlb_addr, page_addr)) { - if (!victim_tlb_hit(env_cpu(env), mmu_idx, index, - access_type, page_addr)) { - CPUState *cs =3D env_cpu(env); - - if (!cs->cc->tcg_ops->tlb_fill(cs, addr, fault_size, access_ty= pe, - mmu_idx, nonfault, retaddr)) { + if (!victim_tlb_hit(cpu, mmu_idx, index, access_type, page_addr)) { + if (!cpu->cc->tcg_ops->tlb_fill(cpu, addr, fault_size, access_= type, + mmu_idx, nonfault, retaddr)) { /* Non-faulting page table read failed. */ *phost =3D NULL; *pfull =3D NULL; @@ -1460,8 +1457,8 @@ static int probe_access_internal(CPUArchState *env, v= addr addr, } =20 /* TLB resize via tlb_fill may have moved the entry. */ - index =3D tlb_index(env_cpu(env), mmu_idx, addr); - entry =3D tlb_entry(env_cpu(env), mmu_idx, addr); + index =3D tlb_index(cpu, mmu_idx, addr); + entry =3D tlb_entry(cpu, mmu_idx, addr); =20 /* * With PAGE_WRITE_INV, we set TLB_INVALID_MASK immediately, @@ -1474,7 +1471,7 @@ static int probe_access_internal(CPUArchState *env, v= addr addr, } flags &=3D tlb_addr; =20 - *pfull =3D full =3D &env_tlb(env)->d[mmu_idx].fulltlb[index]; + *pfull =3D full =3D &cpu->neg.tlb.d[mmu_idx].fulltlb[index]; flags |=3D full->slow_flags[access_type]; =20 /* Fold all "mmio-like" bits into TLB_MMIO. This is not RAM. */ @@ -1495,8 +1492,9 @@ int probe_access_full(CPUArchState *env, vaddr addr, = int size, bool nonfault, void **phost, CPUTLBEntryFull **pfull, uintptr_t retaddr) { - int flags =3D probe_access_internal(env, addr, size, access_type, mmu_= idx, - nonfault, phost, pfull, retaddr, tru= e); + int flags =3D probe_access_internal(env_cpu(env), addr, size, access_t= ype, + mmu_idx, nonfault, phost, pfull, ret= addr, + true); =20 /* Handle clean RAM pages. */ if (unlikely(flags & TLB_NOTDIRTY)) { @@ -1518,8 +1516,8 @@ int probe_access_full_mmu(CPUArchState *env, vaddr ad= dr, int size, phost =3D phost ? phost : &discard_phost; pfull =3D pfull ? pfull : &discard_tlb; =20 - int flags =3D probe_access_internal(env, addr, size, access_type, mmu_= idx, - true, phost, pfull, 0, false); + int flags =3D probe_access_internal(env_cpu(env), addr, size, access_t= ype, + mmu_idx, true, phost, pfull, 0, fals= e); =20 /* Handle clean RAM pages. */ if (unlikely(flags & TLB_NOTDIRTY)) { @@ -1539,8 +1537,9 @@ int probe_access_flags(CPUArchState *env, vaddr addr,= int size, =20 g_assert(-(addr | TARGET_PAGE_MASK) >=3D size); =20 - flags =3D probe_access_internal(env, addr, size, access_type, mmu_idx, - nonfault, phost, &full, retaddr, true); + flags =3D probe_access_internal(env_cpu(env), addr, size, access_type, + mmu_idx, nonfault, phost, &full, retaddr, + true); =20 /* Handle clean RAM pages. */ if (unlikely(flags & TLB_NOTDIRTY)) { @@ -1560,8 +1559,9 @@ void *probe_access(CPUArchState *env, vaddr addr, int= size, =20 g_assert(-(addr | TARGET_PAGE_MASK) >=3D size); =20 - flags =3D probe_access_internal(env, addr, size, access_type, mmu_idx, - false, &host, &full, retaddr, true); + flags =3D probe_access_internal(env_cpu(env), addr, size, access_type, + mmu_idx, false, &host, &full, retaddr, + true); =20 /* Per the interface, size =3D=3D 0 merely faults the access. */ if (size =3D=3D 0) { @@ -1593,7 +1593,7 @@ void *tlb_vaddr_to_host(CPUArchState *env, abi_ptr ad= dr, void *host; int flags; =20 - flags =3D probe_access_internal(env, addr, 0, access_type, + flags =3D probe_access_internal(env_cpu(env), addr, 0, access_type, mmu_idx, true, &host, &full, 0, false); =20 /* No combination of flags are expected by the caller. */ @@ -1616,7 +1616,7 @@ tb_page_addr_t get_page_addr_code_hostp(CPUArchState = *env, vaddr addr, CPUTLBEntryFull *full; void *p; =20 - (void)probe_access_internal(env, addr, 1, MMU_INST_FETCH, + (void)probe_access_internal(env_cpu(env), addr, 1, MMU_INST_FETCH, cpu_mmu_index(env, true), false, &p, &full, 0, false); if (p =3D=3D NULL) { --=20 2.34.1