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Iglesias" , Daniel Henrique Barboza , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , David Gibson , Greg Kurz , Nicholas Piggin , Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Liu Zhiwei , Richard Henderson , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , qemu-arm@nongnu.org (open list:ARM TCG CPUs), qemu-ppc@nongnu.org (open list:PowerPC TCG CPUs), qemu-riscv@nongnu.org (open list:RISC-V TCG CPUs), qemu-s390x@nongnu.org (open list:S390 TCG CPUs) Subject: [PATCH v8 07/19] gdbstub: Use GDBFeature for gdb_register_coprocessor Date: Sat, 16 Sep 2023 17:01:24 +0900 Message-ID: <20230916080149.129989-8-akihiko.odaki@daynix.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20230916080149.129989-1-akihiko.odaki@daynix.com> References: <20230916080149.129989-1-akihiko.odaki@daynix.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=2607:f8b0:4864:20::329; envelope-from=akihiko.odaki@daynix.com; helo=mail-ot1-x329.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @daynix-com.20230601.gappssmtp.com) X-ZM-MESSAGEID: 1694851448109100003 This is a tree-wide change to introduce GDBFeature parameter to gdb_register_coprocessor(). The new parameter just replaces num_regs and xml parameters for now. GDBFeature will be utilized to simplify XML lookup in a following change. Signed-off-by: Akihiko Odaki Acked-by: Alex Benn=C3=A9e --- include/exec/gdbstub.h | 2 +- gdbstub/gdbstub.c | 13 +++++++------ target/arm/gdbstub.c | 34 ++++++++++++++++++---------------- target/hexagon/cpu.c | 3 +-- target/loongarch/gdbstub.c | 2 +- target/m68k/helper.c | 6 +++--- target/microblaze/cpu.c | 5 +++-- target/ppc/gdbstub.c | 11 ++++++----- target/riscv/gdbstub.c | 18 ++++++++++-------- target/s390x/gdbstub.c | 28 +++++++--------------------- 10 files changed, 57 insertions(+), 65 deletions(-) diff --git a/include/exec/gdbstub.h b/include/exec/gdbstub.h index d9ef2ccbff..5525eea090 100644 --- a/include/exec/gdbstub.h +++ b/include/exec/gdbstub.h @@ -37,7 +37,7 @@ typedef int (*gdb_set_reg_cb)(CPUArchState *env, uint8_t = *buf, int reg); */ void gdb_register_coprocessor(CPUState *cpu, gdb_get_reg_cb get_reg, gdb_set_reg_cb set_r= eg, - int num_regs, const char *xml, int g_pos); + const GDBFeature *feature, int g_pos); =20 /** * gdbserver_start: start the gdb server diff --git a/gdbstub/gdbstub.c b/gdbstub/gdbstub.c index d63f6c0d9d..61783ffa48 100644 --- a/gdbstub/gdbstub.c +++ b/gdbstub/gdbstub.c @@ -532,7 +532,7 @@ static int gdb_write_register(CPUState *cpu, uint8_t *m= em_buf, int reg) =20 void gdb_register_coprocessor(CPUState *cpu, gdb_get_reg_cb get_reg, gdb_set_reg_cb set_r= eg, - int num_regs, const char *xml, int g_pos) + const GDBFeature *feature, int g_pos) { GDBRegisterState *s; guint i; @@ -541,7 +541,7 @@ void gdb_register_coprocessor(CPUState *cpu, for (i =3D 0; i < cpu->gdb_regs->len; i++) { /* Check for duplicates. */ s =3D &g_array_index(cpu->gdb_regs, GDBRegisterState, i); - if (strcmp(s->xml, xml) =3D=3D 0) + if (strcmp(s->xml, feature->xmlname) =3D=3D 0) return; } } else { @@ -552,17 +552,18 @@ void gdb_register_coprocessor(CPUState *cpu, g_array_set_size(cpu->gdb_regs, i + 1); s =3D &g_array_index(cpu->gdb_regs, GDBRegisterState, i); s->base_reg =3D cpu->gdb_num_regs; - s->num_regs =3D num_regs; + s->num_regs =3D feature->num_regs; s->get_reg =3D get_reg; s->set_reg =3D set_reg; - s->xml =3D xml; + s->xml =3D feature->xml; =20 /* Add to end of list. */ - cpu->gdb_num_regs +=3D num_regs; + cpu->gdb_num_regs +=3D feature->num_regs; if (g_pos) { if (g_pos !=3D s->base_reg) { error_report("Error: Bad gdb register numbering for '%s', " - "expected %d got %d", xml, g_pos, s->base_reg); + "expected %d got %d", feature->xml, + g_pos, s->base_reg); } else { cpu->gdb_num_g_regs =3D cpu->gdb_num_regs; } diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c index fc0aa6f235..99040e0c4c 100644 --- a/target/arm/gdbstub.c +++ b/target/arm/gdbstub.c @@ -472,14 +472,14 @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *c= pu) */ #ifdef TARGET_AARCH64 if (isar_feature_aa64_sve(&cpu->isar)) { - int nreg =3D arm_gen_dynamic_svereg_feature(cs)->num_regs; + GDBFeature *feature =3D arm_gen_dynamic_svereg_feature(cs); gdb_register_coprocessor(cs, aarch64_gdb_get_sve_reg, - aarch64_gdb_set_sve_reg, nreg, - "sve-registers.xml", 0); + aarch64_gdb_set_sve_reg, feature, 0); } else { gdb_register_coprocessor(cs, aarch64_gdb_get_fpu_reg, aarch64_gdb_set_fpu_reg, - 34, "aarch64-fpu.xml", 0); + gdb_find_static_feature("aarch64-fpu.= xml"), + 0); } /* * Note that we report pauth information via the feature name @@ -490,19 +490,22 @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *c= pu) if (isar_feature_aa64_pauth(&cpu->isar)) { gdb_register_coprocessor(cs, aarch64_gdb_get_pauth_reg, aarch64_gdb_set_pauth_reg, - 4, "aarch64-pauth.xml", 0); + gdb_find_static_feature("aarch64-paut= h.xml"), + 0); } #endif } else { if (arm_feature(env, ARM_FEATURE_NEON)) { gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg, - 49, "arm-neon.xml", 0); + gdb_find_static_feature("arm-neon.xml= "), + 0); } else if (cpu_isar_feature(aa32_simd_r32, cpu)) { gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg, - 33, "arm-vfp3.xml", 0); + gdb_find_static_feature("arm-vfp3.xml= "), + 0); } else if (cpu_isar_feature(aa32_vfp_simd, cpu)) { gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg, - 17, "arm-vfp.xml", 0); + gdb_find_static_feature("arm-vfp.xml"= ), 0); } if (!arm_feature(env, ARM_FEATURE_M)) { /* @@ -510,29 +513,28 @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *c= pu) * expose to gdb. */ gdb_register_coprocessor(cs, vfp_gdb_get_sysreg, vfp_gdb_set_s= ysreg, - 2, "arm-vfp-sysregs.xml", 0); + gdb_find_static_feature("arm-vfp-sysr= egs.xml"), + 0); } } if (cpu_isar_feature(aa32_mve, cpu) && tcg_enabled()) { gdb_register_coprocessor(cs, mve_gdb_get_reg, mve_gdb_set_reg, - 1, "arm-m-profile-mve.xml", 0); + gdb_find_static_feature("arm-m-profile-mv= e.xml"), + 0); } gdb_register_coprocessor(cs, arm_gdb_get_sysreg, arm_gdb_set_sysreg, - arm_gen_dynamic_sysreg_feature(cs)->num_regs, - "system-registers.xml", 0); + arm_gen_dynamic_sysreg_feature(cs), 0); =20 #ifdef CONFIG_TCG if (arm_feature(env, ARM_FEATURE_M) && tcg_enabled()) { gdb_register_coprocessor(cs, arm_gdb_get_m_systemreg, arm_gdb_set_m_systemreg, - arm_gen_dynamic_m_systemreg_feature(cs)->num_regs, - "arm-m-system.xml", 0); + arm_gen_dynamic_m_systemreg_feature(cs), 0); #ifndef CONFIG_USER_ONLY if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { gdb_register_coprocessor(cs, arm_gdb_get_m_secextreg, arm_gdb_set_m_secextreg, - arm_gen_dynamic_m_secextreg_feature(cs)->num_regs, - "arm-m-secext.xml", 0); + arm_gen_dynamic_m_secextreg_feature(cs), 0); } #endif } diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index f155936289..1dc8e0da24 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -342,8 +342,7 @@ static void hexagon_cpu_realize(DeviceState *dev, Error= **errp) =20 gdb_register_coprocessor(cs, hexagon_hvx_gdb_read_register, hexagon_hvx_gdb_write_register, - NUM_VREGS + NUM_QREGS, - "hexagon-hvx.xml", 0); + gdb_find_static_feature("hexagon-hvx.xml"), 0= ); =20 qemu_init_vcpu(cs); cpu_reset(cs); diff --git a/target/loongarch/gdbstub.c b/target/loongarch/gdbstub.c index b09804b62f..e04742c202 100644 --- a/target/loongarch/gdbstub.c +++ b/target/loongarch/gdbstub.c @@ -117,5 +117,5 @@ static int loongarch_gdb_set_fpu(CPULoongArchState *env, void loongarch_cpu_register_gdb_regs_for_features(CPUState *cs) { gdb_register_coprocessor(cs, loongarch_gdb_get_fpu, loongarch_gdb_set_= fpu, - 41, "loongarch-fpu.xml", 0); + gdb_find_static_feature("loongarch-fpu.xml"),= 0); } diff --git a/target/m68k/helper.c b/target/m68k/helper.c index 0a1544cd68..675f2dcd5a 100644 --- a/target/m68k/helper.c +++ b/target/m68k/helper.c @@ -152,10 +152,10 @@ void m68k_cpu_init_gdb(M68kCPU *cpu) =20 if (m68k_feature(env, M68K_FEATURE_CF_FPU)) { gdb_register_coprocessor(cs, cf_fpu_gdb_get_reg, cf_fpu_gdb_set_re= g, - 11, "cf-fp.xml", 18); + gdb_find_static_feature("cf-fp.xml"), 18); } else if (m68k_feature(env, M68K_FEATURE_FPU)) { - gdb_register_coprocessor(cs, m68k_fpu_gdb_get_reg, - m68k_fpu_gdb_set_reg, 11, "m68k-fp.xml", = 18); + gdb_register_coprocessor(cs, m68k_fpu_gdb_get_reg, m68k_fpu_gdb_se= t_reg, + gdb_find_static_feature("m68k-fp.xml"), 1= 8); } /* TODO: Add [E]MAC registers. */ } diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 03c2c4db1f..e1eff0b837 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -298,8 +298,9 @@ static void mb_cpu_initfn(Object *obj) =20 cpu_set_cpustate_pointers(cpu); gdb_register_coprocessor(CPU(cpu), mb_cpu_gdb_read_stack_protect, - mb_cpu_gdb_write_stack_protect, 2, - "microblaze-stack-protect.xml", 0); + mb_cpu_gdb_write_stack_protect, + gdb_find_static_feature("microblaze-stack-pro= tect.xml"), + 0); =20 set_float_rounding_mode(float_round_nearest_even, &env->fp_status); =20 diff --git a/target/ppc/gdbstub.c b/target/ppc/gdbstub.c index 43de40ac36..9f2aad7aa9 100644 --- a/target/ppc/gdbstub.c +++ b/target/ppc/gdbstub.c @@ -567,22 +567,23 @@ void ppc_gdb_init(CPUState *cs, PowerPCCPUClass *pcc) { if (pcc->insns_flags & PPC_FLOAT) { gdb_register_coprocessor(cs, gdb_get_float_reg, gdb_set_float_reg, - 33, "power-fpu.xml", 0); + gdb_find_static_feature("power-fpu.xml"),= 0); } if (pcc->insns_flags & PPC_ALTIVEC) { gdb_register_coprocessor(cs, gdb_get_avr_reg, gdb_set_avr_reg, - 34, "power-altivec.xml", 0); + gdb_find_static_feature("power-altivec.xm= l"), + 0); } if (pcc->insns_flags & PPC_SPE) { gdb_register_coprocessor(cs, gdb_get_spe_reg, gdb_set_spe_reg, - 34, "power-spe.xml", 0); + gdb_find_static_feature("power-spe.xml"),= 0); } if (pcc->insns_flags2 & PPC2_VSX) { gdb_register_coprocessor(cs, gdb_get_vsx_reg, gdb_set_vsx_reg, - 32, "power-vsx.xml", 0); + gdb_find_static_feature("power-vsx.xml"),= 0); } #ifndef CONFIG_USER_ONLY gdb_register_coprocessor(cs, gdb_get_spr_reg, gdb_set_spr_reg, - pcc->gdb_spr.num_regs, "power-spr.xml", 0); + &pcc->gdb_spr, 0); #endif } diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c index cdae406751..d4f9eb1516 100644 --- a/target/riscv/gdbstub.c +++ b/target/riscv/gdbstub.c @@ -305,28 +305,31 @@ void riscv_cpu_register_gdb_regs_for_features(CPUStat= e *cs) CPURISCVState *env =3D &cpu->env; if (env->misa_ext & RVD) { gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu, - 32, "riscv-64bit-fpu.xml", 0); + gdb_find_static_feature("riscv-64bit-fpu.= xml"), + 0); } else if (env->misa_ext & RVF) { gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu, - 32, "riscv-32bit-fpu.xml", 0); + gdb_find_static_feature("riscv-32bit-fpu.= xml"), + 0); } if (env->misa_ext & RVV) { gdb_register_coprocessor(cs, riscv_gdb_get_vector, riscv_gdb_set_vector, - ricsv_gen_dynamic_vector_feature(cs)->num= _regs, - "riscv-vector.xml", 0); + ricsv_gen_dynamic_vector_feature(cs), 0); } switch (env->misa_mxl_max) { case MXL_RV32: gdb_register_coprocessor(cs, riscv_gdb_get_virtual, riscv_gdb_set_virtual, - 1, "riscv-32bit-virtual.xml", 0); + gdb_find_static_feature("riscv-32bit-virt= ual.xml"), + 0); break; case MXL_RV64: case MXL_RV128: gdb_register_coprocessor(cs, riscv_gdb_get_virtual, riscv_gdb_set_virtual, - 1, "riscv-64bit-virtual.xml", 0); + gdb_find_static_feature("riscv-64bit-virt= ual.xml"), + 0); break; default: g_assert_not_reached(); @@ -334,7 +337,6 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState = *cs) =20 if (cpu->cfg.ext_icsr) { gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr, - riscv_gen_dynamic_csr_feature(cs)->num_re= gs, - "riscv-csr.xml", 0); + riscv_gen_dynamic_csr_feature(cs), 0); } } diff --git a/target/s390x/gdbstub.c b/target/s390x/gdbstub.c index 6fbfd41bc8..02c388dc32 100644 --- a/target/s390x/gdbstub.c +++ b/target/s390x/gdbstub.c @@ -69,8 +69,6 @@ int s390_cpu_gdb_write_register(CPUState *cs, uint8_t *me= m_buf, int n) /* the values represent the positions in s390-acr.xml */ #define S390_A0_REGNUM 0 #define S390_A15_REGNUM 15 -/* total number of registers in s390-acr.xml */ -#define S390_NUM_AC_REGS 16 =20 static int cpu_read_ac_reg(CPUS390XState *env, GByteArray *buf, int n) { @@ -98,8 +96,6 @@ static int cpu_write_ac_reg(CPUS390XState *env, uint8_t *= mem_buf, int n) #define S390_FPC_REGNUM 0 #define S390_F0_REGNUM 1 #define S390_F15_REGNUM 16 -/* total number of registers in s390-fpr.xml */ -#define S390_NUM_FP_REGS 17 =20 static int cpu_read_fp_reg(CPUS390XState *env, GByteArray *buf, int n) { @@ -132,8 +128,6 @@ static int cpu_write_fp_reg(CPUS390XState *env, uint8_t= *mem_buf, int n) #define S390_V15L_REGNUM 15 #define S390_V16_REGNUM 16 #define S390_V31_REGNUM 31 -/* total number of registers in s390-vx.xml */ -#define S390_NUM_VREGS 32 =20 static int cpu_read_vreg(CPUS390XState *env, GByteArray *buf, int n) { @@ -172,8 +166,6 @@ static int cpu_write_vreg(CPUS390XState *env, uint8_t *= mem_buf, int n) /* the values represent the positions in s390-cr.xml */ #define S390_C0_REGNUM 0 #define S390_C15_REGNUM 15 -/* total number of registers in s390-cr.xml */ -#define S390_NUM_C_REGS 16 =20 #ifndef CONFIG_USER_ONLY static int cpu_read_c_reg(CPUS390XState *env, GByteArray *buf, int n) @@ -206,8 +198,6 @@ static int cpu_write_c_reg(CPUS390XState *env, uint8_t = *mem_buf, int n) #define S390_VIRT_CPUTM_REGNUM 1 #define S390_VIRT_BEA_REGNUM 2 #define S390_VIRT_PREFIX_REGNUM 3 -/* total number of registers in s390-virt.xml */ -#define S390_NUM_VIRT_REGS 4 =20 static int cpu_read_virt_reg(CPUS390XState *env, GByteArray *mem_buf, int = n) { @@ -254,8 +244,6 @@ static int cpu_write_virt_reg(CPUS390XState *env, uint8= _t *mem_buf, int n) #define S390_VIRT_KVM_PFT_REGNUM 1 #define S390_VIRT_KVM_PFS_REGNUM 2 #define S390_VIRT_KVM_PFC_REGNUM 3 -/* total number of registers in s390-virt-kvm.xml */ -#define S390_NUM_VIRT_KVM_REGS 4 =20 static int cpu_read_virt_kvm_reg(CPUS390XState *env, GByteArray *mem_buf, = int n) { @@ -303,8 +291,6 @@ static int cpu_write_virt_kvm_reg(CPUS390XState *env, u= int8_t *mem_buf, int n) #define S390_GS_GSD_REGNUM 1 #define S390_GS_GSSM_REGNUM 2 #define S390_GS_GSEPLA_REGNUM 3 -/* total number of registers in s390-gs.xml */ -#define S390_NUM_GS_REGS 4 =20 static int cpu_read_gs_reg(CPUS390XState *env, GByteArray *buf, int n) { @@ -322,33 +308,33 @@ void s390_cpu_gdb_init(CPUState *cs) { gdb_register_coprocessor(cs, cpu_read_ac_reg, cpu_write_ac_reg, - S390_NUM_AC_REGS, "s390-acr.xml", 0); + gdb_find_static_feature("s390-acr.xml"), 0); =20 gdb_register_coprocessor(cs, cpu_read_fp_reg, cpu_write_fp_reg, - S390_NUM_FP_REGS, "s390-fpr.xml", 0); + gdb_find_static_feature("s390-fpr.xml"), 0); =20 gdb_register_coprocessor(cs, cpu_read_vreg, cpu_write_vreg, - S390_NUM_VREGS, "s390-vx.xml", 0); + gdb_find_static_feature("s390-vx.xml"), 0); =20 gdb_register_coprocessor(cs, cpu_read_gs_reg, cpu_write_gs_reg, - S390_NUM_GS_REGS, "s390-gs.xml", 0); + gdb_find_static_feature("s390-gs.xml"), 0); =20 #ifndef CONFIG_USER_ONLY gdb_register_coprocessor(cs, cpu_read_c_reg, cpu_write_c_reg, - S390_NUM_C_REGS, "s390-cr.xml", 0); + gdb_find_static_feature("s390-cr.xml"), 0); =20 gdb_register_coprocessor(cs, cpu_read_virt_reg, cpu_write_virt_reg, - S390_NUM_VIRT_REGS, "s390-virt.xml", 0); + gdb_find_static_feature("s390-virt.xml"), 0); =20 if (kvm_enabled()) { gdb_register_coprocessor(cs, cpu_read_virt_kvm_reg, cpu_write_virt_kvm_reg, - S390_NUM_VIRT_KVM_REGS, "s390-virt-kvm.xm= l", + gdb_find_static_feature("s390-virt-kvm.xm= l"), 0); } #endif --=20 2.42.0