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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=2607:f8b0:4864:20::429; envelope-from=akihiko.odaki@daynix.com; helo=mail-pf1-x429.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @daynix-com.20230601.gappssmtp.com) X-ZM-MESSAGEID: 1694851414671100003 Content-Type: text/plain; charset="utf-8" In preparation for a change to use GDBFeature as a parameter of gdb_register_coprocessor(), convert the internal representation of dynamic feature from plain XML to GDBFeature. Signed-off-by: Akihiko Odaki --- target/riscv/cpu.h | 5 +-- target/riscv/cpu.c | 4 +-- target/riscv/gdbstub.c | 77 ++++++++++++++++++------------------------ 3 files changed, 38 insertions(+), 48 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 6ea22e0eea..9063aa1fca 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -23,6 +23,7 @@ #include "hw/core/cpu.h" #include "hw/registerfields.h" #include "exec/cpu-defs.h" +#include "exec/gdbstub.h" #include "qemu/cpu-float.h" #include "qom/object.h" #include "qemu/int128.h" @@ -391,8 +392,8 @@ struct ArchCPU { CPUNegativeOffsetState neg; CPURISCVState env; =20 - char *dyn_csr_xml; - char *dyn_vreg_xml; + GDBFeature dyn_csr_feature; + GDBFeature dyn_vreg_feature; =20 /* Configuration Settings */ RISCVCPUConfig cfg; diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index ef8faaaff5..a03c9069ca 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1960,9 +1960,9 @@ static const char *riscv_gdb_get_dynamic_xml(CPUState= *cs, const char *xmlname) RISCVCPU *cpu =3D RISCV_CPU(cs); =20 if (strcmp(xmlname, "riscv-csr.xml") =3D=3D 0) { - return cpu->dyn_csr_xml; + return cpu->dyn_csr_feature.xml; } else if (strcmp(xmlname, "riscv-vector.xml") =3D=3D 0) { - return cpu->dyn_vreg_xml; + return cpu->dyn_vreg_feature.xml; } =20 return NULL; diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c index 524bede865..cdae406751 100644 --- a/target/riscv/gdbstub.c +++ b/target/riscv/gdbstub.c @@ -212,12 +212,13 @@ static int riscv_gdb_set_virtual(CPURISCVState *cs, u= int8_t *mem_buf, int n) return 0; } =20 -static int riscv_gen_dynamic_csr_xml(CPUState *cs, int base_reg) +static GDBFeature *riscv_gen_dynamic_csr_feature(CPUState *cs) { RISCVCPU *cpu =3D RISCV_CPU(cs); CPURISCVState *env =3D &cpu->env; - GString *s =3D g_string_new(NULL); + GDBFeatureBuilder builder; riscv_csr_predicate_fn predicate; + const char *name; int bitsize =3D 16 << env->misa_mxl_max; int i; =20 @@ -230,9 +231,8 @@ static int riscv_gen_dynamic_csr_xml(CPUState *cs, int = base_reg) bitsize =3D 64; } =20 - g_string_printf(s, ""); - g_string_append_printf(s, ""); - g_string_append_printf(s, ""= ); + gdb_feature_builder_init(&builder, &cpu->dyn_csr_feature, + "org.gnu.gdb.riscv.csr", "riscv-csr.xml"); =20 for (i =3D 0; i < CSR_TABLE_SIZE; i++) { if (env->priv_ver < csr_ops[i].min_priv_ver) { @@ -240,72 +240,63 @@ static int riscv_gen_dynamic_csr_xml(CPUState *cs, in= t base_reg) } predicate =3D csr_ops[i].predicate; if (predicate && (predicate(env, i) =3D=3D RISCV_EXCP_NONE)) { - if (csr_ops[i].name) { - g_string_append_printf(s, "", base_reg + i); + + gdb_feature_builder_append_reg(&builder, name, bitsize, + "int", NULL); } } =20 - g_string_append_printf(s, ""); - - cpu->dyn_csr_xml =3D g_string_free(s, false); + gdb_feature_builder_end(&builder); =20 #if !defined(CONFIG_USER_ONLY) env->debugger =3D false; #endif =20 - return CSR_TABLE_SIZE; + return &cpu->dyn_csr_feature; } =20 -static int ricsv_gen_dynamic_vector_xml(CPUState *cs, int base_reg) +static GDBFeature *ricsv_gen_dynamic_vector_feature(CPUState *cs) { RISCVCPU *cpu =3D RISCV_CPU(cs); - GString *s =3D g_string_new(NULL); - g_autoptr(GString) ts =3D g_string_new(""); + GDBFeatureBuilder builder; int reg_width =3D cpu->cfg.vlen; - int num_regs =3D 0; int i; =20 - g_string_printf(s, ""); - g_string_append_printf(s, "= "); - g_string_append_printf(s, ""); + gdb_feature_builder_init(&builder, &cpu->dyn_vreg_feature, + "org.gnu.gdb.riscv.vector", "riscv-vector.xml= "); =20 /* First define types and totals in a whole VL */ for (i =3D 0; i < ARRAY_SIZE(vec_lanes); i++) { int count =3D reg_width / vec_lanes[i].size; - g_string_printf(ts, "%s", vec_lanes[i].id); - g_string_append_printf(s, - "", - ts->str, vec_lanes[i].gdb_type, count); + gdb_feature_builder_append_tag( + &builder, "", + vec_lanes[i].id, vec_lanes[i].gdb_type, count); } =20 /* Define unions */ - g_string_append_printf(s, ""); + gdb_feature_builder_append_tag(&builder, ""); for (i =3D 0; i < ARRAY_SIZE(vec_lanes); i++) { - g_string_append_printf(s, "", - vec_lanes[i].suffix, - vec_lanes[i].id); + gdb_feature_builder_append_tag(&builder, + "", + vec_lanes[i].suffix, vec_lanes[i].i= d); } - g_string_append(s, ""); + gdb_feature_builder_append_tag(&builder, ""); =20 /* Define vector registers */ for (i =3D 0; i < 32; i++) { - g_string_append_printf(s, - "", - i, reg_width, base_reg++); - num_regs++; + gdb_feature_builder_append_reg(&builder, g_strdup_printf("v%d", i), + reg_width, "riscv_vector", "vector"= ); } =20 - g_string_append_printf(s, ""); + gdb_feature_builder_end(&builder); =20 - cpu->dyn_vreg_xml =3D g_string_free(s, false); - return num_regs; + return &cpu->dyn_vreg_feature; } =20 void riscv_cpu_register_gdb_regs_for_features(CPUState *cs) @@ -320,10 +311,9 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState= *cs) 32, "riscv-32bit-fpu.xml", 0); } if (env->misa_ext & RVV) { - int base_reg =3D cs->gdb_num_regs; gdb_register_coprocessor(cs, riscv_gdb_get_vector, riscv_gdb_set_vector, - ricsv_gen_dynamic_vector_xml(cs, base_reg= ), + ricsv_gen_dynamic_vector_feature(cs)->num= _regs, "riscv-vector.xml", 0); } switch (env->misa_mxl_max) { @@ -343,9 +333,8 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState = *cs) } =20 if (cpu->cfg.ext_icsr) { - int base_reg =3D cs->gdb_num_regs; gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr, - riscv_gen_dynamic_csr_xml(cs, base_reg), + riscv_gen_dynamic_csr_feature(cs)->num_re= gs, "riscv-csr.xml", 0); } } --=20 2.42.0