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Iglesias" , Daniel Henrique Barboza , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , David Gibson , Greg Kurz , Nicholas Piggin , Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Liu Zhiwei , Richard Henderson , David Hildenbrand , Ilya Leoshkevich , Thomas Huth , qemu-arm@nongnu.org (open list:ARM TCG CPUs), qemu-ppc@nongnu.org (open list:PowerPC TCG CPUs), qemu-riscv@nongnu.org (open list:RISC-V TCG CPUs), qemu-s390x@nongnu.org (open list:S390 TCG CPUs) Subject: [PATCH v8 09/19] gdbstub: Change gdb_get_reg_cb and gdb_set_reg_cb Date: Sat, 16 Sep 2023 17:01:26 +0900 Message-ID: <20230916080149.129989-10-akihiko.odaki@daynix.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20230916080149.129989-1-akihiko.odaki@daynix.com> References: <20230916080149.129989-1-akihiko.odaki@daynix.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=2607:f8b0:4864:20::435; envelope-from=akihiko.odaki@daynix.com; helo=mail-pf1-x435.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @daynix-com.20230601.gappssmtp.com) X-ZM-MESSAGEID: 1694851595479100003 Content-Type: text/plain; charset="utf-8" Align the parameters of gdb_get_reg_cb and gdb_set_reg_cb with the gdb_read_register and gdb_write_register members of CPUClass to allow to unify the logic to access registers of the core and coprocessors in the future. Signed-off-by: Akihiko Odaki --- include/exec/gdbstub.h | 4 +- target/arm/internals.h | 12 +++--- target/hexagon/internal.h | 4 +- target/microblaze/cpu.h | 4 +- gdbstub/gdbstub.c | 6 +-- target/arm/gdbstub.c | 51 ++++++++++++++++-------- target/arm/gdbstub64.c | 27 +++++++++---- target/hexagon/gdbstub.c | 10 ++++- target/loongarch/gdbstub.c | 11 ++++-- target/m68k/helper.c | 20 ++++++++-- target/microblaze/gdbstub.c | 9 ++++- target/ppc/gdbstub.c | 46 +++++++++++++++++----- target/riscv/gdbstub.c | 46 ++++++++++++++++------ target/s390x/gdbstub.c | 77 ++++++++++++++++++++++++++++--------- 14 files changed, 236 insertions(+), 91 deletions(-) diff --git a/include/exec/gdbstub.h b/include/exec/gdbstub.h index 5525eea090..38b8db29f7 100644 --- a/include/exec/gdbstub.h +++ b/include/exec/gdbstub.h @@ -23,8 +23,8 @@ typedef struct GDBFeatureBuilder { =20 =20 /* Get or set a register. Returns the size of the register. */ -typedef int (*gdb_get_reg_cb)(CPUArchState *env, GByteArray *buf, int reg); -typedef int (*gdb_set_reg_cb)(CPUArchState *env, uint8_t *buf, int reg); +typedef int (*gdb_get_reg_cb)(CPUState *cpu, GByteArray *buf, int reg); +typedef int (*gdb_set_reg_cb)(CPUState *cpu, uint8_t *buf, int reg); =20 /** * gdb_register_coprocessor() - register a supplemental set of registers diff --git a/target/arm/internals.h b/target/arm/internals.h index 58f1a66f8d..5240d86619 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1386,12 +1386,12 @@ static inline uint64_t pmu_counter_mask(CPUARMState= *env) =20 #ifdef TARGET_AARCH64 GDBFeature *arm_gen_dynamic_svereg_feature(CPUState *cpu); -int aarch64_gdb_get_sve_reg(CPUARMState *env, GByteArray *buf, int reg); -int aarch64_gdb_set_sve_reg(CPUARMState *env, uint8_t *buf, int reg); -int aarch64_gdb_get_fpu_reg(CPUARMState *env, GByteArray *buf, int reg); -int aarch64_gdb_set_fpu_reg(CPUARMState *env, uint8_t *buf, int reg); -int aarch64_gdb_get_pauth_reg(CPUARMState *env, GByteArray *buf, int reg); -int aarch64_gdb_set_pauth_reg(CPUARMState *env, uint8_t *buf, int reg); +int aarch64_gdb_get_sve_reg(CPUState *cs, GByteArray *buf, int reg); +int aarch64_gdb_set_sve_reg(CPUState *cs, uint8_t *buf, int reg); +int aarch64_gdb_get_fpu_reg(CPUState *cs, GByteArray *buf, int reg); +int aarch64_gdb_set_fpu_reg(CPUState *cs, uint8_t *buf, int reg); +int aarch64_gdb_get_pauth_reg(CPUState *cs, GByteArray *buf, int reg); +int aarch64_gdb_set_pauth_reg(CPUState *cs, uint8_t *buf, int reg); void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp); void arm_cpu_sme_finalize(ARMCPU *cpu, Error **errp); void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp); diff --git a/target/hexagon/internal.h b/target/hexagon/internal.h index d732b6bb3c..beb08cb7e3 100644 --- a/target/hexagon/internal.h +++ b/target/hexagon/internal.h @@ -33,8 +33,8 @@ =20 int hexagon_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int hexagon_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); -int hexagon_hvx_gdb_read_register(CPUHexagonState *env, GByteArray *mem_bu= f, int n); -int hexagon_hvx_gdb_write_register(CPUHexagonState *env, uint8_t *mem_buf,= int n); +int hexagon_hvx_gdb_read_register(CPUState *env, GByteArray *mem_buf, int = n); +int hexagon_hvx_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n); =20 void hexagon_debug_vreg(CPUHexagonState *env, int regnum); void hexagon_debug_qreg(CPUHexagonState *env, int regnum); diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index f6cab6ce19..820d3c261e 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -370,8 +370,8 @@ G_NORETURN void mb_cpu_do_unaligned_access(CPUState *cs= , vaddr vaddr, void mb_cpu_dump_state(CPUState *cpu, FILE *f, int flags); int mb_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int mb_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); -int mb_cpu_gdb_read_stack_protect(CPUArchState *cpu, GByteArray *buf, int = reg); -int mb_cpu_gdb_write_stack_protect(CPUArchState *cpu, uint8_t *buf, int re= g); +int mb_cpu_gdb_read_stack_protect(CPUState *cs, GByteArray *buf, int reg); +int mb_cpu_gdb_write_stack_protect(CPUState *cs, uint8_t *buf, int reg); =20 static inline uint32_t mb_cpu_read_msr(const CPUMBState *env) { diff --git a/gdbstub/gdbstub.c b/gdbstub/gdbstub.c index b3f6f0dd2d..fb9f56bd4a 100644 --- a/gdbstub/gdbstub.c +++ b/gdbstub/gdbstub.c @@ -494,7 +494,6 @@ const GDBFeature *gdb_find_static_feature(const char *x= mlname) static int gdb_read_register(CPUState *cpu, GByteArray *buf, int reg) { CPUClass *cc =3D CPU_GET_CLASS(cpu); - CPUArchState *env =3D cpu->env_ptr; GDBRegisterState *r; =20 if (reg < cc->gdb_num_core_regs) { @@ -504,7 +503,7 @@ static int gdb_read_register(CPUState *cpu, GByteArray = *buf, int reg) for (guint i =3D 0; i < cpu->gdb_regs->len; i++) { r =3D &g_array_index(cpu->gdb_regs, GDBRegisterState, i); if (r->base_reg <=3D reg && reg < r->base_reg + r->feature->num_re= gs) { - return r->get_reg(env, buf, reg - r->base_reg); + return r->get_reg(cpu, buf, reg - r->base_reg); } } return 0; @@ -513,7 +512,6 @@ static int gdb_read_register(CPUState *cpu, GByteArray = *buf, int reg) static int gdb_write_register(CPUState *cpu, uint8_t *mem_buf, int reg) { CPUClass *cc =3D CPU_GET_CLASS(cpu); - CPUArchState *env =3D cpu->env_ptr; GDBRegisterState *r; =20 if (reg < cc->gdb_num_core_regs) { @@ -523,7 +521,7 @@ static int gdb_write_register(CPUState *cpu, uint8_t *m= em_buf, int reg) for (guint i =3D 0; i < cpu->gdb_regs->len; i++) { r =3D &g_array_index(cpu->gdb_regs, GDBRegisterState, i); if (r->base_reg <=3D reg && reg < r->base_reg + r->feature->num_re= gs) { - return r->set_reg(env, mem_buf, reg - r->base_reg); + return r->set_reg(cpu, mem_buf, reg - r->base_reg); } } return 0; diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c index 99040e0c4c..aa2c6c1bde 100644 --- a/target/arm/gdbstub.c +++ b/target/arm/gdbstub.c @@ -104,9 +104,10 @@ int arm_cpu_gdb_write_register(CPUState *cs, uint8_t *= mem_buf, int n) return 0; } =20 -static int vfp_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg) +static int vfp_gdb_get_reg(CPUState *cs, GByteArray *buf, int reg) { - ARMCPU *cpu =3D env_archcpu(env); + ARMCPU *cpu =3D ARM_CPU(cs); + CPUARMState *env =3D &cpu->env; int nregs =3D cpu_isar_feature(aa32_simd_r32, cpu) ? 32 : 16; =20 /* VFP data registers are always little-endian. */ @@ -128,9 +129,10 @@ static int vfp_gdb_get_reg(CPUARMState *env, GByteArra= y *buf, int reg) return 0; } =20 -static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg) +static int vfp_gdb_set_reg(CPUState *cs, uint8_t *buf, int reg) { - ARMCPU *cpu =3D env_archcpu(env); + ARMCPU *cpu =3D ARM_CPU(cs); + CPUARMState *env =3D &cpu->env; int nregs =3D cpu_isar_feature(aa32_simd_r32, cpu) ? 32 : 16; =20 if (reg < nregs) { @@ -154,8 +156,11 @@ static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *= buf, int reg) return 0; } =20 -static int vfp_gdb_get_sysreg(CPUARMState *env, GByteArray *buf, int reg) +static int vfp_gdb_get_sysreg(CPUState *cs, GByteArray *buf, int reg) { + ARMCPU *cpu =3D ARM_CPU(cs); + CPUARMState *env =3D &cpu->env; + switch (reg) { case 0: return gdb_get_reg32(buf, env->vfp.xregs[ARM_VFP_FPSID]); @@ -165,8 +170,11 @@ static int vfp_gdb_get_sysreg(CPUARMState *env, GByteA= rray *buf, int reg) return 0; } =20 -static int vfp_gdb_set_sysreg(CPUARMState *env, uint8_t *buf, int reg) +static int vfp_gdb_set_sysreg(CPUState *cs, uint8_t *buf, int reg) { + ARMCPU *cpu =3D ARM_CPU(cs); + CPUARMState *env =3D &cpu->env; + switch (reg) { case 0: env->vfp.xregs[ARM_VFP_FPSID] =3D ldl_p(buf); @@ -178,8 +186,11 @@ static int vfp_gdb_set_sysreg(CPUARMState *env, uint8_= t *buf, int reg) return 0; } =20 -static int mve_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg) +static int mve_gdb_get_reg(CPUState *cs, GByteArray *buf, int reg) { + ARMCPU *cpu =3D ARM_CPU(cs); + CPUARMState *env =3D &cpu->env; + switch (reg) { case 0: return gdb_get_reg32(buf, env->v7m.vpr); @@ -188,8 +199,11 @@ static int mve_gdb_get_reg(CPUARMState *env, GByteArra= y *buf, int reg) } } =20 -static int mve_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg) +static int mve_gdb_set_reg(CPUState *cs, uint8_t *buf, int reg) { + ARMCPU *cpu =3D ARM_CPU(cs); + CPUARMState *env =3D &cpu->env; + switch (reg) { case 0: env->v7m.vpr =3D ldl_p(buf); @@ -208,9 +222,10 @@ static int mve_gdb_set_reg(CPUARMState *env, uint8_t *= buf, int reg) * We return the number of bytes copied */ =20 -static int arm_gdb_get_sysreg(CPUARMState *env, GByteArray *buf, int reg) +static int arm_gdb_get_sysreg(CPUState *cs, GByteArray *buf, int reg) { - ARMCPU *cpu =3D env_archcpu(env); + ARMCPU *cpu =3D ARM_CPU(cs); + CPUARMState *env =3D &cpu->env; const ARMCPRegInfo *ri; uint32_t key; =20 @@ -226,7 +241,7 @@ static int arm_gdb_get_sysreg(CPUARMState *env, GByteAr= ray *buf, int reg) return 0; } =20 -static int arm_gdb_set_sysreg(CPUARMState *env, uint8_t *buf, int reg) +static int arm_gdb_set_sysreg(CPUState *cs, uint8_t *buf, int reg) { return 0; } @@ -364,8 +379,11 @@ static int m_sysreg_get(CPUARMState *env, GByteArray *= buf, return gdb_get_reg32(buf, *ptr); } =20 -static int arm_gdb_get_m_systemreg(CPUARMState *env, GByteArray *buf, int = reg) +static int arm_gdb_get_m_systemreg(CPUState *cs, GByteArray *buf, int reg) { + ARMCPU *cpu =3D ARM_CPU(cs); + CPUARMState *env =3D &cpu->env; + /* * Here, we emulate MRS instruction, where CONTROL has a mix of * banked and non-banked bits. @@ -376,7 +394,7 @@ static int arm_gdb_get_m_systemreg(CPUARMState *env, GB= yteArray *buf, int reg) return m_sysreg_get(env, buf, reg, env->v7m.secure); } =20 -static int arm_gdb_set_m_systemreg(CPUARMState *env, uint8_t *buf, int reg) +static int arm_gdb_set_m_systemreg(CPUState *cs, uint8_t *buf, int reg) { return 0; /* TODO */ } @@ -408,12 +426,15 @@ static GDBFeature *arm_gen_dynamic_m_systemreg_featur= e(CPUState *cs) * For user-only, we see the non-secure registers via m_systemreg above. * For secext, encode the non-secure view as even and secure view as odd. */ -static int arm_gdb_get_m_secextreg(CPUARMState *env, GByteArray *buf, int = reg) +static int arm_gdb_get_m_secextreg(CPUState *cs, GByteArray *buf, int reg) { + ARMCPU *cpu =3D ARM_CPU(cs); + CPUARMState *env =3D &cpu->env; + return m_sysreg_get(env, buf, reg >> 1, reg & 1); } =20 -static int arm_gdb_set_m_secextreg(CPUARMState *env, uint8_t *buf, int reg) +static int arm_gdb_set_m_secextreg(CPUState *cs, uint8_t *buf, int reg) { return 0; /* TODO */ } diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c index 632ac2a520..b7978bdf02 100644 --- a/target/arm/gdbstub64.c +++ b/target/arm/gdbstub64.c @@ -72,8 +72,11 @@ int aarch64_cpu_gdb_write_register(CPUState *cs, uint8_t= *mem_buf, int n) return 0; } =20 -int aarch64_gdb_get_fpu_reg(CPUARMState *env, GByteArray *buf, int reg) +int aarch64_gdb_get_fpu_reg(CPUState *cs, GByteArray *buf, int reg) { + ARMCPU *cpu =3D ARM_CPU(cs); + CPUARMState *env =3D &cpu->env; + switch (reg) { case 0 ... 31: { @@ -92,8 +95,11 @@ int aarch64_gdb_get_fpu_reg(CPUARMState *env, GByteArray= *buf, int reg) } } =20 -int aarch64_gdb_set_fpu_reg(CPUARMState *env, uint8_t *buf, int reg) +int aarch64_gdb_set_fpu_reg(CPUState *cs, uint8_t *buf, int reg) { + ARMCPU *cpu =3D ARM_CPU(cs); + CPUARMState *env =3D &cpu->env; + switch (reg) { case 0 ... 31: /* 128 bit FP register */ @@ -116,9 +122,10 @@ int aarch64_gdb_set_fpu_reg(CPUARMState *env, uint8_t = *buf, int reg) } } =20 -int aarch64_gdb_get_sve_reg(CPUARMState *env, GByteArray *buf, int reg) +int aarch64_gdb_get_sve_reg(CPUState *cs, GByteArray *buf, int reg) { - ARMCPU *cpu =3D env_archcpu(env); + ARMCPU *cpu =3D ARM_CPU(cs); + CPUARMState *env =3D &cpu->env; =20 switch (reg) { /* The first 32 registers are the zregs */ @@ -164,9 +171,10 @@ int aarch64_gdb_get_sve_reg(CPUARMState *env, GByteArr= ay *buf, int reg) return 0; } =20 -int aarch64_gdb_set_sve_reg(CPUARMState *env, uint8_t *buf, int reg) +int aarch64_gdb_set_sve_reg(CPUState *cs, uint8_t *buf, int reg) { - ARMCPU *cpu =3D env_archcpu(env); + ARMCPU *cpu =3D ARM_CPU(cs); + CPUARMState *env =3D &cpu->env; =20 /* The first 32 registers are the zregs */ switch (reg) { @@ -210,8 +218,11 @@ int aarch64_gdb_set_sve_reg(CPUARMState *env, uint8_t = *buf, int reg) return 0; } =20 -int aarch64_gdb_get_pauth_reg(CPUARMState *env, GByteArray *buf, int reg) +int aarch64_gdb_get_pauth_reg(CPUState *cs, GByteArray *buf, int reg) { + ARMCPU *cpu =3D ARM_CPU(cs); + CPUARMState *env =3D &cpu->env; + switch (reg) { case 0: /* pauth_dmask */ case 1: /* pauth_cmask */ @@ -241,7 +252,7 @@ int aarch64_gdb_get_pauth_reg(CPUARMState *env, GByteAr= ray *buf, int reg) } } =20 -int aarch64_gdb_set_pauth_reg(CPUARMState *env, uint8_t *buf, int reg) +int aarch64_gdb_set_pauth_reg(CPUState *cs, uint8_t *buf, int reg) { /* All pseudo registers are read-only. */ return 0; diff --git a/target/hexagon/gdbstub.c b/target/hexagon/gdbstub.c index 54d37e006e..6007e6462b 100644 --- a/target/hexagon/gdbstub.c +++ b/target/hexagon/gdbstub.c @@ -81,8 +81,11 @@ static int gdb_get_qreg(CPUHexagonState *env, GByteArray= *mem_buf, int n) return total; } =20 -int hexagon_hvx_gdb_read_register(CPUHexagonState *env, GByteArray *mem_bu= f, int n) +int hexagon_hvx_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) { + HexagonCPU *cpu =3D HEXAGON_CPU(cs); + CPUHexagonState *env =3D &cpu->env; + if (n < NUM_VREGS) { return gdb_get_vreg(env, mem_buf, n); } @@ -115,8 +118,11 @@ static int gdb_put_qreg(CPUHexagonState *env, uint8_t = *mem_buf, int n) return MAX_VEC_SIZE_BYTES / 8; } =20 -int hexagon_hvx_gdb_write_register(CPUHexagonState *env, uint8_t *mem_buf,= int n) +int hexagon_hvx_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) { + HexagonCPU *cpu =3D HEXAGON_CPU(cs); + CPUHexagonState *env =3D &cpu->env; + if (n < NUM_VREGS) { return gdb_put_vreg(env, mem_buf, n); } diff --git a/target/loongarch/gdbstub.c b/target/loongarch/gdbstub.c index e04742c202..2da5d2aef7 100644 --- a/target/loongarch/gdbstub.c +++ b/target/loongarch/gdbstub.c @@ -83,9 +83,11 @@ int loongarch_cpu_gdb_write_register(CPUState *cs, uint8= _t *mem_buf, int n) return length; } =20 -static int loongarch_gdb_get_fpu(CPULoongArchState *env, - GByteArray *mem_buf, int n) +static int loongarch_gdb_get_fpu(CPUState *cs, GByteArray *mem_buf, int n) { + LoongArchCPU *cpu =3D LOONGARCH_CPU(cs); + CPULoongArchState *env =3D &cpu->env; + if (0 <=3D n && n < 32) { return gdb_get_reg64(mem_buf, env->fpr[n].vreg.D(0)); } else if (32 <=3D n && n < 40) { @@ -96,9 +98,10 @@ static int loongarch_gdb_get_fpu(CPULoongArchState *env, return 0; } =20 -static int loongarch_gdb_set_fpu(CPULoongArchState *env, - uint8_t *mem_buf, int n) +static int loongarch_gdb_set_fpu(CPUState *cs, uint8_t *mem_buf, int n) { + LoongArchCPU *cpu =3D LOONGARCH_CPU(cs); + CPULoongArchState *env =3D &cpu->env; int length =3D 0; =20 if (0 <=3D n && n < 32) { diff --git a/target/m68k/helper.c b/target/m68k/helper.c index 675f2dcd5a..a5ee4d87e3 100644 --- a/target/m68k/helper.c +++ b/target/m68k/helper.c @@ -69,8 +69,11 @@ void m68k_cpu_list(void) g_slist_free(list); } =20 -static int cf_fpu_gdb_get_reg(CPUM68KState *env, GByteArray *mem_buf, int = n) +static int cf_fpu_gdb_get_reg(CPUState *cs, GByteArray *mem_buf, int n) { + M68kCPU *cpu =3D M68K_CPU(cs); + CPUM68KState *env =3D &cpu->env; + if (n < 8) { float_status s; return gdb_get_reg64(mem_buf, floatx80_to_float64(env->fregs[n].d,= &s)); @@ -86,8 +89,11 @@ static int cf_fpu_gdb_get_reg(CPUM68KState *env, GByteAr= ray *mem_buf, int n) return 0; } =20 -static int cf_fpu_gdb_set_reg(CPUM68KState *env, uint8_t *mem_buf, int n) +static int cf_fpu_gdb_set_reg(CPUState *cs, uint8_t *mem_buf, int n) { + M68kCPU *cpu =3D M68K_CPU(cs); + CPUM68KState *env =3D &cpu->env; + if (n < 8) { float_status s; env->fregs[n].d =3D float64_to_floatx80(ldq_p(mem_buf), &s); @@ -106,8 +112,11 @@ static int cf_fpu_gdb_set_reg(CPUM68KState *env, uint8= _t *mem_buf, int n) return 0; } =20 -static int m68k_fpu_gdb_get_reg(CPUM68KState *env, GByteArray *mem_buf, in= t n) +static int m68k_fpu_gdb_get_reg(CPUState *cs, GByteArray *mem_buf, int n) { + M68kCPU *cpu =3D M68K_CPU(cs); + CPUM68KState *env =3D &cpu->env; + if (n < 8) { int len =3D gdb_get_reg16(mem_buf, env->fregs[n].l.upper); len +=3D gdb_get_reg16(mem_buf, 0); @@ -125,8 +134,11 @@ static int m68k_fpu_gdb_get_reg(CPUM68KState *env, GBy= teArray *mem_buf, int n) return 0; } =20 -static int m68k_fpu_gdb_set_reg(CPUM68KState *env, uint8_t *mem_buf, int n) +static int m68k_fpu_gdb_set_reg(CPUState *cs, uint8_t *mem_buf, int n) { + M68kCPU *cpu =3D M68K_CPU(cs); + CPUM68KState *env =3D &cpu->env; + if (n < 8) { env->fregs[n].l.upper =3D lduw_be_p(mem_buf); env->fregs[n].l.lower =3D ldq_be_p(mem_buf + 4); diff --git a/target/microblaze/gdbstub.c b/target/microblaze/gdbstub.c index 29ac6e9c0f..6ffc5ad075 100644 --- a/target/microblaze/gdbstub.c +++ b/target/microblaze/gdbstub.c @@ -94,8 +94,10 @@ int mb_cpu_gdb_read_register(CPUState *cs, GByteArray *m= em_buf, int n) return gdb_get_reg32(mem_buf, val); } =20 -int mb_cpu_gdb_read_stack_protect(CPUMBState *env, GByteArray *mem_buf, in= t n) +int mb_cpu_gdb_read_stack_protect(CPUState *cs, GByteArray *mem_buf, int n) { + MicroBlazeCPU *cpu =3D MICROBLAZE_CPU(cs); + CPUMBState *env =3D &cpu->env; uint32_t val; =20 switch (n) { @@ -153,8 +155,11 @@ int mb_cpu_gdb_write_register(CPUState *cs, uint8_t *m= em_buf, int n) return 4; } =20 -int mb_cpu_gdb_write_stack_protect(CPUMBState *env, uint8_t *mem_buf, int = n) +int mb_cpu_gdb_write_stack_protect(CPUState *cs, uint8_t *mem_buf, int n) { + MicroBlazeCPU *cpu =3D MICROBLAZE_CPU(cs); + CPUMBState *env =3D &cpu->env; + switch (n) { case GDB_SP_SHL: env->slr =3D ldl_p(mem_buf); diff --git a/target/ppc/gdbstub.c b/target/ppc/gdbstub.c index 9f2aad7aa9..2392625441 100644 --- a/target/ppc/gdbstub.c +++ b/target/ppc/gdbstub.c @@ -366,8 +366,10 @@ static int gdb_find_spr_idx(CPUPPCState *env, int n) return -1; } =20 -static int gdb_get_spr_reg(CPUPPCState *env, GByteArray *buf, int n) +static int gdb_get_spr_reg(CPUState *cs, GByteArray *buf, int n) { + PowerPCCPU *cpu =3D POWERPC_CPU(cs); + CPUPPCState *env =3D &cpu->env; int reg; int len; =20 @@ -382,8 +384,10 @@ static int gdb_get_spr_reg(CPUPPCState *env, GByteArra= y *buf, int n) return len; } =20 -static int gdb_set_spr_reg(CPUPPCState *env, uint8_t *mem_buf, int n) +static int gdb_set_spr_reg(CPUState *cs, uint8_t *mem_buf, int n) { + PowerPCCPU *cpu =3D POWERPC_CPU(cs); + CPUPPCState *env =3D &cpu->env; int reg; int len; =20 @@ -400,8 +404,10 @@ static int gdb_set_spr_reg(CPUPPCState *env, uint8_t *= mem_buf, int n) } #endif =20 -static int gdb_get_float_reg(CPUPPCState *env, GByteArray *buf, int n) +static int gdb_get_float_reg(CPUState *cs, GByteArray *buf, int n) { + PowerPCCPU *cpu =3D POWERPC_CPU(cs); + CPUPPCState *env =3D &cpu->env; uint8_t *mem_buf; if (n < 32) { gdb_get_reg64(buf, *cpu_fpr_ptr(env, n)); @@ -418,8 +424,11 @@ static int gdb_get_float_reg(CPUPPCState *env, GByteAr= ray *buf, int n) return 0; } =20 -static int gdb_set_float_reg(CPUPPCState *env, uint8_t *mem_buf, int n) +static int gdb_set_float_reg(CPUState *cs, uint8_t *mem_buf, int n) { + PowerPCCPU *cpu =3D POWERPC_CPU(cs); + CPUPPCState *env =3D &cpu->env; + if (n < 32) { ppc_maybe_bswap_register(env, mem_buf, 8); *cpu_fpr_ptr(env, n) =3D ldq_p(mem_buf); @@ -433,8 +442,10 @@ static int gdb_set_float_reg(CPUPPCState *env, uint8_t= *mem_buf, int n) return 0; } =20 -static int gdb_get_avr_reg(CPUPPCState *env, GByteArray *buf, int n) +static int gdb_get_avr_reg(CPUState *cs, GByteArray *buf, int n) { + PowerPCCPU *cpu =3D POWERPC_CPU(cs); + CPUPPCState *env =3D &cpu->env; uint8_t *mem_buf; =20 if (n < 32) { @@ -459,8 +470,11 @@ static int gdb_get_avr_reg(CPUPPCState *env, GByteArra= y *buf, int n) return 0; } =20 -static int gdb_set_avr_reg(CPUPPCState *env, uint8_t *mem_buf, int n) +static int gdb_set_avr_reg(CPUState *cs, uint8_t *mem_buf, int n) { + PowerPCCPU *cpu =3D POWERPC_CPU(cs); + CPUPPCState *env =3D &cpu->env; + if (n < 32) { ppc_avr_t *avr =3D cpu_avr_ptr(env, n); ppc_maybe_bswap_register(env, mem_buf, 16); @@ -481,8 +495,11 @@ static int gdb_set_avr_reg(CPUPPCState *env, uint8_t *= mem_buf, int n) return 0; } =20 -static int gdb_get_spe_reg(CPUPPCState *env, GByteArray *buf, int n) +static int gdb_get_spe_reg(CPUState *cs, GByteArray *buf, int n) { + PowerPCCPU *cpu =3D POWERPC_CPU(cs); + CPUPPCState *env =3D &cpu->env; + if (n < 32) { #if defined(TARGET_PPC64) gdb_get_reg32(buf, env->gpr[n] >> 32); @@ -505,8 +522,11 @@ static int gdb_get_spe_reg(CPUPPCState *env, GByteArra= y *buf, int n) return 0; } =20 -static int gdb_set_spe_reg(CPUPPCState *env, uint8_t *mem_buf, int n) +static int gdb_set_spe_reg(CPUState *cs, uint8_t *mem_buf, int n) { + PowerPCCPU *cpu =3D POWERPC_CPU(cs); + CPUPPCState *env =3D &cpu->env; + if (n < 32) { #if defined(TARGET_PPC64) target_ulong lo =3D (uint32_t)env->gpr[n]; @@ -534,8 +554,11 @@ static int gdb_set_spe_reg(CPUPPCState *env, uint8_t *= mem_buf, int n) return 0; } =20 -static int gdb_get_vsx_reg(CPUPPCState *env, GByteArray *buf, int n) +static int gdb_get_vsx_reg(CPUState *cs, GByteArray *buf, int n) { + PowerPCCPU *cpu =3D POWERPC_CPU(cs); + CPUPPCState *env =3D &cpu->env; + if (n < 32) { gdb_get_reg64(buf, *cpu_vsrl_ptr(env, n)); ppc_maybe_bswap_register(env, gdb_get_reg_ptr(buf, 8), 8); @@ -544,8 +567,11 @@ static int gdb_get_vsx_reg(CPUPPCState *env, GByteArra= y *buf, int n) return 0; } =20 -static int gdb_set_vsx_reg(CPUPPCState *env, uint8_t *mem_buf, int n) +static int gdb_set_vsx_reg(CPUState *cs, uint8_t *mem_buf, int n) { + PowerPCCPU *cpu =3D POWERPC_CPU(cs); + CPUPPCState *env =3D &cpu->env; + if (n < 32) { ppc_maybe_bswap_register(env, mem_buf, 8); *cpu_vsrl_ptr(env, n) =3D ldq_p(mem_buf); diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c index d4f9eb1516..c8525794ef 100644 --- a/target/riscv/gdbstub.c +++ b/target/riscv/gdbstub.c @@ -106,8 +106,11 @@ int riscv_cpu_gdb_write_register(CPUState *cs, uint8_t= *mem_buf, int n) return length; } =20 -static int riscv_gdb_get_fpu(CPURISCVState *env, GByteArray *buf, int n) +static int riscv_gdb_get_fpu(CPUState *cs, GByteArray *buf, int n) { + RISCVCPU *cpu =3D RISCV_CPU(cs); + CPURISCVState *env =3D &cpu->env; + if (n < 32) { if (env->misa_ext & RVD) { return gdb_get_reg64(buf, env->fpr[n]); @@ -119,8 +122,11 @@ static int riscv_gdb_get_fpu(CPURISCVState *env, GByte= Array *buf, int n) return 0; } =20 -static int riscv_gdb_set_fpu(CPURISCVState *env, uint8_t *mem_buf, int n) +static int riscv_gdb_set_fpu(CPUState *cs, uint8_t *mem_buf, int n) { + RISCVCPU *cpu =3D RISCV_CPU(cs); + CPURISCVState *env =3D &cpu->env; + if (n < 32) { env->fpr[n] =3D ldq_p(mem_buf); /* always 64-bit */ return sizeof(uint64_t); @@ -128,8 +134,10 @@ static int riscv_gdb_set_fpu(CPURISCVState *env, uint8= _t *mem_buf, int n) return 0; } =20 -static int riscv_gdb_get_vector(CPURISCVState *env, GByteArray *buf, int n) +static int riscv_gdb_get_vector(CPUState *cs, GByteArray *buf, int n) { + RISCVCPU *cpu =3D RISCV_CPU(cs); + CPURISCVState *env =3D &cpu->env; uint16_t vlenb =3D riscv_cpu_cfg(env)->vlen >> 3; if (n < 32) { int i; @@ -144,8 +152,10 @@ static int riscv_gdb_get_vector(CPURISCVState *env, GB= yteArray *buf, int n) return 0; } =20 -static int riscv_gdb_set_vector(CPURISCVState *env, uint8_t *mem_buf, int = n) +static int riscv_gdb_set_vector(CPUState *cs, uint8_t *mem_buf, int n) { + RISCVCPU *cpu =3D RISCV_CPU(cs); + CPURISCVState *env =3D &cpu->env; uint16_t vlenb =3D riscv_cpu_cfg(env)->vlen >> 3; if (n < 32) { int i; @@ -158,8 +168,11 @@ static int riscv_gdb_set_vector(CPURISCVState *env, ui= nt8_t *mem_buf, int n) return 0; } =20 -static int riscv_gdb_get_csr(CPURISCVState *env, GByteArray *buf, int n) +static int riscv_gdb_get_csr(CPUState *cs, GByteArray *buf, int n) { + RISCVCPU *cpu =3D RISCV_CPU(cs); + CPURISCVState *env =3D &cpu->env; + if (n < CSR_TABLE_SIZE) { target_ulong val =3D 0; int result; @@ -172,8 +185,11 @@ static int riscv_gdb_get_csr(CPURISCVState *env, GByte= Array *buf, int n) return 0; } =20 -static int riscv_gdb_set_csr(CPURISCVState *env, uint8_t *mem_buf, int n) +static int riscv_gdb_set_csr(CPUState *cs, uint8_t *mem_buf, int n) { + RISCVCPU *cpu =3D RISCV_CPU(cs); + CPURISCVState *env =3D &cpu->env; + if (n < CSR_TABLE_SIZE) { target_ulong val =3D ldtul_p(mem_buf); int result; @@ -186,25 +202,31 @@ static int riscv_gdb_set_csr(CPURISCVState *env, uint= 8_t *mem_buf, int n) return 0; } =20 -static int riscv_gdb_get_virtual(CPURISCVState *cs, GByteArray *buf, int n) +static int riscv_gdb_get_virtual(CPUState *cs, GByteArray *buf, int n) { if (n =3D=3D 0) { #ifdef CONFIG_USER_ONLY return gdb_get_regl(buf, 0); #else - return gdb_get_regl(buf, cs->priv); + RISCVCPU *cpu =3D RISCV_CPU(cs); + CPURISCVState *env =3D &cpu->env; + + return gdb_get_regl(buf, env->priv); #endif } return 0; } =20 -static int riscv_gdb_set_virtual(CPURISCVState *cs, uint8_t *mem_buf, int = n) +static int riscv_gdb_set_virtual(CPUState *cs, uint8_t *mem_buf, int n) { if (n =3D=3D 0) { #ifndef CONFIG_USER_ONLY - cs->priv =3D ldtul_p(mem_buf) & 0x3; - if (cs->priv =3D=3D PRV_RESERVED) { - cs->priv =3D PRV_S; + RISCVCPU *cpu =3D RISCV_CPU(cs); + CPURISCVState *env =3D &cpu->env; + + env->priv =3D ldtul_p(mem_buf) & 0x3; + if (env->priv =3D=3D PRV_RESERVED) { + env->priv =3D PRV_S; } #endif return sizeof(target_ulong); diff --git a/target/s390x/gdbstub.c b/target/s390x/gdbstub.c index 02c388dc32..c1e7c59b82 100644 --- a/target/s390x/gdbstub.c +++ b/target/s390x/gdbstub.c @@ -70,8 +70,11 @@ int s390_cpu_gdb_write_register(CPUState *cs, uint8_t *m= em_buf, int n) #define S390_A0_REGNUM 0 #define S390_A15_REGNUM 15 =20 -static int cpu_read_ac_reg(CPUS390XState *env, GByteArray *buf, int n) +static int cpu_read_ac_reg(CPUState *cs, GByteArray *buf, int n) { + S390CPU *cpu =3D S390_CPU(cs); + CPUS390XState *env =3D &cpu->env; + switch (n) { case S390_A0_REGNUM ... S390_A15_REGNUM: return gdb_get_reg32(buf, env->aregs[n]); @@ -80,8 +83,11 @@ static int cpu_read_ac_reg(CPUS390XState *env, GByteArra= y *buf, int n) } } =20 -static int cpu_write_ac_reg(CPUS390XState *env, uint8_t *mem_buf, int n) +static int cpu_write_ac_reg(CPUState *cs, uint8_t *mem_buf, int n) { + S390CPU *cpu =3D S390_CPU(cs); + CPUS390XState *env =3D &cpu->env; + switch (n) { case S390_A0_REGNUM ... S390_A15_REGNUM: env->aregs[n] =3D ldl_p(mem_buf); @@ -97,8 +103,11 @@ static int cpu_write_ac_reg(CPUS390XState *env, uint8_t= *mem_buf, int n) #define S390_F0_REGNUM 1 #define S390_F15_REGNUM 16 =20 -static int cpu_read_fp_reg(CPUS390XState *env, GByteArray *buf, int n) +static int cpu_read_fp_reg(CPUState *cs, GByteArray *buf, int n) { + S390CPU *cpu =3D S390_CPU(cs); + CPUS390XState *env =3D &cpu->env; + switch (n) { case S390_FPC_REGNUM: return gdb_get_reg32(buf, env->fpc); @@ -109,8 +118,11 @@ static int cpu_read_fp_reg(CPUS390XState *env, GByteAr= ray *buf, int n) } } =20 -static int cpu_write_fp_reg(CPUS390XState *env, uint8_t *mem_buf, int n) +static int cpu_write_fp_reg(CPUState *cs, uint8_t *mem_buf, int n) { + S390CPU *cpu =3D S390_CPU(cs); + CPUS390XState *env =3D &cpu->env; + switch (n) { case S390_FPC_REGNUM: env->fpc =3D ldl_p(mem_buf); @@ -129,8 +141,10 @@ static int cpu_write_fp_reg(CPUS390XState *env, uint8_= t *mem_buf, int n) #define S390_V16_REGNUM 16 #define S390_V31_REGNUM 31 =20 -static int cpu_read_vreg(CPUS390XState *env, GByteArray *buf, int n) +static int cpu_read_vreg(CPUState *cs, GByteArray *buf, int n) { + S390CPU *cpu =3D S390_CPU(cs); + CPUS390XState *env =3D &cpu->env; int ret; =20 switch (n) { @@ -148,8 +162,11 @@ static int cpu_read_vreg(CPUS390XState *env, GByteArra= y *buf, int n) return ret; } =20 -static int cpu_write_vreg(CPUS390XState *env, uint8_t *mem_buf, int n) +static int cpu_write_vreg(CPUState *cs, uint8_t *mem_buf, int n) { + S390CPU *cpu =3D S390_CPU(cs); + CPUS390XState *env =3D &cpu->env; + switch (n) { case S390_V0L_REGNUM ... S390_V15L_REGNUM: env->vregs[n][1] =3D ldtul_p(mem_buf + 8); @@ -168,8 +185,11 @@ static int cpu_write_vreg(CPUS390XState *env, uint8_t = *mem_buf, int n) #define S390_C15_REGNUM 15 =20 #ifndef CONFIG_USER_ONLY -static int cpu_read_c_reg(CPUS390XState *env, GByteArray *buf, int n) +static int cpu_read_c_reg(CPUState *cs, GByteArray *buf, int n) { + S390CPU *cpu =3D S390_CPU(cs); + CPUS390XState *env =3D &cpu->env; + switch (n) { case S390_C0_REGNUM ... S390_C15_REGNUM: return gdb_get_regl(buf, env->cregs[n]); @@ -178,8 +198,11 @@ static int cpu_read_c_reg(CPUS390XState *env, GByteArr= ay *buf, int n) } } =20 -static int cpu_write_c_reg(CPUS390XState *env, uint8_t *mem_buf, int n) +static int cpu_write_c_reg(CPUState *cs, uint8_t *mem_buf, int n) { + S390CPU *cpu =3D S390_CPU(cs); + CPUS390XState *env =3D &cpu->env; + switch (n) { case S390_C0_REGNUM ... S390_C15_REGNUM: env->cregs[n] =3D ldtul_p(mem_buf); @@ -199,8 +222,11 @@ static int cpu_write_c_reg(CPUS390XState *env, uint8_t= *mem_buf, int n) #define S390_VIRT_BEA_REGNUM 2 #define S390_VIRT_PREFIX_REGNUM 3 =20 -static int cpu_read_virt_reg(CPUS390XState *env, GByteArray *mem_buf, int = n) +static int cpu_read_virt_reg(CPUState *cs, GByteArray *mem_buf, int n) { + S390CPU *cpu =3D S390_CPU(cs); + CPUS390XState *env =3D &cpu->env; + switch (n) { case S390_VIRT_CKC_REGNUM: return gdb_get_regl(mem_buf, env->ckc); @@ -215,24 +241,27 @@ static int cpu_read_virt_reg(CPUS390XState *env, GByt= eArray *mem_buf, int n) } } =20 -static int cpu_write_virt_reg(CPUS390XState *env, uint8_t *mem_buf, int n) +static int cpu_write_virt_reg(CPUState *cs, uint8_t *mem_buf, int n) { + S390CPU *cpu =3D S390_CPU(cs); + CPUS390XState *env =3D &cpu->env; + switch (n) { case S390_VIRT_CKC_REGNUM: env->ckc =3D ldtul_p(mem_buf); - cpu_synchronize_post_init(env_cpu(env)); + cpu_synchronize_post_init(cs); return 8; case S390_VIRT_CPUTM_REGNUM: env->cputm =3D ldtul_p(mem_buf); - cpu_synchronize_post_init(env_cpu(env)); + cpu_synchronize_post_init(cs); return 8; case S390_VIRT_BEA_REGNUM: env->gbea =3D ldtul_p(mem_buf); - cpu_synchronize_post_init(env_cpu(env)); + cpu_synchronize_post_init(cs); return 8; case S390_VIRT_PREFIX_REGNUM: env->psa =3D ldtul_p(mem_buf); - cpu_synchronize_post_init(env_cpu(env)); + cpu_synchronize_post_init(cs); return 8; default: return 0; @@ -245,8 +274,11 @@ static int cpu_write_virt_reg(CPUS390XState *env, uint= 8_t *mem_buf, int n) #define S390_VIRT_KVM_PFS_REGNUM 2 #define S390_VIRT_KVM_PFC_REGNUM 3 =20 -static int cpu_read_virt_kvm_reg(CPUS390XState *env, GByteArray *mem_buf, = int n) +static int cpu_read_virt_kvm_reg(CPUState *cs, GByteArray *mem_buf, int n) { + S390CPU *cpu =3D S390_CPU(cs); + CPUS390XState *env =3D &cpu->env; + switch (n) { case S390_VIRT_KVM_PP_REGNUM: return gdb_get_regl(mem_buf, env->pp); @@ -261,8 +293,11 @@ static int cpu_read_virt_kvm_reg(CPUS390XState *env, G= ByteArray *mem_buf, int n) } } =20 -static int cpu_write_virt_kvm_reg(CPUS390XState *env, uint8_t *mem_buf, in= t n) +static int cpu_write_virt_kvm_reg(CPUState *cs, uint8_t *mem_buf, int n) { + S390CPU *cpu =3D S390_CPU(cs); + CPUS390XState *env =3D &cpu->env; + switch (n) { case S390_VIRT_KVM_PP_REGNUM: env->pp =3D ldtul_p(mem_buf); @@ -292,13 +327,19 @@ static int cpu_write_virt_kvm_reg(CPUS390XState *env,= uint8_t *mem_buf, int n) #define S390_GS_GSSM_REGNUM 2 #define S390_GS_GSEPLA_REGNUM 3 =20 -static int cpu_read_gs_reg(CPUS390XState *env, GByteArray *buf, int n) +static int cpu_read_gs_reg(CPUState *cs, GByteArray *buf, int n) { + S390CPU *cpu =3D S390_CPU(cs); + CPUS390XState *env =3D &cpu->env; + return gdb_get_regl(buf, env->gscb[n]); } =20 -static int cpu_write_gs_reg(CPUS390XState *env, uint8_t *mem_buf, int n) +static int cpu_write_gs_reg(CPUState *cs, uint8_t *mem_buf, int n) { + S390CPU *cpu =3D S390_CPU(cs); + CPUS390XState *env =3D &cpu->env; + env->gscb[n] =3D ldtul_p(mem_buf); cpu_synchronize_post_init(env_cpu(env)); return 8; --=20 2.42.0