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([71.212.131.115]) by smtp.gmail.com with ESMTPSA id j26-20020aa783da000000b00687a4b70d1esm3577320pfn.218.2023.09.15.20.30.34 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Sep 2023 20:30:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1694835035; x=1695439835; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=AjeCPzUocYg1JKJ2KMopCouMlpFmZ9U4rN+3dpEuC9M=; b=p2XFWhNF5d9hTo1GLfKMzamaAYkXdtSSftYuXsYjknx864R7owLG6o/NVukAPnnUnR yqW1nAPSXNba+w+vMa8O42RcQA7tnDVCaSL/I5D5DGWAbJYkfUDNLDp1vZARzLvQbFPb ARSbHJjRIvGnq5XxscF0rLaIpDHK+UdHiSxJBnOjsycnkDnq/PIdIyETKMluIvyc4oQz pWL42/hOncJhF64nvjchRX7GI3vyMCdz1tp8mqAd9v6/ZxMKOZbXjodoatWKGPRM39j6 Ua2boXbEUX5/clz+26c92eCJGQPOTIgLaF8+nvMM9yrvZACGvKci/njarKP62FULAMV7 sSNQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1694835035; x=1695439835; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=AjeCPzUocYg1JKJ2KMopCouMlpFmZ9U4rN+3dpEuC9M=; b=W3bHUslMe25IT/W5IJSKxGYYMCPqu9yw0vODuIX8iO1ZwkWor2t2FBTMFKiu9j4fHQ 5GVinBJ39b3PBGsxQM97Irc8uABwqxS+MnXKIuEUAR6aIaaoROchWaP0nXO2CRgm3X4q yIGduchzCEyN+XHo+iTly56NsSSig4XGa9uFNIeAOVpCqHuWida0aG2olK3Wwc5ulKjf 4X0/4nlqzhZCjXrFF34P4JtGJkFtKMpsO+zl/snasGQNrV98v31maFpOthc1OhxOsk8o LERVLqjq2xhomHLrDTOjwLvIzMynBDWDL+ji1yy5VS5N1/quUCmu85pKeM3uOhBrjpcB c6qA== X-Gm-Message-State: AOJu0Yz7vbCqWWPWQKU0QuKFjSkBpRdG1SliJjEffiOuNdJf9NnyvF0Z RIqe+o6tdI4dMndelWNQAt+09/Fqe/cTyqsdWPw= X-Google-Smtp-Source: AGHT+IF9n4aWbpIiAeL6BYYfuqQNi0ewg1q6Uxy86Gb9pjF2hocSGLavS0/P3ywiNNuNKINUKNExLw== X-Received: by 2002:a05:6a21:7888:b0:153:56b1:8417 with SMTP id bf8-20020a056a21788800b0015356b18417mr4579835pzc.21.1694835035379; Fri, 15 Sep 2023 20:30:35 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 24/39] accel/tcg: Simplify tlb_plugin_lookup Date: Fri, 15 Sep 2023 20:29:56 -0700 Message-Id: <20230916033011.479144-25-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230916033011.479144-1-richard.henderson@linaro.org> References: <20230916033011.479144-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::430; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1694835092750100020 Content-Type: text/plain; charset="utf-8" Now that we defer address space update and tlb_flush until the next async_run_on_cpu, the plugin run at the end of the instruction no longer has to contend with a flushed tlb. Therefore, delete SavedIOTLB entirely. Properly return false from tlb_plugin_lookup when we do not have a tlb match. Fixes a bug in which SavedIOTLB had stale data, because there were multiple i/o accesses within a single insn. Signed-off-by: Richard Henderson --- include/hw/core/cpu.h | 13 ------- include/qemu/typedefs.h | 1 - accel/tcg/cputlb.c | 79 ++++++++++++----------------------------- 3 files changed, 23 insertions(+), 70 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 92a4234439..648b5b3586 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -227,17 +227,6 @@ struct CPUWatchpoint { QTAILQ_ENTRY(CPUWatchpoint) entry; }; =20 -#ifdef CONFIG_PLUGIN -/* - * For plugins we sometime need to save the resolved iotlb data before - * the memory regions get moved around by io_writex. - */ -typedef struct SavedIOTLB { - MemoryRegionSection *section; - hwaddr mr_offset; -} SavedIOTLB; -#endif - struct KVMState; struct kvm_run; =20 @@ -409,8 +398,6 @@ struct CPUState { =20 #ifdef CONFIG_PLUGIN GArray *plugin_mem_cbs; - /* saved iotlb data from io_writex */ - SavedIOTLB saved_iotlb; #endif =20 /* TODO Move common fields from CPUArchState here. */ diff --git a/include/qemu/typedefs.h b/include/qemu/typedefs.h index 834b0e47a0..5abdbc3874 100644 --- a/include/qemu/typedefs.h +++ b/include/qemu/typedefs.h @@ -129,7 +129,6 @@ typedef struct QString QString; typedef struct RAMBlock RAMBlock; typedef struct Range Range; typedef struct ReservedRegion ReservedRegion; -typedef struct SavedIOTLB SavedIOTLB; typedef struct SHPCDevice SHPCDevice; typedef struct SSIBus SSIBus; typedef struct TCGHelperInfo TCGHelperInfo; diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 03e27b2a38..9cbcd202d2 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1367,21 +1367,6 @@ static inline void cpu_transaction_failed(CPUState *= cpu, hwaddr physaddr, } } =20 -/* - * Save a potentially trashed CPUTLBEntryFull for later lookup by plugin. - * This is read by tlb_plugin_lookup if the fulltlb entry doesn't match - * because of the side effect of io_writex changing memory layout. - */ -static void save_iotlb_data(CPUState *cs, MemoryRegionSection *section, - hwaddr mr_offset) -{ -#ifdef CONFIG_PLUGIN - SavedIOTLB *saved =3D &cs->saved_iotlb; - saved->section =3D section; - saved->mr_offset =3D mr_offset; -#endif -} - static uint64_t io_readx(CPUArchState *env, CPUTLBEntryFull *full, int mmu_idx, vaddr addr, uintptr_t retaddr, MMUAccessType access_type, MemOp op) @@ -1401,12 +1386,6 @@ static uint64_t io_readx(CPUArchState *env, CPUTLBEn= tryFull *full, cpu_io_recompile(cpu, retaddr); } =20 - /* - * The memory_region_dispatch may trigger a flush/resize - * so for plugins we save the iotlb_data just in case. - */ - save_iotlb_data(cpu, section, mr_offset); - { QEMU_IOTHREAD_LOCK_GUARD(); r =3D memory_region_dispatch_read(mr, mr_offset, &val, op, full->a= ttrs); @@ -1441,12 +1420,6 @@ static void io_writex(CPUArchState *env, CPUTLBEntry= Full *full, } cpu->mem_io_pc =3D retaddr; =20 - /* - * The memory_region_dispatch may trigger a flush/resize - * so for plugins we save the iotlb_data just in case. - */ - save_iotlb_data(cpu, section, mr_offset); - { QEMU_IOTHREAD_LOCK_GUARD(); r =3D memory_region_dispatch_write(mr, mr_offset, val, op, full->a= ttrs); @@ -1729,45 +1702,39 @@ tb_page_addr_t get_page_addr_code_hostp(CPUArchStat= e *env, vaddr addr, * in the softmmu lookup code (or helper). We don't handle re-fills or * checking the victim table. This is purely informational. * - * This almost never fails as the memory access being instrumented - * should have just filled the TLB. The one corner case is io_writex - * which can cause TLB flushes and potential resizing of the TLBs - * losing the information we need. In those cases we need to recover - * data from a copy of the CPUTLBEntryFull. As long as this always occurs - * from the same thread (which a mem callback will be) this is safe. + * The one corner case is i/o write, which can cause changes to the + * address space. Those changes, and the corresponding tlb flush, + * should be delayed until the next TB, so even then this ought not fail. + * But check, Just in Case. */ - bool tlb_plugin_lookup(CPUState *cpu, vaddr addr, int mmu_idx, bool is_store, struct qemu_plugin_hwaddr *data) { CPUArchState *env =3D cpu->env_ptr; CPUTLBEntry *tlbe =3D tlb_entry(env, mmu_idx, addr); uintptr_t index =3D tlb_index(env, mmu_idx, addr); - uint64_t tlb_addr =3D is_store ? tlb_addr_write(tlbe) : tlbe->addr_rea= d; + MMUAccessType access_type =3D is_store ? MMU_DATA_STORE : MMU_DATA_LOA= D; + uint64_t tlb_addr =3D tlb_read_idx(tlbe, access_type); =20 - if (likely(tlb_hit(tlb_addr, addr))) { - /* We must have an iotlb entry for MMIO */ - if (tlb_addr & TLB_MMIO) { - CPUTLBEntryFull *full; - full =3D &env_tlb(env)->d[mmu_idx].fulltlb[index]; - data->is_io =3D true; - data->v.io.section =3D - iotlb_to_section(cpu, full->xlat_section, full->attrs); - data->v.io.offset =3D (full->xlat_section & TARGET_PAGE_MASK) = + addr; - } else { - data->is_io =3D false; - data->v.ram.hostaddr =3D (void *)((uintptr_t)addr + tlbe->adde= nd); - } - return true; - } else { - SavedIOTLB *saved =3D &cpu->saved_iotlb; - data->is_io =3D true; - data->v.io.section =3D saved->section; - data->v.io.offset =3D saved->mr_offset; - return true; + if (unlikely(!tlb_hit(tlb_addr, addr))) { + return false; } -} =20 + /* We must have an iotlb entry for MMIO */ + if (tlb_addr & TLB_MMIO) { + CPUTLBEntryFull *full =3D &env_tlb(env)->d[mmu_idx].fulltlb[index]; + hwaddr xlat =3D full->xlat_section; + + data->is_io =3D true; + data->v.io.offset =3D (xlat & TARGET_PAGE_MASK) + addr; + data->v.io.section =3D + iotlb_to_section(cpu, xlat & ~TARGET_PAGE_MASK, full->attrs); + } else { + data->is_io =3D false; + data->v.ram.hostaddr =3D (void *)((uintptr_t)addr + tlbe->addend); + } + return true; +} #endif =20 /* --=20 2.34.1