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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::729; envelope-from=richard.henderson@linaro.org; helo=mail-qk1-x729.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1694835329340100003 Content-Type: text/plain; charset="utf-8" From: Jiajie Chen Signed-off-by: Jiajie Chen Reviewed-by: Richard Henderson Message-Id: <20230908022302.180442-5-c@jia.je> Signed-off-by: Richard Henderson --- tcg/loongarch64/tcg-target-con-set.h | 1 + tcg/loongarch64/tcg-target-con-str.h | 1 + tcg/loongarch64/tcg-target.c.inc | 65 ++++++++++++++++++++++++++++ 3 files changed, 67 insertions(+) diff --git a/tcg/loongarch64/tcg-target-con-set.h b/tcg/loongarch64/tcg-tar= get-con-set.h index 37b3f80bf9..8c8ea5d919 100644 --- a/tcg/loongarch64/tcg-target-con-set.h +++ b/tcg/loongarch64/tcg-target-con-set.h @@ -31,4 +31,5 @@ C_O1_I2(r, 0, rZ) C_O1_I2(r, rZ, ri) C_O1_I2(r, rZ, rJ) C_O1_I2(r, rZ, rZ) +C_O1_I2(w, w, wM) C_O1_I4(r, rZ, rJ, rZ, rZ) diff --git a/tcg/loongarch64/tcg-target-con-str.h b/tcg/loongarch64/tcg-tar= get-con-str.h index 81b8d40278..a8a1c44014 100644 --- a/tcg/loongarch64/tcg-target-con-str.h +++ b/tcg/loongarch64/tcg-target-con-str.h @@ -26,3 +26,4 @@ CONST('U', TCG_CT_CONST_U12) CONST('Z', TCG_CT_CONST_ZERO) CONST('C', TCG_CT_CONST_C12) CONST('W', TCG_CT_CONST_WSZ) +CONST('M', TCG_CT_CONST_VCMP) diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.= c.inc index 07a0326e5d..129dd92910 100644 --- a/tcg/loongarch64/tcg-target.c.inc +++ b/tcg/loongarch64/tcg-target.c.inc @@ -176,6 +176,7 @@ static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKin= d kind, int slot) #define TCG_CT_CONST_U12 0x800 #define TCG_CT_CONST_C12 0x1000 #define TCG_CT_CONST_WSZ 0x2000 +#define TCG_CT_CONST_VCMP 0x4000 =20 #define ALL_GENERAL_REGS MAKE_64BIT_MASK(0, 32) #define ALL_VECTOR_REGS MAKE_64BIT_MASK(32, 32) @@ -209,6 +210,10 @@ static bool tcg_target_const_match(int64_t val, TCGTyp= e type, int ct, int vece) if ((ct & TCG_CT_CONST_WSZ) && val =3D=3D (type =3D=3D TCG_TYPE_I32 ? = 32 : 64)) { return true; } + int64_t vec_val =3D sextract64(val, 0, 8 << vece); + if ((ct & TCG_CT_CONST_VCMP) && -0x10 <=3D vec_val && vec_val <=3D 0x1= f) { + return true; + } return false; } =20 @@ -1624,6 +1629,23 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode = opc, TCGType type =3D vecl + TCG_TYPE_V64; TCGArg a0, a1, a2; TCGReg temp =3D TCG_REG_TMP0; + TCGReg temp_vec =3D TCG_VEC_TMP0; + + static const LoongArchInsn cmp_vec_insn[16][4] =3D { + [TCG_COND_EQ] =3D {OPC_VSEQ_B, OPC_VSEQ_H, OPC_VSEQ_W, OPC_VSEQ_D}, + [TCG_COND_LE] =3D {OPC_VSLE_B, OPC_VSLE_H, OPC_VSLE_W, OPC_VSLE_D}, + [TCG_COND_LEU] =3D {OPC_VSLE_BU, OPC_VSLE_HU, OPC_VSLE_WU, OPC_VSL= E_DU}, + [TCG_COND_LT] =3D {OPC_VSLT_B, OPC_VSLT_H, OPC_VSLT_W, OPC_VSLT_D}, + [TCG_COND_LTU] =3D {OPC_VSLT_BU, OPC_VSLT_HU, OPC_VSLT_WU, OPC_VSL= T_DU}, + }; + static const LoongArchInsn cmp_vec_imm_insn[16][4] =3D { + [TCG_COND_EQ] =3D {OPC_VSEQI_B, OPC_VSEQI_H, OPC_VSEQI_W, OPC_VSEQ= I_D}, + [TCG_COND_LE] =3D {OPC_VSLEI_B, OPC_VSLEI_H, OPC_VSLEI_W, OPC_VSLE= I_D}, + [TCG_COND_LEU] =3D {OPC_VSLEI_BU, OPC_VSLEI_HU, OPC_VSLEI_WU, OPC_= VSLEI_DU}, + [TCG_COND_LT] =3D {OPC_VSLTI_B, OPC_VSLTI_H, OPC_VSLTI_W, OPC_VSLT= I_D}, + [TCG_COND_LTU] =3D {OPC_VSLTI_BU, OPC_VSLTI_HU, OPC_VSLTI_WU, OPC_= VSLTI_DU}, + }; + LoongArchInsn insn; =20 a0 =3D args[0]; a1 =3D args[1]; @@ -1651,6 +1673,45 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode = opc, tcg_out_opc_vldx(s, a0, a1, temp); } break; + case INDEX_op_cmp_vec: + TCGCond cond =3D args[3]; + if (const_args[2]) { + /* + * cmp_vec dest, src, value + * Try vseqi/vslei/vslti + */ + int64_t value =3D sextract64(a2, 0, 8 << vece); + if ((cond =3D=3D TCG_COND_EQ || cond =3D=3D TCG_COND_LE || \ + cond =3D=3D TCG_COND_LT) && (-0x10 <=3D value && value <= =3D 0x0f)) { + tcg_out32(s, encode_vdvjsk5_insn(cmp_vec_imm_insn[cond][ve= ce], \ + a0, a1, value)); + break; + } else if ((cond =3D=3D TCG_COND_LEU || cond =3D=3D TCG_COND_L= TU) && + (0x00 <=3D value && value <=3D 0x1f)) { + tcg_out32(s, encode_vdvjuk5_insn(cmp_vec_imm_insn[cond][ve= ce], \ + a0, a1, value)); + break; + } + + /* + * Fallback to: + * dupi_vec temp, a2 + * cmp_vec a0, a1, temp, cond + */ + tcg_out_dupi_vec(s, type, vece, temp_vec, a2); + a2 =3D temp_vec; + } + + insn =3D cmp_vec_insn[cond][vece]; + if (insn =3D=3D 0) { + TCGArg t; + t =3D a1, a1 =3D a2, a2 =3D t; + cond =3D tcg_swap_cond(cond); + insn =3D cmp_vec_insn[cond][vece]; + tcg_debug_assert(insn !=3D 0); + } + tcg_out32(s, encode_vdvjvk_insn(insn, a0, a1, a2)); + break; case INDEX_op_dupm_vec: tcg_out_dupm_vec(s, type, vece, a0, a1, a2); break; @@ -1666,6 +1727,7 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, = unsigned vece) case INDEX_op_st_vec: case INDEX_op_dup_vec: case INDEX_op_dupm_vec: + case INDEX_op_cmp_vec: return 1; default: return 0; @@ -1827,6 +1889,9 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpc= ode op) case INDEX_op_st_vec: return C_O0_I2(w, r); =20 + case INDEX_op_cmp_vec: + return C_O1_I2(w, w, wM); + default: g_assert_not_reached(); } --=20 2.34.1