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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id n12-20020a05600c294c00b003fee777fd84sm5298849wmd.41.2023.09.15.11.54.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Sep 2023 11:54:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1694804096; x=1695408896; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=5R4zE8heAJ76w0EEJu7tUdeCBxBgPEWGUttS6DVMkwI=; b=Mmgi9dlDmv1kCXf8gRsc1UKFuFj4aStPWiM9Q6vGM90WDi2kuwLs4CyTTft9hCXqyX 3tI0ez9LQPUE9iA+0b7S/82kKXCB6AmVgAX/Nmxig2iYTbcNQubGO3F0sXNgDfYbQs89 cIhlOktDH3qWczbRZuZ0jw6wpfLncWnmCOikeCFYmVOULsADHiwuwtMLcOZcO68uViB2 c9X/LkQdRzajhYD+ynphesAoLQVTViMOyjpJFK6aIXiC4+Sp3s0qCOvwFrtszhkI1SoX ibKMLSuxHq55+u5z8FIYbmb3xT+UWe9dXzcx/OpzIWAlqadxVkIMiwy5Sw9rcsJKAZd/ i/nw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1694804096; x=1695408896; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=5R4zE8heAJ76w0EEJu7tUdeCBxBgPEWGUttS6DVMkwI=; b=wv8QM6MjrUfMXySYxdNB+C0EEEwR+C6xu42HiCFgu8kcKEOo+0DPzwRZuePSe6hyZW QcSk3QIRQqkHAMZKeSeec/aARXmOT0luSkwZWrkwZZ1zty1plEnhrgUfSbsKSg9J5LqF LECzYIn2YfpdrsIZZ0Rsam95Omiw9OykHCf0eTAmjxOik/LomQPqZxwSm7NQwu+1g0dd KkvIReCEKGb45UjMdcmVSDTaeSnK67v147oJzrBXkbpRD89O48ch4w2khLOg/mRB7pqu 0OuCiQbciudgKvDT+947qMsu1wabW9GBbV4ecXI9QfDW/I9APC2OnNBbjX8/AhvvGKcd aKXQ== X-Gm-Message-State: AOJu0Ywa9zfwnJaaW9sSrt6AgGRCd1aQ/KSICcFnvlH3SwzoGbYw66zK q5JT5drpmIesHQH1krhn2yXPpw== X-Google-Smtp-Source: AGHT+IFZltuStAIOIcZc/6GiDiMlAY7c6kRm5z4cRWXROiEWMkr8GlXvZJyDIt9n+tgjFw0Nsrkwlw== X-Received: by 2002:a7b:c4c8:0:b0:3fe:16c8:65fa with SMTP id g8-20020a7bc4c8000000b003fe16c865famr2119414wmk.4.1694804096451; Fri, 15 Sep 2023 11:54:56 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Marcin Juszkiewicz , Leif Lindholm , Radoslaw Biernacki Subject: [PATCH 2/2] target/arm: Implement Neoverse N2 CPU model Date: Fri, 15 Sep 2023 19:54:53 +0100 Message-Id: <20230915185453.1871167-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230915185453.1871167-1-peter.maydell@linaro.org> References: <20230915185453.1871167-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1694804182693100007 Content-Type: text/plain; charset="utf-8" Implement a model of the Neoverse N2 CPU. This is an Armv9.0-A processor very similar to the Cortex-A710. The differences are: * no FEAT_EVT * FEAT_DGH (data gathering hint) * FEAT_NV (not yet implemented in QEMU) * Statistical Profiling Extension (not implemented in QEMU) * 48 bit physical address range, not 40 * CTR_EL0.DIC =3D 1 (no explicit icache cleaning needed) * PMCR_EL0.N =3D 6 (always 6 PMU counters, not 20) Because it has 48-bit physical address support, we can use this CPU in the sbsa-ref board as well as the virt board. Signed-off-by: Peter Maydell Reviewed-by: Alex Benn=C3=A9e --- docs/system/arm/virt.rst | 1 + hw/arm/sbsa-ref.c | 1 + hw/arm/virt.c | 1 + target/arm/tcg/cpu64.c | 103 +++++++++++++++++++++++++++++++++++++++ 4 files changed, 106 insertions(+) diff --git a/docs/system/arm/virt.rst b/docs/system/arm/virt.rst index e1697ac8f48..7c4c80180c6 100644 --- a/docs/system/arm/virt.rst +++ b/docs/system/arm/virt.rst @@ -63,6 +63,7 @@ Supported guest CPU types: - ``host`` (with KVM only) - ``neoverse-n1`` (64-bit) - ``neoverse-v1`` (64-bit) +- ``neoverse-n2`` (64-bit) - ``max`` (same as ``host`` for KVM; best possible emulation with TCG) =20 Note that the default is ``cortex-a15``, so for an AArch64 guest you must diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c index bc89eb48062..4db287287e1 100644 --- a/hw/arm/sbsa-ref.c +++ b/hw/arm/sbsa-ref.c @@ -154,6 +154,7 @@ static const char * const valid_cpus[] =3D { ARM_CPU_TYPE_NAME("cortex-a72"), ARM_CPU_TYPE_NAME("neoverse-n1"), ARM_CPU_TYPE_NAME("neoverse-v1"), + ARM_CPU_TYPE_NAME("neoverse-n2"), ARM_CPU_TYPE_NAME("max"), }; =20 diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 8ad78b23c24..42253462735 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -215,6 +215,7 @@ static const char *valid_cpus[] =3D { ARM_CPU_TYPE_NAME("a64fx"), ARM_CPU_TYPE_NAME("neoverse-n1"), ARM_CPU_TYPE_NAME("neoverse-v1"), + ARM_CPU_TYPE_NAME("neoverse-n2"), #endif ARM_CPU_TYPE_NAME("cortex-a53"), ARM_CPU_TYPE_NAME("cortex-a57"), diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index ea43cf3c1ee..370cc82f0ef 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -963,6 +963,108 @@ static void aarch64_a710_initfn(Object *obj) aarch64_add_sve_properties(obj); } =20 +/* Extra IMPDEF regs in the N2 beyond those in the A710 */ +static const ARMCPRegInfo neoverse_n2_cp_reginfo[] =3D { + { .name =3D "CPURNDBR_EL3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 6, .crn =3D 15, .crm =3D 3, .opc2 =3D 0, + .access =3D PL3_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "CPURNDPEID_EL3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 6, .crn =3D 15, .crm =3D 3, .opc2 =3D 1, + .access =3D PL3_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, +}; + +static void aarch64_neoverse_n2_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + + cpu->dtb_compatible =3D "arm,neoverse-n2"; + set_feature(&cpu->env, ARM_FEATURE_V8); + set_feature(&cpu->env, ARM_FEATURE_NEON); + set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); + set_feature(&cpu->env, ARM_FEATURE_AARCH64); + set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); + set_feature(&cpu->env, ARM_FEATURE_EL2); + set_feature(&cpu->env, ARM_FEATURE_EL3); + set_feature(&cpu->env, ARM_FEATURE_PMU); + + /* Ordered by Section B.5: AArch64 ID registers */ + cpu->midr =3D 0x410FD493; /* r0p3 */ + cpu->revidr =3D 0; + cpu->isar.id_pfr0 =3D 0x21110131; + cpu->isar.id_pfr1 =3D 0x00010000; /* GIC filled in later */ + cpu->isar.id_dfr0 =3D 0x16011099; + cpu->id_afr0 =3D 0; + cpu->isar.id_mmfr0 =3D 0x10201105; + cpu->isar.id_mmfr1 =3D 0x40000000; + cpu->isar.id_mmfr2 =3D 0x01260000; + cpu->isar.id_mmfr3 =3D 0x02122211; + cpu->isar.id_isar0 =3D 0x02101110; + cpu->isar.id_isar1 =3D 0x13112111; + cpu->isar.id_isar2 =3D 0x21232042; + cpu->isar.id_isar3 =3D 0x01112131; + cpu->isar.id_isar4 =3D 0x00010142; + cpu->isar.id_isar5 =3D 0x11011121; /* with Crypto */ + cpu->isar.id_mmfr4 =3D 0x01021110; + cpu->isar.id_isar6 =3D 0x01111111; + cpu->isar.mvfr0 =3D 0x10110222; + cpu->isar.mvfr1 =3D 0x13211111; + cpu->isar.mvfr2 =3D 0x00000043; + cpu->isar.id_pfr2 =3D 0x00000011; + cpu->isar.id_aa64pfr0 =3D 0x1201111120111112ull; /* GIC filled in lat= er */ + cpu->isar.id_aa64pfr1 =3D 0x0000000000000221ull; + cpu->isar.id_aa64zfr0 =3D 0x0000110100110021ull; /* with Crypto */ + cpu->isar.id_aa64dfr0 =3D 0x000011f210305619ull; + cpu->isar.id_aa64dfr1 =3D 0; + cpu->id_aa64afr0 =3D 0; + cpu->id_aa64afr1 =3D 0; + cpu->isar.id_aa64isar0 =3D 0x0221111110212120ull; /* with Crypto */ + cpu->isar.id_aa64isar1 =3D 0x0011111101211052ull; + cpu->isar.id_aa64mmfr0 =3D 0x0000022200101125ull; + cpu->isar.id_aa64mmfr1 =3D 0x0000000010212122ull; + cpu->isar.id_aa64mmfr2 =3D 0x1221011112101011ull; + cpu->clidr =3D 0x0000001482000023ull; + cpu->gm_blocksize =3D 4; + cpu->ctr =3D 0x00000004b444c004ull; + cpu->dcz_blocksize =3D 4; + /* TODO FEAT_MPAM: mpamidr_el1 =3D 0x0000_0001_001e_01ff */ + + /* Section B.7.2: PMCR_EL0 */ + cpu->isar.reset_pmcr_el0 =3D 0x3000; /* with 6 counters */ + + /* Section B.8.9: ICH_VTR_EL2 */ + cpu->gic_num_lrs =3D 4; + cpu->gic_vpribits =3D 5; + cpu->gic_vprebits =3D 5; + cpu->gic_pribits =3D 5; + + /* Section 14: Scalable Vector Extensions support */ + cpu->sve_vq.supported =3D 1 << 0; /* 128bit */ + + /* + * The Neoverse N2 TRM does not list CCSIDR values. The layout of + * the caches are in text in Table 7-1, Table 8-1, and Table 9-1. + * + * L1: 4-way set associative 64-byte line size, total 64K. + * L2: 8-way set associative 64 byte line size, total either 512K or 1= 024K. + */ + cpu->ccsidr[0] =3D make_ccsidr64(4, 64, 64 * KiB); /* L1 dcache */ + cpu->ccsidr[1] =3D cpu->ccsidr[0]; /* L1 icache */ + cpu->ccsidr[2] =3D make_ccsidr64(8, 64, 512 * KiB); /* L2 cache */ + + /* FIXME: Not documented -- copied from neoverse-v1 */ + cpu->reset_sctlr =3D 0x30c50838; + + /* + * The Neoverse N2 has all of the Cortex-A710 IMPDEF registers, + * and a few more RNG related ones. + */ + define_arm_cp_regs(cpu, cortex_a710_cp_reginfo); + define_arm_cp_regs(cpu, neoverse_n2_cp_reginfo); + + aarch64_add_pauth_properties(obj); + aarch64_add_sve_properties(obj); +} + /* * -cpu max: a CPU with as many features enabled as our emulation supports. * The version of '-cpu max' for qemu-system-arm is defined in cpu32.c; @@ -1159,6 +1261,7 @@ static const ARMCPUInfo aarch64_cpus[] =3D { { .name =3D "a64fx", .initfn =3D aarch64_a64fx_initfn }, { .name =3D "neoverse-n1", .initfn =3D aarch64_neoverse_n1_init= fn }, { .name =3D "neoverse-v1", .initfn =3D aarch64_neoverse_v1_init= fn }, + { .name =3D "neoverse-n2", .initfn =3D aarch64_neoverse_n2_init= fn }, }; =20 static void aarch64_cpu_register_types(void) --=20 2.34.1