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bh=shNcLssPydexJR/HgqX7dcXWSdVE/iwCA8mFVcwq2H0=; b=gOaKYk38AsnURBhwA6pEshzNUnmvEwow383jRLuoHmBeleS7YgVez1vqdD+c9cevdUNB nYj5RjthZSQuiWfUAxBc//gNWdGHrrQcpi+V330SjmAd0ZWWHJcK/IJ0wzWin96ytcA5 856M5iYmm0l+sV4hqzWqZ5ha1kmBdLkOSgOnUZI5EQiddtci5OR4NxnGWEHLWEkfOHe3 oAab7mcWt2SLMhgVsggLMGniCzu4p7b5oXnO8oVYHTsBf+He/RTUlDNlUrVieelv4Vhs pFMWdkWYtfb19q9UVc8dZaO/pe1C7zOL0aA30GXa/f9BlrNuwDT9pYw/xgsLmE0M1wxj yw== From: Leif Lindholm To: CC: , Radoslaw Biernacki , Peter Maydell , Marcin Juszkiewicz , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v1 1/3] {include/}hw/arm: refactor virt PPI logic Date: Fri, 15 Sep 2023 12:55:33 +0100 Message-ID: <20230915115535.129834-2-quic_llindhol@quicinc.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20230915115535.129834-1-quic_llindhol@quicinc.com> References: <20230915115535.129834-1-quic_llindhol@quicinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: DHkBfPXwvTpeGVOCGvIgbPGdkiru9W3N X-Proofpoint-ORIG-GUID: DHkBfPXwvTpeGVOCGvIgbPGdkiru9W3N X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.980,Hydra:6.0.601,FMLib:17.11.176.26 definitions=2023-09-15_08,2023-09-14_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 priorityscore=1501 malwarescore=0 phishscore=0 spamscore=0 impostorscore=0 lowpriorityscore=0 bulkscore=0 clxscore=1015 mlxscore=0 mlxlogscore=356 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2308100000 definitions=main-2309150106 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=quic_llindhol@quicinc.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @quicinc.com) X-ZM-MESSAGEID: 1694779013684100001 Content-Type: text/plain; charset="utf-8" GIC Private Peripheral Interrupts (PPI) are defined as GIC INTID 16-31. As in, PPI0 is INTID16 .. PPI15 is INTID31. Arm's Base System Architecture specification (BSA) lists the mandated and recommended private interrupt IDs by INTID, not by PPI index. But current definitions in virt define them by PPI index, complicating cross referencing. Meanwhile, the PPI(x) macro counterintuitively adds 16 to the input value, converting a PPI index to an INTID. Resolve this by redefining the BSA-allocated PPIs by their INTIDs, inverting the logic of the PPI(x) macro and flipping where it is used. Signed-off-by: Leif Lindholm Reviewed-by: Marcin Juszkiewicz Tested-by: Marcin Juszkiewicz --- hw/arm/virt-acpi-build.c | 4 ++-- hw/arm/virt.c | 9 +++++---- include/hw/arm/virt.h | 14 +++++++------- 3 files changed, 14 insertions(+), 13 deletions(-) diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index 6b674231c2..963c58a88a 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -729,9 +729,9 @@ build_madt(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) for (i =3D 0; i < MACHINE(vms)->smp.cpus; i++) { ARMCPU *armcpu =3D ARM_CPU(qemu_get_cpu(i)); uint64_t physical_base_address =3D 0, gich =3D 0, gicv =3D 0; - uint32_t vgic_interrupt =3D vms->virt ? PPI(ARCH_GIC_MAINT_IRQ) : = 0; + uint32_t vgic_interrupt =3D vms->virt ? ARCH_GIC_MAINT_IRQ : 0; uint32_t pmu_interrupt =3D arm_feature(&armcpu->env, ARM_FEATURE_P= MU) ? - PPI(VIRTUAL_PMU_IRQ) : 0; + VIRTUAL_PMU_IRQ : 0; =20 if (vms->gic_version =3D=3D VIRT_GIC_VERSION_2) { physical_base_address =3D memmap[VIRT_GIC_CPU].base; diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 8ad78b23c2..bb70f3eec8 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -815,23 +815,24 @@ static void create_gic(VirtMachineState *vms, MemoryR= egion *mem) for (irq =3D 0; irq < ARRAY_SIZE(timer_irq); irq++) { qdev_connect_gpio_out(cpudev, irq, qdev_get_gpio_in(vms->gic, - ppibase + timer_irq[irq= ])); + ppibase + + PPI(timer_irq[irq]))); } =20 if (vms->gic_version !=3D VIRT_GIC_VERSION_2) { qemu_irq irq =3D qdev_get_gpio_in(vms->gic, - ppibase + ARCH_GIC_MAINT_IRQ); + ppibase + PPI(ARCH_GIC_MAINT_I= RQ)); qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interru= pt", 0, irq); } else if (vms->virt) { qemu_irq irq =3D qdev_get_gpio_in(vms->gic, - ppibase + ARCH_GIC_MAINT_IRQ); + ppibase + PPI(ARCH_GIC_MAINT_I= RQ)); sysbus_connect_irq(gicbusdev, i + 4 * smp_cpus, irq); } =20 qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0, qdev_get_gpio_in(vms->gic, ppibase - + VIRTUAL_PMU_IRQ)); + + PPI(VIRTUAL_PMU_IRQ= ))); =20 sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_= IRQ)); sysbus_connect_irq(gicbusdev, i + smp_cpus, diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h index e1ddbea96b..8ba4e5b836 100644 --- a/include/hw/arm/virt.h +++ b/include/hw/arm/virt.h @@ -43,16 +43,16 @@ #define NUM_VIRTIO_TRANSPORTS 32 #define NUM_SMMU_IRQS 4 =20 -#define ARCH_GIC_MAINT_IRQ 9 +#define ARCH_GIC_MAINT_IRQ 25 =20 -#define ARCH_TIMER_VIRT_IRQ 11 -#define ARCH_TIMER_S_EL1_IRQ 13 -#define ARCH_TIMER_NS_EL1_IRQ 14 -#define ARCH_TIMER_NS_EL2_IRQ 10 +#define ARCH_TIMER_VIRT_IRQ 27 +#define ARCH_TIMER_S_EL1_IRQ 29 +#define ARCH_TIMER_NS_EL1_IRQ 30 +#define ARCH_TIMER_NS_EL2_IRQ 26 =20 -#define VIRTUAL_PMU_IRQ 7 +#define VIRTUAL_PMU_IRQ 23 =20 -#define PPI(irq) ((irq) + 16) +#define PPI(irq) ((irq) - 16) =20 /* See Linux kernel arch/arm64/include/asm/pvclock-abi.h */ #define PVTIME_SIZE_PER_CPU 64 --=20 2.30.2 From nobody Sat May 18 15:38:16 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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bh=PrkOgQCZH2Q4EgYsCq7gML0NEEoriMloQQM/qQbzSdg=; b=cRzOmhJ/sqxSS3XXXyzHxYaqWdD2GkSe8vJR+uYaBGS4dbv0JGlIBU7LTnA4UunrgoWh +b0fduou+QzyFa/3YrgTafqxh0uGhMoNd7JvizIdogl1AuB+EhHUue15mJKOkDM8r6R8 eZMMAJlz3Hz6ImddI1p/Phjfk6NystU1lTfqDRQXL6Vbg14/tZGlPS1ZbiH65z6m0rg3 r3l9+WmNPohjvuGVDTdzQJrBrBWQr54iBW4QyxZAdrrsiNAFMnSFFR7Jl+ff/Cm3Ei/D Ed4X0p4GqlbFKpgNKvjyGv5X4QORwrsGf2YhvZI/R5rChzNdns+ArskY0eUl3+t8E6Gn YA== From: Leif Lindholm To: CC: , Radoslaw Biernacki , Peter Maydell , Marcin Juszkiewicz , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v1 2/3] include/hw/arm: move BSA definitions to bsa.h Date: Fri, 15 Sep 2023 12:55:34 +0100 Message-ID: <20230915115535.129834-3-quic_llindhol@quicinc.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20230915115535.129834-1-quic_llindhol@quicinc.com> References: <20230915115535.129834-1-quic_llindhol@quicinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: ZmAS8SnhLkLpTtfUGGK-tNH-c77YO11a X-Proofpoint-ORIG-GUID: ZmAS8SnhLkLpTtfUGGK-tNH-c77YO11a X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.980,Hydra:6.0.601,FMLib:17.11.176.26 definitions=2023-09-15_08,2023-09-14_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 suspectscore=0 lowpriorityscore=0 spamscore=0 impostorscore=0 bulkscore=0 clxscore=1015 mlxlogscore=387 phishscore=0 adultscore=0 malwarescore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2308100000 definitions=main-2309150106 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=quic_llindhol@quicinc.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @quicinc.com) X-ZM-MESSAGEID: 1694779020724100001 Content-Type: text/plain; charset="utf-8" virt.h defines a number of IRQs that are ultimately described by Arm's Base System Architecture specification. Move these to a dedicated header so that they can be reused by other platforms that do the same. Include that header from virt.h to minimise churn. Signed-off-by: Leif Lindholm Reviewed-by: Marcin Juszkiewicz Tested-by: Marcin Juszkiewicz --- include/hw/arm/bsa.h | 35 +++++++++++++++++++++++++++++++++++ include/hw/arm/virt.h | 12 +----------- 2 files changed, 36 insertions(+), 11 deletions(-) create mode 100644 include/hw/arm/bsa.h diff --git a/include/hw/arm/bsa.h b/include/hw/arm/bsa.h new file mode 100644 index 0000000000..b7db1cacf1 --- /dev/null +++ b/include/hw/arm/bsa.h @@ -0,0 +1,35 @@ +/* + * Common definitions for Arm Base System Architecture (BSA) platforms. + * + * Copyright (c) 2015 Linaro Limited + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or + * more details. + * + * You should have received a copy of the GNU General Public License along= with + * this program. If not, see . + * + */ + +#ifndef QEMU_ARM_BSA_H +#define QEMU_ARM_BSA_H + +#define ARCH_GIC_MAINT_IRQ 25 + +#define ARCH_TIMER_VIRT_IRQ 27 +#define ARCH_TIMER_S_EL1_IRQ 29 +#define ARCH_TIMER_NS_EL1_IRQ 30 +#define ARCH_TIMER_NS_EL2_IRQ 26 + +#define VIRTUAL_PMU_IRQ 23 + +#define PPI(irq) ((irq) - 16) + +#endif /* QEMU_ARM_BSA_H */ diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h index 8ba4e5b836..f69239850e 100644 --- a/include/hw/arm/virt.h +++ b/include/hw/arm/virt.h @@ -34,6 +34,7 @@ #include "qemu/notify.h" #include "hw/boards.h" #include "hw/arm/boot.h" +#include "hw/arm/bsa.h" #include "hw/block/flash.h" #include "sysemu/kvm.h" #include "hw/intc/arm_gicv3_common.h" @@ -43,17 +44,6 @@ #define NUM_VIRTIO_TRANSPORTS 32 #define NUM_SMMU_IRQS 4 =20 -#define ARCH_GIC_MAINT_IRQ 25 - -#define ARCH_TIMER_VIRT_IRQ 27 -#define ARCH_TIMER_S_EL1_IRQ 29 -#define ARCH_TIMER_NS_EL1_IRQ 30 -#define ARCH_TIMER_NS_EL2_IRQ 26 - -#define VIRTUAL_PMU_IRQ 23 - -#define PPI(irq) ((irq) - 16) - /* See Linux kernel arch/arm64/include/asm/pvclock-abi.h */ #define PVTIME_SIZE_PER_CPU 64 =20 --=20 2.30.2 From nobody Sat May 18 15:38:16 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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bh=5DvEs4xO/6B9ch/QBDA3720rbF8VAaCdkLX4aOBmM1w=; b=izDULcVaSmYNhkIrZHSpDOBMKFKxpvQA7Npc72YhnQTG6zxIClDJCWAsfOJzIPfGlUWY 91ImFSPhN4sgIen7lZA4AtAhbsx3dab0sm0tlGxcrRciEYqYUT040xpji/WZyOH6qg0f sqKVo18N7slPQAAreRZwouU731R2JMPRJYPjDAsxcmS+1oBn7nY4tVZZnq+sG85X6kLd Vlc2jC8hSObi2h4LU+OZKDpi4zRGeb0JhcRYKg2N3OD0tBlZGF3anFUXEw5GzezsXRjs YsijIJYuTAnOg81g08eGD/vIw/r8wiqcUhcSMSAe7evYlnSHuHREpWe1miuFbr8+Z3Gd 5g== From: Leif Lindholm To: CC: , Radoslaw Biernacki , Peter Maydell , Marcin Juszkiewicz , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v1 3/3] hw/arm/sbsa-ref: use bsa.h for PPI definitions Date: Fri, 15 Sep 2023 12:55:35 +0100 Message-ID: <20230915115535.129834-4-quic_llindhol@quicinc.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20230915115535.129834-1-quic_llindhol@quicinc.com> References: <20230915115535.129834-1-quic_llindhol@quicinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: _yngj1rYPhwN7Yxx_WT2cWVSs_ES2qnR X-Proofpoint-ORIG-GUID: _yngj1rYPhwN7Yxx_WT2cWVSs_ES2qnR X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.980,Hydra:6.0.601,FMLib:17.11.176.26 definitions=2023-09-15_08,2023-09-14_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 impostorscore=0 clxscore=1015 phishscore=0 spamscore=0 mlxscore=0 adultscore=0 suspectscore=0 lowpriorityscore=0 malwarescore=0 bulkscore=0 mlxlogscore=510 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2308100000 definitions=main-2309150106 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=quic_llindhol@quicinc.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @quicinc.com) X-ZM-MESSAGEID: 1694779041745100003 Content-Type: text/plain; charset="utf-8" Use the private peripheral interrupt definitions from bsa.h instead of defining them locally. Refactor to use PPI() to convert from INTID macro where necessary. Signed-off-by: Leif Lindholm Reviewed-by: Marcin Juszkiewicz Tested-by: Marcin Juszkiewicz --- hw/arm/sbsa-ref.c | 23 +++++++++++------------ 1 file changed, 11 insertions(+), 12 deletions(-) diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c index bc89eb4806..3a4ea4dfdd 100644 --- a/hw/arm/sbsa-ref.c +++ b/hw/arm/sbsa-ref.c @@ -2,6 +2,7 @@ * ARM SBSA Reference Platform emulation * * Copyright (c) 2018 Linaro Limited + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. * Written by Hongbo Zhang * * This program is free software; you can redistribute it and/or modify it @@ -30,6 +31,7 @@ #include "exec/hwaddr.h" #include "kvm_arm.h" #include "hw/arm/boot.h" +#include "hw/arm/bsa.h" #include "hw/arm/fdt.h" #include "hw/arm/smmuv3.h" #include "hw/block/flash.h" @@ -55,13 +57,6 @@ #define NUM_SMMU_IRQS 4 #define NUM_SATA_PORTS 6 =20 -#define VIRTUAL_PMU_IRQ 7 -#define ARCH_GIC_MAINT_IRQ 9 -#define ARCH_TIMER_VIRT_IRQ 11 -#define ARCH_TIMER_S_EL1_IRQ 13 -#define ARCH_TIMER_NS_EL1_IRQ 14 -#define ARCH_TIMER_NS_EL2_IRQ 10 - enum { SBSA_FLASH, SBSA_MEM, @@ -494,15 +489,19 @@ static void create_gic(SBSAMachineState *sms, MemoryR= egion *mem) for (irq =3D 0; irq < ARRAY_SIZE(timer_irq); irq++) { qdev_connect_gpio_out(cpudev, irq, qdev_get_gpio_in(sms->gic, - ppibase + timer_irq[irq= ])); + ppibase + + PPI(timer_irq[irq]))); } =20 qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt",= 0, - qdev_get_gpio_in(sms->gic, ppibase - + ARCH_GIC_MAINT_IRQ)= ); + qdev_get_gpio_in(sms->gic, + ppibase + + PPI(ARCH_GIC_MAINT_= IRQ))); + qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0, - qdev_get_gpio_in(sms->gic, ppibase - + VIRTUAL_PMU_IRQ)); + qdev_get_gpio_in(sms->gic, + ppibase + + PPI(VIRTUAL_PMU_IRQ= ))); =20 sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_= IRQ)); sysbus_connect_irq(gicbusdev, i + smp_cpus, --=20 2.30.2