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([71.212.131.115]) by smtp.gmail.com with ESMTPSA id x24-20020a170902b41800b001bbdf32f011sm304336plr.269.2023.09.13.19.44.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 13 Sep 2023 19:44:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1694659494; x=1695264294; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=QlRjSPu9pkKe5z3aMOZ1zMotJJX6cUOFzXt13L4Ml2s=; b=icQKAnAc5W8isja7J1LIeuPu3bdK9QRvtMIU5KM+nBHwN/okSN2mJ2Y7vMxZgbnpbp BwbQEW2PgoEb37EAsHX5dELxJN1/sgVZNLL4AAFebnh6NNnea+S96f4qLgBN4S2B3FI2 7umFffJMZDVgMdwGi0/8K9YggQXbad1nBEfh6N7BgbHMs5NYsSrkVTL2teFNdsS9OsE3 0zzq/vSfa9VazmzTHdQNqkETcJw7utf4CtV2pbgSlM3t3N4PNB5xism6x2NvrqRi50HR JjuMN8m0VVOdm24ZBb7jUqtj8byzWvsSi8BiJNT9ioev0PB3V85ZczbrTn5GxEGvJiOl PB7g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1694659494; x=1695264294; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=QlRjSPu9pkKe5z3aMOZ1zMotJJX6cUOFzXt13L4Ml2s=; b=aEKTjGAP/+knr1rXoXLej+zXlIf/WTRncB06NCJgDcf3AGoz0yEBf/Ddl/eoflHAzh Zv1ZxZeXXOXEPFqy+VPfOm1BsPWkrRSWlTEl5NBYpf72k3bP2Q9Misn3mAeBjfA8z7Iq Q3njat6JRtI61wVpHwBZrTx3+B54Uk0OlZUNayGvuOHnTiPjqP1hOQ5UmAjASx7dmNH7 NLHzOomkkLSwDuSn3FI0NoLyg9aLu14hR+FoCWpD+XjXMqJMF8/SsXLjTtRHdxwOiwS+ dyf/lSX3DlIKJax5rSoURm88pifiiwODwRYojwP0sat/XAIyIyhr5P+0wEq2VZbojW0y ZwTA== X-Gm-Message-State: AOJu0YxMHZ3ncICG9RkXbZ3n+SDcEuVdpxLMhj1onGlT+ZZNLOgMjm5r YbPtkTx15JOhW3WjOn4dD02Uqr13mV/cypvoyak= X-Google-Smtp-Source: AGHT+IHb0auVpJa1folNldkG/GoR5C++Hvu62gvJEVMN6dJnHi2cFcVnwcqmr0nzLgowv9Z9rPTVzQ== X-Received: by 2002:a17:902:f54b:b0:1c3:6018:fda4 with SMTP id h11-20020a170902f54b00b001c36018fda4mr5226008plf.64.1694659494390; Wed, 13 Sep 2023 19:44:54 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: anjo@rev.ng, ale@rev.ng, philmd@linaro.org Subject: [PATCH v2 19/24] accel/tcg: Modifies memory access functions to use CPUState Date: Wed, 13 Sep 2023 19:44:30 -0700 Message-Id: <20230914024435.1381329-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230914024435.1381329-1-richard.henderson@linaro.org> References: <20230914024435.1381329-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1694659632978100003 Content-Type: text/plain; charset="utf-8" From: Anton Johansson do_[ld|st]*() and mmu_lookup*() are changed to use CPUState over CPUArchState, moving the target-dependence to the target-facing facing cpu_[ld|st] functions. Signed-off-by: Anton Johansson Message-Id: <20230912153428.17816-6-anjo@rev.ng> Reviewed-by: Richard Henderson [rth: Use cpu->neg.tlb instead of cpu_tlb; cpu_env instead of env_ptr.] Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- accel/tcg/cputlb.c | 324 ++++++++++++++++++++++----------------------- 1 file changed, 161 insertions(+), 163 deletions(-) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index f3ac87050e..29c35bd201 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1367,11 +1367,10 @@ static void save_iotlb_data(CPUState *cs, MemoryReg= ionSection *section, #endif } =20 -static uint64_t io_readx(CPUArchState *env, CPUTLBEntryFull *full, +static uint64_t io_readx(CPUState *cpu, CPUTLBEntryFull *full, int mmu_idx, vaddr addr, uintptr_t retaddr, MMUAccessType access_type, MemOp op) { - CPUState *cpu =3D env_cpu(env); hwaddr mr_offset; MemoryRegionSection *section; MemoryRegion *mr; @@ -1408,11 +1407,10 @@ static uint64_t io_readx(CPUArchState *env, CPUTLBE= ntryFull *full, return val; } =20 -static void io_writex(CPUArchState *env, CPUTLBEntryFull *full, +static void io_writex(CPUState *cpu, CPUTLBEntryFull *full, int mmu_idx, uint64_t val, vaddr addr, uintptr_t retaddr, MemOp op) { - CPUState *cpu =3D env_cpu(env); hwaddr mr_offset; MemoryRegionSection *section; MemoryRegion *mr; @@ -1776,7 +1774,7 @@ typedef struct MMULookupLocals { =20 /** * mmu_lookup1: translate one page - * @env: cpu context + * @cpu: generic cpu state * @data: lookup parameters * @mmu_idx: virtual address context * @access_type: load/store/code @@ -1787,12 +1785,12 @@ typedef struct MMULookupLocals { * tlb_fill will longjmp out. Return true if the softmmu tlb for * @mmu_idx may have resized. */ -static bool mmu_lookup1(CPUArchState *env, MMULookupPageData *data, +static bool mmu_lookup1(CPUState *cpu, MMULookupPageData *data, int mmu_idx, MMUAccessType access_type, uintptr_t = ra) { vaddr addr =3D data->addr; - uintptr_t index =3D tlb_index(env_cpu(env), mmu_idx, addr); - CPUTLBEntry *entry =3D tlb_entry(env_cpu(env), mmu_idx, addr); + uintptr_t index =3D tlb_index(cpu, mmu_idx, addr); + CPUTLBEntry *entry =3D tlb_entry(cpu, mmu_idx, addr); uint64_t tlb_addr =3D tlb_read_idx(entry, access_type); bool maybe_resized =3D false; CPUTLBEntryFull *full; @@ -1800,17 +1798,17 @@ static bool mmu_lookup1(CPUArchState *env, MMULooku= pPageData *data, =20 /* If the TLB entry is for a different page, reload and try again. */ if (!tlb_hit(tlb_addr, addr)) { - if (!victim_tlb_hit(env_cpu(env), mmu_idx, index, access_type, + if (!victim_tlb_hit(cpu, mmu_idx, index, access_type, addr & TARGET_PAGE_MASK)) { - tlb_fill(env_cpu(env), addr, data->size, access_type, mmu_idx,= ra); + tlb_fill(cpu, addr, data->size, access_type, mmu_idx, ra); maybe_resized =3D true; - index =3D tlb_index(env_cpu(env), mmu_idx, addr); - entry =3D tlb_entry(env_cpu(env), mmu_idx, addr); + index =3D tlb_index(cpu, mmu_idx, addr); + entry =3D tlb_entry(cpu, mmu_idx, addr); } tlb_addr =3D tlb_read_idx(entry, access_type) & ~TLB_INVALID_MASK; } =20 - full =3D &env_tlb(env)->d[mmu_idx].fulltlb[index]; + full =3D &cpu->neg.tlb.d[mmu_idx].fulltlb[index]; flags =3D tlb_addr & (TLB_FLAGS_MASK & ~TLB_FORCE_SLOW); flags |=3D full->slow_flags[access_type]; =20 @@ -1824,7 +1822,7 @@ static bool mmu_lookup1(CPUArchState *env, MMULookupP= ageData *data, =20 /** * mmu_watch_or_dirty - * @env: cpu context + * @cpu: generic cpu state * @data: lookup parameters * @access_type: load/store/code * @ra: return address into tcg generated code, or 0 @@ -1832,7 +1830,7 @@ static bool mmu_lookup1(CPUArchState *env, MMULookupP= ageData *data, * Trigger watchpoints for @data.addr:@data.size; * record writes to protected clean pages. */ -static void mmu_watch_or_dirty(CPUArchState *env, MMULookupPageData *data, +static void mmu_watch_or_dirty(CPUState *cpu, MMULookupPageData *data, MMUAccessType access_type, uintptr_t ra) { CPUTLBEntryFull *full =3D data->full; @@ -1843,13 +1841,13 @@ static void mmu_watch_or_dirty(CPUArchState *env, M= MULookupPageData *data, /* On watchpoint hit, this will longjmp out. */ if (flags & TLB_WATCHPOINT) { int wp =3D access_type =3D=3D MMU_DATA_STORE ? BP_MEM_WRITE : BP_M= EM_READ; - cpu_check_watchpoint(env_cpu(env), addr, size, full->attrs, wp, ra= ); + cpu_check_watchpoint(cpu, addr, size, full->attrs, wp, ra); flags &=3D ~TLB_WATCHPOINT; } =20 /* Note that notdirty is only set for writes. */ if (flags & TLB_NOTDIRTY) { - notdirty_write(env_cpu(env), addr, size, full, ra); + notdirty_write(cpu, addr, size, full, ra); flags &=3D ~TLB_NOTDIRTY; } data->flags =3D flags; @@ -1857,7 +1855,7 @@ static void mmu_watch_or_dirty(CPUArchState *env, MMU= LookupPageData *data, =20 /** * mmu_lookup: translate page(s) - * @env: cpu context + * @cpu: generic cpu state * @addr: virtual address * @oi: combined mmu_idx and MemOp * @ra: return address into tcg generated code, or 0 @@ -1867,7 +1865,7 @@ static void mmu_watch_or_dirty(CPUArchState *env, MMU= LookupPageData *data, * Resolve the translation for the page(s) beginning at @addr, for MemOp.s= ize * bytes. Return true if the lookup crosses a page boundary. */ -static bool mmu_lookup(CPUArchState *env, vaddr addr, MemOpIdx oi, +static bool mmu_lookup(CPUState *cpu, vaddr addr, MemOpIdx oi, uintptr_t ra, MMUAccessType type, MMULookupLocals *= l) { unsigned a_bits; @@ -1882,7 +1880,7 @@ static bool mmu_lookup(CPUArchState *env, vaddr addr,= MemOpIdx oi, /* Handle CPU specific unaligned behaviour */ a_bits =3D get_alignment_bits(l->memop); if (addr & ((1 << a_bits) - 1)) { - cpu_unaligned_access(env_cpu(env), addr, type, l->mmu_idx, ra); + cpu_unaligned_access(cpu, addr, type, l->mmu_idx, ra); } =20 l->page[0].addr =3D addr; @@ -1892,11 +1890,11 @@ static bool mmu_lookup(CPUArchState *env, vaddr add= r, MemOpIdx oi, crosspage =3D (addr ^ l->page[1].addr) & TARGET_PAGE_MASK; =20 if (likely(!crosspage)) { - mmu_lookup1(env, &l->page[0], l->mmu_idx, type, ra); + mmu_lookup1(cpu, &l->page[0], l->mmu_idx, type, ra); =20 flags =3D l->page[0].flags; if (unlikely(flags & (TLB_WATCHPOINT | TLB_NOTDIRTY))) { - mmu_watch_or_dirty(env, &l->page[0], type, ra); + mmu_watch_or_dirty(cpu, &l->page[0], type, ra); } if (unlikely(flags & TLB_BSWAP)) { l->memop ^=3D MO_BSWAP; @@ -1911,16 +1909,16 @@ static bool mmu_lookup(CPUArchState *env, vaddr add= r, MemOpIdx oi, * Lookup both pages, recognizing exceptions from either. If the * second lookup potentially resized, refresh first CPUTLBEntryFul= l. */ - mmu_lookup1(env, &l->page[0], l->mmu_idx, type, ra); - if (mmu_lookup1(env, &l->page[1], l->mmu_idx, type, ra)) { - uintptr_t index =3D tlb_index(env_cpu(env), l->mmu_idx, addr); - l->page[0].full =3D &env_tlb(env)->d[l->mmu_idx].fulltlb[index= ]; + mmu_lookup1(cpu, &l->page[0], l->mmu_idx, type, ra); + if (mmu_lookup1(cpu, &l->page[1], l->mmu_idx, type, ra)) { + uintptr_t index =3D tlb_index(cpu, l->mmu_idx, addr); + l->page[0].full =3D &cpu->neg.tlb.d[l->mmu_idx].fulltlb[index]; } =20 flags =3D l->page[0].flags | l->page[1].flags; if (unlikely(flags & (TLB_WATCHPOINT | TLB_NOTDIRTY))) { - mmu_watch_or_dirty(env, &l->page[0], type, ra); - mmu_watch_or_dirty(env, &l->page[1], type, ra); + mmu_watch_or_dirty(cpu, &l->page[0], type, ra); + mmu_watch_or_dirty(cpu, &l->page[1], type, ra); } =20 /* @@ -2060,7 +2058,7 @@ static void *atomic_mmu_lookup(CPUArchState *env, vad= dr addr, MemOpIdx oi, =20 /** * do_ld_mmio_beN: - * @env: cpu context + * @cpu: generic cpu state * @full: page parameters * @ret_be: accumulated data * @addr: virtual address @@ -2072,7 +2070,7 @@ static void *atomic_mmu_lookup(CPUArchState *env, vad= dr addr, MemOpIdx oi, * Load @size bytes from @addr, which is memory-mapped i/o. * The bytes are concatenated in big-endian order with @ret_be. */ -static uint64_t do_ld_mmio_beN(CPUArchState *env, CPUTLBEntryFull *full, +static uint64_t do_ld_mmio_beN(CPUState *cpu, CPUTLBEntryFull *full, uint64_t ret_be, vaddr addr, int size, int mmu_idx, MMUAccessType type, uintptr_t = ra) { @@ -2086,26 +2084,26 @@ static uint64_t do_ld_mmio_beN(CPUArchState *env, C= PUTLBEntryFull *full, case 3: case 5: case 7: - t =3D io_readx(env, full, mmu_idx, addr, ra, type, MO_UB); + t =3D io_readx(cpu, full, mmu_idx, addr, ra, type, MO_UB); ret_be =3D (ret_be << 8) | t; size -=3D 1; addr +=3D 1; break; case 2: case 6: - t =3D io_readx(env, full, mmu_idx, addr, ra, type, MO_BEUW); + t =3D io_readx(cpu, full, mmu_idx, addr, ra, type, MO_BEUW); ret_be =3D (ret_be << 16) | t; size -=3D 2; addr +=3D 2; break; case 4: - t =3D io_readx(env, full, mmu_idx, addr, ra, type, MO_BEUL); + t =3D io_readx(cpu, full, mmu_idx, addr, ra, type, MO_BEUL); ret_be =3D (ret_be << 32) | t; size -=3D 4; addr +=3D 4; break; case 0: - return io_readx(env, full, mmu_idx, addr, ra, type, MO_BEUQ); + return io_readx(cpu, full, mmu_idx, addr, ra, type, MO_BEUQ); default: qemu_build_not_reached(); } @@ -2207,11 +2205,11 @@ static uint64_t do_ld_whole_be4(MMULookupPageData *= p, uint64_t ret_be) * As do_ld_bytes_beN, but with one atomic load. * Eight aligned bytes are guaranteed to cover the load. */ -static uint64_t do_ld_whole_be8(CPUArchState *env, uintptr_t ra, +static uint64_t do_ld_whole_be8(CPUState *cpu, uintptr_t ra, MMULookupPageData *p, uint64_t ret_be) { int o =3D p->addr & 7; - uint64_t x =3D load_atomic8_or_exit(env, ra, p->haddr - o); + uint64_t x =3D load_atomic8_or_exit(cpu_env(cpu), ra, p->haddr - o); =20 x =3D cpu_to_be64(x); x <<=3D o * 8; @@ -2227,11 +2225,11 @@ static uint64_t do_ld_whole_be8(CPUArchState *env, = uintptr_t ra, * As do_ld_bytes_beN, but with one atomic load. * 16 aligned bytes are guaranteed to cover the load. */ -static Int128 do_ld_whole_be16(CPUArchState *env, uintptr_t ra, +static Int128 do_ld_whole_be16(CPUState *cpu, uintptr_t ra, MMULookupPageData *p, uint64_t ret_be) { int o =3D p->addr & 15; - Int128 x, y =3D load_atomic16_or_exit(env, ra, p->haddr - o); + Int128 x, y =3D load_atomic16_or_exit(cpu_env(cpu), ra, p->haddr - o); int size =3D p->size; =20 if (!HOST_BIG_ENDIAN) { @@ -2247,7 +2245,7 @@ static Int128 do_ld_whole_be16(CPUArchState *env, uin= tptr_t ra, /* * Wrapper for the above. */ -static uint64_t do_ld_beN(CPUArchState *env, MMULookupPageData *p, +static uint64_t do_ld_beN(CPUState *cpu, MMULookupPageData *p, uint64_t ret_be, int mmu_idx, MMUAccessType type, MemOp mop, uintptr_t ra) { @@ -2256,7 +2254,7 @@ static uint64_t do_ld_beN(CPUArchState *env, MMULooku= pPageData *p, =20 if (unlikely(p->flags & TLB_MMIO)) { QEMU_IOTHREAD_LOCK_GUARD(); - return do_ld_mmio_beN(env, p->full, ret_be, p->addr, p->size, + return do_ld_mmio_beN(cpu, p->full, ret_be, p->addr, p->size, mmu_idx, type, ra); } =20 @@ -2280,7 +2278,7 @@ static uint64_t do_ld_beN(CPUArchState *env, MMULooku= pPageData *p, if (!HAVE_al8_fast && p->size < 4) { return do_ld_whole_be4(p, ret_be); } else { - return do_ld_whole_be8(env, ra, p, ret_be); + return do_ld_whole_be8(cpu, ra, p, ret_be); } } /* fall through */ @@ -2298,7 +2296,7 @@ static uint64_t do_ld_beN(CPUArchState *env, MMULooku= pPageData *p, /* * Wrapper for the above, for 8 < size < 16. */ -static Int128 do_ld16_beN(CPUArchState *env, MMULookupPageData *p, +static Int128 do_ld16_beN(CPUState *cpu, MMULookupPageData *p, uint64_t a, int mmu_idx, MemOp mop, uintptr_t ra) { int size =3D p->size; @@ -2307,9 +2305,9 @@ static Int128 do_ld16_beN(CPUArchState *env, MMULooku= pPageData *p, =20 if (unlikely(p->flags & TLB_MMIO)) { QEMU_IOTHREAD_LOCK_GUARD(); - a =3D do_ld_mmio_beN(env, p->full, a, p->addr, size - 8, + a =3D do_ld_mmio_beN(cpu, p->full, a, p->addr, size - 8, mmu_idx, MMU_DATA_LOAD, ra); - b =3D do_ld_mmio_beN(env, p->full, 0, p->addr + 8, 8, + b =3D do_ld_mmio_beN(cpu, p->full, 0, p->addr + 8, 8, mmu_idx, MMU_DATA_LOAD, ra); return int128_make128(b, a); } @@ -2330,7 +2328,7 @@ static Int128 do_ld16_beN(CPUArchState *env, MMULooku= pPageData *p, =20 case MO_ATOM_WITHIN16_PAIR: /* Since size > 8, this is the half that must be atomic. */ - return do_ld_whole_be16(env, ra, p, a); + return do_ld_whole_be16(cpu, ra, p, a); =20 case MO_ATOM_IFALIGN_PAIR: /* @@ -2352,30 +2350,30 @@ static Int128 do_ld16_beN(CPUArchState *env, MMULoo= kupPageData *p, return int128_make128(b, a); } =20 -static uint8_t do_ld_1(CPUArchState *env, MMULookupPageData *p, int mmu_id= x, +static uint8_t do_ld_1(CPUState *cpu, MMULookupPageData *p, int mmu_idx, MMUAccessType type, uintptr_t ra) { if (unlikely(p->flags & TLB_MMIO)) { - return io_readx(env, p->full, mmu_idx, p->addr, ra, type, MO_UB); + return io_readx(cpu, p->full, mmu_idx, p->addr, ra, type, MO_UB); } else { return *(uint8_t *)p->haddr; } } =20 -static uint16_t do_ld_2(CPUArchState *env, MMULookupPageData *p, int mmu_i= dx, +static uint16_t do_ld_2(CPUState *cpu, MMULookupPageData *p, int mmu_idx, MMUAccessType type, MemOp memop, uintptr_t ra) { uint16_t ret; =20 if (unlikely(p->flags & TLB_MMIO)) { QEMU_IOTHREAD_LOCK_GUARD(); - ret =3D do_ld_mmio_beN(env, p->full, 0, p->addr, 2, mmu_idx, type,= ra); + ret =3D do_ld_mmio_beN(cpu, p->full, 0, p->addr, 2, mmu_idx, type,= ra); if ((memop & MO_BSWAP) =3D=3D MO_LE) { ret =3D bswap16(ret); } } else { /* Perform the load host endian, then swap if necessary. */ - ret =3D load_atom_2(env, ra, p->haddr, memop); + ret =3D load_atom_2(cpu_env(cpu), ra, p->haddr, memop); if (memop & MO_BSWAP) { ret =3D bswap16(ret); } @@ -2383,20 +2381,20 @@ static uint16_t do_ld_2(CPUArchState *env, MMULooku= pPageData *p, int mmu_idx, return ret; } =20 -static uint32_t do_ld_4(CPUArchState *env, MMULookupPageData *p, int mmu_i= dx, +static uint32_t do_ld_4(CPUState *cpu, MMULookupPageData *p, int mmu_idx, MMUAccessType type, MemOp memop, uintptr_t ra) { uint32_t ret; =20 if (unlikely(p->flags & TLB_MMIO)) { QEMU_IOTHREAD_LOCK_GUARD(); - ret =3D do_ld_mmio_beN(env, p->full, 0, p->addr, 4, mmu_idx, type,= ra); + ret =3D do_ld_mmio_beN(cpu, p->full, 0, p->addr, 4, mmu_idx, type,= ra); if ((memop & MO_BSWAP) =3D=3D MO_LE) { ret =3D bswap32(ret); } } else { /* Perform the load host endian. */ - ret =3D load_atom_4(env, ra, p->haddr, memop); + ret =3D load_atom_4(cpu_env(cpu), ra, p->haddr, memop); if (memop & MO_BSWAP) { ret =3D bswap32(ret); } @@ -2404,20 +2402,20 @@ static uint32_t do_ld_4(CPUArchState *env, MMULooku= pPageData *p, int mmu_idx, return ret; } =20 -static uint64_t do_ld_8(CPUArchState *env, MMULookupPageData *p, int mmu_i= dx, +static uint64_t do_ld_8(CPUState *cpu, MMULookupPageData *p, int mmu_idx, MMUAccessType type, MemOp memop, uintptr_t ra) { uint64_t ret; =20 if (unlikely(p->flags & TLB_MMIO)) { QEMU_IOTHREAD_LOCK_GUARD(); - ret =3D do_ld_mmio_beN(env, p->full, 0, p->addr, 8, mmu_idx, type,= ra); + ret =3D do_ld_mmio_beN(cpu, p->full, 0, p->addr, 8, mmu_idx, type,= ra); if ((memop & MO_BSWAP) =3D=3D MO_LE) { ret =3D bswap64(ret); } } else { /* Perform the load host endian. */ - ret =3D load_atom_8(env, ra, p->haddr, memop); + ret =3D load_atom_8(cpu_env(cpu), ra, p->haddr, memop); if (memop & MO_BSWAP) { ret =3D bswap64(ret); } @@ -2425,27 +2423,27 @@ static uint64_t do_ld_8(CPUArchState *env, MMULooku= pPageData *p, int mmu_idx, return ret; } =20 -static uint8_t do_ld1_mmu(CPUArchState *env, vaddr addr, MemOpIdx oi, +static uint8_t do_ld1_mmu(CPUState *cpu, vaddr addr, MemOpIdx oi, uintptr_t ra, MMUAccessType access_type) { MMULookupLocals l; bool crosspage; =20 cpu_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); - crosspage =3D mmu_lookup(env, addr, oi, ra, access_type, &l); + crosspage =3D mmu_lookup(cpu, addr, oi, ra, access_type, &l); tcg_debug_assert(!crosspage); =20 - return do_ld_1(env, &l.page[0], l.mmu_idx, access_type, ra); + return do_ld_1(cpu, &l.page[0], l.mmu_idx, access_type, ra); } =20 tcg_target_ulong helper_ldub_mmu(CPUArchState *env, uint64_t addr, MemOpIdx oi, uintptr_t retaddr) { tcg_debug_assert((get_memop(oi) & MO_SIZE) =3D=3D MO_8); - return do_ld1_mmu(env, addr, oi, retaddr, MMU_DATA_LOAD); + return do_ld1_mmu(env_cpu(env), addr, oi, retaddr, MMU_DATA_LOAD); } =20 -static uint16_t do_ld2_mmu(CPUArchState *env, vaddr addr, MemOpIdx oi, +static uint16_t do_ld2_mmu(CPUState *cpu, vaddr addr, MemOpIdx oi, uintptr_t ra, MMUAccessType access_type) { MMULookupLocals l; @@ -2454,13 +2452,13 @@ static uint16_t do_ld2_mmu(CPUArchState *env, vaddr= addr, MemOpIdx oi, uint8_t a, b; =20 cpu_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); - crosspage =3D mmu_lookup(env, addr, oi, ra, access_type, &l); + crosspage =3D mmu_lookup(cpu, addr, oi, ra, access_type, &l); if (likely(!crosspage)) { - return do_ld_2(env, &l.page[0], l.mmu_idx, access_type, l.memop, r= a); + return do_ld_2(cpu, &l.page[0], l.mmu_idx, access_type, l.memop, r= a); } =20 - a =3D do_ld_1(env, &l.page[0], l.mmu_idx, access_type, ra); - b =3D do_ld_1(env, &l.page[1], l.mmu_idx, access_type, ra); + a =3D do_ld_1(cpu, &l.page[0], l.mmu_idx, access_type, ra); + b =3D do_ld_1(cpu, &l.page[1], l.mmu_idx, access_type, ra); =20 if ((l.memop & MO_BSWAP) =3D=3D MO_LE) { ret =3D a | (b << 8); @@ -2474,10 +2472,10 @@ tcg_target_ulong helper_lduw_mmu(CPUArchState *env,= uint64_t addr, MemOpIdx oi, uintptr_t retaddr) { tcg_debug_assert((get_memop(oi) & MO_SIZE) =3D=3D MO_16); - return do_ld2_mmu(env, addr, oi, retaddr, MMU_DATA_LOAD); + return do_ld2_mmu(env_cpu(env), addr, oi, retaddr, MMU_DATA_LOAD); } =20 -static uint32_t do_ld4_mmu(CPUArchState *env, vaddr addr, MemOpIdx oi, +static uint32_t do_ld4_mmu(CPUState *cpu, vaddr addr, MemOpIdx oi, uintptr_t ra, MMUAccessType access_type) { MMULookupLocals l; @@ -2485,13 +2483,13 @@ static uint32_t do_ld4_mmu(CPUArchState *env, vaddr= addr, MemOpIdx oi, uint32_t ret; =20 cpu_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); - crosspage =3D mmu_lookup(env, addr, oi, ra, access_type, &l); + crosspage =3D mmu_lookup(cpu, addr, oi, ra, access_type, &l); if (likely(!crosspage)) { - return do_ld_4(env, &l.page[0], l.mmu_idx, access_type, l.memop, r= a); + return do_ld_4(cpu, &l.page[0], l.mmu_idx, access_type, l.memop, r= a); } =20 - ret =3D do_ld_beN(env, &l.page[0], 0, l.mmu_idx, access_type, l.memop,= ra); - ret =3D do_ld_beN(env, &l.page[1], ret, l.mmu_idx, access_type, l.memo= p, ra); + ret =3D do_ld_beN(cpu, &l.page[0], 0, l.mmu_idx, access_type, l.memop,= ra); + ret =3D do_ld_beN(cpu, &l.page[1], ret, l.mmu_idx, access_type, l.memo= p, ra); if ((l.memop & MO_BSWAP) =3D=3D MO_LE) { ret =3D bswap32(ret); } @@ -2502,10 +2500,10 @@ tcg_target_ulong helper_ldul_mmu(CPUArchState *env,= uint64_t addr, MemOpIdx oi, uintptr_t retaddr) { tcg_debug_assert((get_memop(oi) & MO_SIZE) =3D=3D MO_32); - return do_ld4_mmu(env, addr, oi, retaddr, MMU_DATA_LOAD); + return do_ld4_mmu(env_cpu(env), addr, oi, retaddr, MMU_DATA_LOAD); } =20 -static uint64_t do_ld8_mmu(CPUArchState *env, vaddr addr, MemOpIdx oi, +static uint64_t do_ld8_mmu(CPUState *cpu, vaddr addr, MemOpIdx oi, uintptr_t ra, MMUAccessType access_type) { MMULookupLocals l; @@ -2513,13 +2511,13 @@ static uint64_t do_ld8_mmu(CPUArchState *env, vaddr= addr, MemOpIdx oi, uint64_t ret; =20 cpu_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); - crosspage =3D mmu_lookup(env, addr, oi, ra, access_type, &l); + crosspage =3D mmu_lookup(cpu, addr, oi, ra, access_type, &l); if (likely(!crosspage)) { - return do_ld_8(env, &l.page[0], l.mmu_idx, access_type, l.memop, r= a); + return do_ld_8(cpu, &l.page[0], l.mmu_idx, access_type, l.memop, r= a); } =20 - ret =3D do_ld_beN(env, &l.page[0], 0, l.mmu_idx, access_type, l.memop,= ra); - ret =3D do_ld_beN(env, &l.page[1], ret, l.mmu_idx, access_type, l.memo= p, ra); + ret =3D do_ld_beN(cpu, &l.page[0], 0, l.mmu_idx, access_type, l.memop,= ra); + ret =3D do_ld_beN(cpu, &l.page[1], ret, l.mmu_idx, access_type, l.memo= p, ra); if ((l.memop & MO_BSWAP) =3D=3D MO_LE) { ret =3D bswap64(ret); } @@ -2530,7 +2528,7 @@ uint64_t helper_ldq_mmu(CPUArchState *env, uint64_t a= ddr, MemOpIdx oi, uintptr_t retaddr) { tcg_debug_assert((get_memop(oi) & MO_SIZE) =3D=3D MO_64); - return do_ld8_mmu(env, addr, oi, retaddr, MMU_DATA_LOAD); + return do_ld8_mmu(env_cpu(env), addr, oi, retaddr, MMU_DATA_LOAD); } =20 /* @@ -2556,7 +2554,7 @@ tcg_target_ulong helper_ldsl_mmu(CPUArchState *env, u= int64_t addr, return (int32_t)helper_ldul_mmu(env, addr, oi, retaddr); } =20 -static Int128 do_ld16_mmu(CPUArchState *env, vaddr addr, +static Int128 do_ld16_mmu(CPUState *cpu, vaddr addr, MemOpIdx oi, uintptr_t ra) { MMULookupLocals l; @@ -2566,13 +2564,13 @@ static Int128 do_ld16_mmu(CPUArchState *env, vaddr = addr, int first; =20 cpu_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); - crosspage =3D mmu_lookup(env, addr, oi, ra, MMU_DATA_LOAD, &l); + crosspage =3D mmu_lookup(cpu, addr, oi, ra, MMU_DATA_LOAD, &l); if (likely(!crosspage)) { if (unlikely(l.page[0].flags & TLB_MMIO)) { QEMU_IOTHREAD_LOCK_GUARD(); - a =3D do_ld_mmio_beN(env, l.page[0].full, 0, addr, 8, + a =3D do_ld_mmio_beN(cpu, l.page[0].full, 0, addr, 8, l.mmu_idx, MMU_DATA_LOAD, ra); - b =3D do_ld_mmio_beN(env, l.page[0].full, 0, addr + 8, 8, + b =3D do_ld_mmio_beN(cpu, l.page[0].full, 0, addr + 8, 8, l.mmu_idx, MMU_DATA_LOAD, ra); ret =3D int128_make128(b, a); if ((l.memop & MO_BSWAP) =3D=3D MO_LE) { @@ -2580,7 +2578,7 @@ static Int128 do_ld16_mmu(CPUArchState *env, vaddr ad= dr, } } else { /* Perform the load host endian. */ - ret =3D load_atom_16(env, ra, l.page[0].haddr, l.memop); + ret =3D load_atom_16(cpu_env(cpu), ra, l.page[0].haddr, l.memo= p); if (l.memop & MO_BSWAP) { ret =3D bswap128(ret); } @@ -2592,8 +2590,8 @@ static Int128 do_ld16_mmu(CPUArchState *env, vaddr ad= dr, if (first =3D=3D 8) { MemOp mop8 =3D (l.memop & ~MO_SIZE) | MO_64; =20 - a =3D do_ld_8(env, &l.page[0], l.mmu_idx, MMU_DATA_LOAD, mop8, ra); - b =3D do_ld_8(env, &l.page[1], l.mmu_idx, MMU_DATA_LOAD, mop8, ra); + a =3D do_ld_8(cpu, &l.page[0], l.mmu_idx, MMU_DATA_LOAD, mop8, ra); + b =3D do_ld_8(cpu, &l.page[1], l.mmu_idx, MMU_DATA_LOAD, mop8, ra); if ((mop8 & MO_BSWAP) =3D=3D MO_LE) { ret =3D int128_make128(a, b); } else { @@ -2603,15 +2601,15 @@ static Int128 do_ld16_mmu(CPUArchState *env, vaddr = addr, } =20 if (first < 8) { - a =3D do_ld_beN(env, &l.page[0], 0, l.mmu_idx, + a =3D do_ld_beN(cpu, &l.page[0], 0, l.mmu_idx, MMU_DATA_LOAD, l.memop, ra); - ret =3D do_ld16_beN(env, &l.page[1], a, l.mmu_idx, l.memop, ra); + ret =3D do_ld16_beN(cpu, &l.page[1], a, l.mmu_idx, l.memop, ra); } else { - ret =3D do_ld16_beN(env, &l.page[0], 0, l.mmu_idx, l.memop, ra); + ret =3D do_ld16_beN(cpu, &l.page[0], 0, l.mmu_idx, l.memop, ra); b =3D int128_getlo(ret); ret =3D int128_lshift(ret, l.page[1].size * 8); a =3D int128_gethi(ret); - b =3D do_ld_beN(env, &l.page[1], b, l.mmu_idx, + b =3D do_ld_beN(cpu, &l.page[1], b, l.mmu_idx, MMU_DATA_LOAD, l.memop, ra); ret =3D int128_make128(b, a); } @@ -2625,7 +2623,7 @@ Int128 helper_ld16_mmu(CPUArchState *env, uint64_t ad= dr, uint32_t oi, uintptr_t retaddr) { tcg_debug_assert((get_memop(oi) & MO_SIZE) =3D=3D MO_128); - return do_ld16_mmu(env, addr, oi, retaddr); + return do_ld16_mmu(env_cpu(env), addr, oi, retaddr); } =20 Int128 helper_ld_i128(CPUArchState *env, uint64_t addr, uint32_t oi) @@ -2647,7 +2645,7 @@ uint8_t cpu_ldb_mmu(CPUArchState *env, abi_ptr addr, = MemOpIdx oi, uintptr_t ra) uint8_t ret; =20 tcg_debug_assert((get_memop(oi) & MO_SIZE) =3D=3D MO_UB); - ret =3D do_ld1_mmu(env, addr, oi, ra, MMU_DATA_LOAD); + ret =3D do_ld1_mmu(env_cpu(env), addr, oi, ra, MMU_DATA_LOAD); plugin_load_cb(env, addr, oi); return ret; } @@ -2658,7 +2656,7 @@ uint16_t cpu_ldw_mmu(CPUArchState *env, abi_ptr addr, uint16_t ret; =20 tcg_debug_assert((get_memop(oi) & MO_SIZE) =3D=3D MO_16); - ret =3D do_ld2_mmu(env, addr, oi, ra, MMU_DATA_LOAD); + ret =3D do_ld2_mmu(env_cpu(env), addr, oi, ra, MMU_DATA_LOAD); plugin_load_cb(env, addr, oi); return ret; } @@ -2669,7 +2667,7 @@ uint32_t cpu_ldl_mmu(CPUArchState *env, abi_ptr addr, uint32_t ret; =20 tcg_debug_assert((get_memop(oi) & MO_SIZE) =3D=3D MO_32); - ret =3D do_ld4_mmu(env, addr, oi, ra, MMU_DATA_LOAD); + ret =3D do_ld4_mmu(env_cpu(env), addr, oi, ra, MMU_DATA_LOAD); plugin_load_cb(env, addr, oi); return ret; } @@ -2680,7 +2678,7 @@ uint64_t cpu_ldq_mmu(CPUArchState *env, abi_ptr addr, uint64_t ret; =20 tcg_debug_assert((get_memop(oi) & MO_SIZE) =3D=3D MO_64); - ret =3D do_ld8_mmu(env, addr, oi, ra, MMU_DATA_LOAD); + ret =3D do_ld8_mmu(env_cpu(env), addr, oi, ra, MMU_DATA_LOAD); plugin_load_cb(env, addr, oi); return ret; } @@ -2691,7 +2689,7 @@ Int128 cpu_ld16_mmu(CPUArchState *env, abi_ptr addr, Int128 ret; =20 tcg_debug_assert((get_memop(oi) & MO_SIZE) =3D=3D MO_128); - ret =3D do_ld16_mmu(env, addr, oi, ra); + ret =3D do_ld16_mmu(env_cpu(env), addr, oi, ra); plugin_load_cb(env, addr, oi); return ret; } @@ -2702,7 +2700,7 @@ Int128 cpu_ld16_mmu(CPUArchState *env, abi_ptr addr, =20 /** * do_st_mmio_leN: - * @env: cpu context + * @cpu: generic cpu state * @full: page parameters * @val_le: data to store * @addr: virtual address @@ -2715,7 +2713,7 @@ Int128 cpu_ld16_mmu(CPUArchState *env, abi_ptr addr, * The bytes to store are extracted in little-endian order from @val_le; * return the bytes of @val_le beyond @p->size that have not been stored. */ -static uint64_t do_st_mmio_leN(CPUArchState *env, CPUTLBEntryFull *full, +static uint64_t do_st_mmio_leN(CPUState *cpu, CPUTLBEntryFull *full, uint64_t val_le, vaddr addr, int size, int mmu_idx, uintptr_t ra) { @@ -2728,26 +2726,26 @@ static uint64_t do_st_mmio_leN(CPUArchState *env, C= PUTLBEntryFull *full, case 3: case 5: case 7: - io_writex(env, full, mmu_idx, val_le, addr, ra, MO_UB); + io_writex(cpu, full, mmu_idx, val_le, addr, ra, MO_UB); val_le >>=3D 8; size -=3D 1; addr +=3D 1; break; case 2: case 6: - io_writex(env, full, mmu_idx, val_le, addr, ra, MO_LEUW); + io_writex(cpu, full, mmu_idx, val_le, addr, ra, MO_LEUW); val_le >>=3D 16; size -=3D 2; addr +=3D 2; break; case 4: - io_writex(env, full, mmu_idx, val_le, addr, ra, MO_LEUL); + io_writex(cpu, full, mmu_idx, val_le, addr, ra, MO_LEUL); val_le >>=3D 32; size -=3D 4; addr +=3D 4; break; case 0: - io_writex(env, full, mmu_idx, val_le, addr, ra, MO_LEUQ); + io_writex(cpu, full, mmu_idx, val_le, addr, ra, MO_LEUQ); return 0; default: qemu_build_not_reached(); @@ -2760,7 +2758,7 @@ static uint64_t do_st_mmio_leN(CPUArchState *env, CPU= TLBEntryFull *full, /* * Wrapper for the above. */ -static uint64_t do_st_leN(CPUArchState *env, MMULookupPageData *p, +static uint64_t do_st_leN(CPUState *cpu, MMULookupPageData *p, uint64_t val_le, int mmu_idx, MemOp mop, uintptr_t ra) { @@ -2769,7 +2767,7 @@ static uint64_t do_st_leN(CPUArchState *env, MMULooku= pPageData *p, =20 if (unlikely(p->flags & TLB_MMIO)) { QEMU_IOTHREAD_LOCK_GUARD(); - return do_st_mmio_leN(env, p->full, val_le, p->addr, + return do_st_mmio_leN(cpu, p->full, val_le, p->addr, p->size, mmu_idx, ra); } else if (unlikely(p->flags & TLB_DISCARD_WRITE)) { return val_le >> (p->size * 8); @@ -2797,7 +2795,7 @@ static uint64_t do_st_leN(CPUArchState *env, MMULooku= pPageData *p, } else if (HAVE_al8) { return store_whole_le8(p->haddr, p->size, val_le); } else { - cpu_loop_exit_atomic(env_cpu(env), ra); + cpu_loop_exit_atomic(cpu, ra); } } /* fall through */ @@ -2815,7 +2813,7 @@ static uint64_t do_st_leN(CPUArchState *env, MMULooku= pPageData *p, /* * Wrapper for the above, for 8 < size < 16. */ -static uint64_t do_st16_leN(CPUArchState *env, MMULookupPageData *p, +static uint64_t do_st16_leN(CPUState *cpu, MMULookupPageData *p, Int128 val_le, int mmu_idx, MemOp mop, uintptr_t ra) { @@ -2824,9 +2822,9 @@ static uint64_t do_st16_leN(CPUArchState *env, MMULoo= kupPageData *p, =20 if (unlikely(p->flags & TLB_MMIO)) { QEMU_IOTHREAD_LOCK_GUARD(); - do_st_mmio_leN(env, p->full, int128_getlo(val_le), + do_st_mmio_leN(cpu, p->full, int128_getlo(val_le), p->addr, 8, mmu_idx, ra); - return do_st_mmio_leN(env, p->full, int128_gethi(val_le), + return do_st_mmio_leN(cpu, p->full, int128_gethi(val_le), p->addr + 8, size - 8, mmu_idx, ra); } else if (unlikely(p->flags & TLB_DISCARD_WRITE)) { return int128_gethi(val_le) >> ((size - 8) * 8); @@ -2846,7 +2844,7 @@ static uint64_t do_st16_leN(CPUArchState *env, MMULoo= kupPageData *p, case MO_ATOM_WITHIN16_PAIR: /* Since size > 8, this is the half that must be atomic. */ if (!HAVE_ATOMIC128_RW) { - cpu_loop_exit_atomic(env_cpu(env), ra); + cpu_loop_exit_atomic(cpu, ra); } return store_whole_le16(p->haddr, p->size, val_le); =20 @@ -2867,11 +2865,11 @@ static uint64_t do_st16_leN(CPUArchState *env, MMUL= ookupPageData *p, } } =20 -static void do_st_1(CPUArchState *env, MMULookupPageData *p, uint8_t val, +static void do_st_1(CPUState *cpu, MMULookupPageData *p, uint8_t val, int mmu_idx, uintptr_t ra) { if (unlikely(p->flags & TLB_MMIO)) { - io_writex(env, p->full, mmu_idx, val, p->addr, ra, MO_UB); + io_writex(cpu, p->full, mmu_idx, val, p->addr, ra, MO_UB); } else if (unlikely(p->flags & TLB_DISCARD_WRITE)) { /* nothing */ } else { @@ -2879,7 +2877,7 @@ static void do_st_1(CPUArchState *env, MMULookupPageD= ata *p, uint8_t val, } } =20 -static void do_st_2(CPUArchState *env, MMULookupPageData *p, uint16_t val, +static void do_st_2(CPUState *cpu, MMULookupPageData *p, uint16_t val, int mmu_idx, MemOp memop, uintptr_t ra) { if (unlikely(p->flags & TLB_MMIO)) { @@ -2887,7 +2885,7 @@ static void do_st_2(CPUArchState *env, MMULookupPageD= ata *p, uint16_t val, val =3D bswap16(val); } QEMU_IOTHREAD_LOCK_GUARD(); - do_st_mmio_leN(env, p->full, val, p->addr, 2, mmu_idx, ra); + do_st_mmio_leN(cpu, p->full, val, p->addr, 2, mmu_idx, ra); } else if (unlikely(p->flags & TLB_DISCARD_WRITE)) { /* nothing */ } else { @@ -2895,11 +2893,11 @@ static void do_st_2(CPUArchState *env, MMULookupPag= eData *p, uint16_t val, if (memop & MO_BSWAP) { val =3D bswap16(val); } - store_atom_2(env, ra, p->haddr, memop, val); + store_atom_2(cpu_env(cpu), ra, p->haddr, memop, val); } } =20 -static void do_st_4(CPUArchState *env, MMULookupPageData *p, uint32_t val, +static void do_st_4(CPUState *cpu, MMULookupPageData *p, uint32_t val, int mmu_idx, MemOp memop, uintptr_t ra) { if (unlikely(p->flags & TLB_MMIO)) { @@ -2907,7 +2905,7 @@ static void do_st_4(CPUArchState *env, MMULookupPageD= ata *p, uint32_t val, val =3D bswap32(val); } QEMU_IOTHREAD_LOCK_GUARD(); - do_st_mmio_leN(env, p->full, val, p->addr, 4, mmu_idx, ra); + do_st_mmio_leN(cpu, p->full, val, p->addr, 4, mmu_idx, ra); } else if (unlikely(p->flags & TLB_DISCARD_WRITE)) { /* nothing */ } else { @@ -2915,11 +2913,11 @@ static void do_st_4(CPUArchState *env, MMULookupPag= eData *p, uint32_t val, if (memop & MO_BSWAP) { val =3D bswap32(val); } - store_atom_4(env, ra, p->haddr, memop, val); + store_atom_4(cpu_env(cpu), ra, p->haddr, memop, val); } } =20 -static void do_st_8(CPUArchState *env, MMULookupPageData *p, uint64_t val, +static void do_st_8(CPUState *cpu, MMULookupPageData *p, uint64_t val, int mmu_idx, MemOp memop, uintptr_t ra) { if (unlikely(p->flags & TLB_MMIO)) { @@ -2927,7 +2925,7 @@ static void do_st_8(CPUArchState *env, MMULookupPageD= ata *p, uint64_t val, val =3D bswap64(val); } QEMU_IOTHREAD_LOCK_GUARD(); - do_st_mmio_leN(env, p->full, val, p->addr, 8, mmu_idx, ra); + do_st_mmio_leN(cpu, p->full, val, p->addr, 8, mmu_idx, ra); } else if (unlikely(p->flags & TLB_DISCARD_WRITE)) { /* nothing */ } else { @@ -2935,7 +2933,7 @@ static void do_st_8(CPUArchState *env, MMULookupPageD= ata *p, uint64_t val, if (memop & MO_BSWAP) { val =3D bswap64(val); } - store_atom_8(env, ra, p->haddr, memop, val); + store_atom_8(cpu_env(cpu), ra, p->haddr, memop, val); } } =20 @@ -2947,13 +2945,13 @@ void helper_stb_mmu(CPUArchState *env, uint64_t add= r, uint32_t val, =20 tcg_debug_assert((get_memop(oi) & MO_SIZE) =3D=3D MO_8); cpu_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST); - crosspage =3D mmu_lookup(env, addr, oi, ra, MMU_DATA_STORE, &l); + crosspage =3D mmu_lookup(env_cpu(env), addr, oi, ra, MMU_DATA_STORE, &= l); tcg_debug_assert(!crosspage); =20 - do_st_1(env, &l.page[0], val, l.mmu_idx, ra); + do_st_1(env_cpu(env), &l.page[0], val, l.mmu_idx, ra); } =20 -static void do_st2_mmu(CPUArchState *env, vaddr addr, uint16_t val, +static void do_st2_mmu(CPUState *cpu, vaddr addr, uint16_t val, MemOpIdx oi, uintptr_t ra) { MMULookupLocals l; @@ -2961,9 +2959,9 @@ static void do_st2_mmu(CPUArchState *env, vaddr addr,= uint16_t val, uint8_t a, b; =20 cpu_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST); - crosspage =3D mmu_lookup(env, addr, oi, ra, MMU_DATA_STORE, &l); + crosspage =3D mmu_lookup(cpu, addr, oi, ra, MMU_DATA_STORE, &l); if (likely(!crosspage)) { - do_st_2(env, &l.page[0], val, l.mmu_idx, l.memop, ra); + do_st_2(cpu, &l.page[0], val, l.mmu_idx, l.memop, ra); return; } =20 @@ -2972,27 +2970,27 @@ static void do_st2_mmu(CPUArchState *env, vaddr add= r, uint16_t val, } else { b =3D val, a =3D val >> 8; } - do_st_1(env, &l.page[0], a, l.mmu_idx, ra); - do_st_1(env, &l.page[1], b, l.mmu_idx, ra); + do_st_1(cpu, &l.page[0], a, l.mmu_idx, ra); + do_st_1(cpu, &l.page[1], b, l.mmu_idx, ra); } =20 void helper_stw_mmu(CPUArchState *env, uint64_t addr, uint32_t val, MemOpIdx oi, uintptr_t retaddr) { tcg_debug_assert((get_memop(oi) & MO_SIZE) =3D=3D MO_16); - do_st2_mmu(env, addr, val, oi, retaddr); + do_st2_mmu(env_cpu(env), addr, val, oi, retaddr); } =20 -static void do_st4_mmu(CPUArchState *env, vaddr addr, uint32_t val, +static void do_st4_mmu(CPUState *cpu, vaddr addr, uint32_t val, MemOpIdx oi, uintptr_t ra) { MMULookupLocals l; bool crosspage; =20 cpu_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST); - crosspage =3D mmu_lookup(env, addr, oi, ra, MMU_DATA_STORE, &l); + crosspage =3D mmu_lookup(cpu, addr, oi, ra, MMU_DATA_STORE, &l); if (likely(!crosspage)) { - do_st_4(env, &l.page[0], val, l.mmu_idx, l.memop, ra); + do_st_4(cpu, &l.page[0], val, l.mmu_idx, l.memop, ra); return; } =20 @@ -3000,27 +2998,27 @@ static void do_st4_mmu(CPUArchState *env, vaddr add= r, uint32_t val, if ((l.memop & MO_BSWAP) !=3D MO_LE) { val =3D bswap32(val); } - val =3D do_st_leN(env, &l.page[0], val, l.mmu_idx, l.memop, ra); - (void) do_st_leN(env, &l.page[1], val, l.mmu_idx, l.memop, ra); + val =3D do_st_leN(cpu, &l.page[0], val, l.mmu_idx, l.memop, ra); + (void) do_st_leN(cpu, &l.page[1], val, l.mmu_idx, l.memop, ra); } =20 void helper_stl_mmu(CPUArchState *env, uint64_t addr, uint32_t val, MemOpIdx oi, uintptr_t retaddr) { tcg_debug_assert((get_memop(oi) & MO_SIZE) =3D=3D MO_32); - do_st4_mmu(env, addr, val, oi, retaddr); + do_st4_mmu(env_cpu(env), addr, val, oi, retaddr); } =20 -static void do_st8_mmu(CPUArchState *env, vaddr addr, uint64_t val, +static void do_st8_mmu(CPUState *cpu, vaddr addr, uint64_t val, MemOpIdx oi, uintptr_t ra) { MMULookupLocals l; bool crosspage; =20 cpu_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST); - crosspage =3D mmu_lookup(env, addr, oi, ra, MMU_DATA_STORE, &l); + crosspage =3D mmu_lookup(cpu, addr, oi, ra, MMU_DATA_STORE, &l); if (likely(!crosspage)) { - do_st_8(env, &l.page[0], val, l.mmu_idx, l.memop, ra); + do_st_8(cpu, &l.page[0], val, l.mmu_idx, l.memop, ra); return; } =20 @@ -3028,18 +3026,18 @@ static void do_st8_mmu(CPUArchState *env, vaddr add= r, uint64_t val, if ((l.memop & MO_BSWAP) !=3D MO_LE) { val =3D bswap64(val); } - val =3D do_st_leN(env, &l.page[0], val, l.mmu_idx, l.memop, ra); - (void) do_st_leN(env, &l.page[1], val, l.mmu_idx, l.memop, ra); + val =3D do_st_leN(cpu, &l.page[0], val, l.mmu_idx, l.memop, ra); + (void) do_st_leN(cpu, &l.page[1], val, l.mmu_idx, l.memop, ra); } =20 void helper_stq_mmu(CPUArchState *env, uint64_t addr, uint64_t val, MemOpIdx oi, uintptr_t retaddr) { tcg_debug_assert((get_memop(oi) & MO_SIZE) =3D=3D MO_64); - do_st8_mmu(env, addr, val, oi, retaddr); + do_st8_mmu(env_cpu(env), addr, val, oi, retaddr); } =20 -static void do_st16_mmu(CPUArchState *env, vaddr addr, Int128 val, +static void do_st16_mmu(CPUState *cpu, vaddr addr, Int128 val, MemOpIdx oi, uintptr_t ra) { MMULookupLocals l; @@ -3048,7 +3046,7 @@ static void do_st16_mmu(CPUArchState *env, vaddr addr= , Int128 val, int first; =20 cpu_req_mo(TCG_MO_LD_ST | TCG_MO_ST_ST); - crosspage =3D mmu_lookup(env, addr, oi, ra, MMU_DATA_STORE, &l); + crosspage =3D mmu_lookup(cpu, addr, oi, ra, MMU_DATA_STORE, &l); if (likely(!crosspage)) { if (unlikely(l.page[0].flags & TLB_MMIO)) { if ((l.memop & MO_BSWAP) !=3D MO_LE) { @@ -3057,8 +3055,8 @@ static void do_st16_mmu(CPUArchState *env, vaddr addr= , Int128 val, a =3D int128_getlo(val); b =3D int128_gethi(val); QEMU_IOTHREAD_LOCK_GUARD(); - do_st_mmio_leN(env, l.page[0].full, a, addr, 8, l.mmu_idx, ra); - do_st_mmio_leN(env, l.page[0].full, b, addr + 8, 8, l.mmu_idx,= ra); + do_st_mmio_leN(cpu, l.page[0].full, a, addr, 8, l.mmu_idx, ra); + do_st_mmio_leN(cpu, l.page[0].full, b, addr + 8, 8, l.mmu_idx,= ra); } else if (unlikely(l.page[0].flags & TLB_DISCARD_WRITE)) { /* nothing */ } else { @@ -3066,7 +3064,7 @@ static void do_st16_mmu(CPUArchState *env, vaddr addr= , Int128 val, if (l.memop & MO_BSWAP) { val =3D bswap128(val); } - store_atom_16(env, ra, l.page[0].haddr, l.memop, val); + store_atom_16(cpu_env(cpu), ra, l.page[0].haddr, l.memop, val); } return; } @@ -3083,8 +3081,8 @@ static void do_st16_mmu(CPUArchState *env, vaddr addr= , Int128 val, } else { a =3D int128_getlo(val), b =3D int128_gethi(val); } - do_st_8(env, &l.page[0], a, l.mmu_idx, mop8, ra); - do_st_8(env, &l.page[1], b, l.mmu_idx, mop8, ra); + do_st_8(cpu, &l.page[0], a, l.mmu_idx, mop8, ra); + do_st_8(cpu, &l.page[1], b, l.mmu_idx, mop8, ra); return; } =20 @@ -3092,12 +3090,12 @@ static void do_st16_mmu(CPUArchState *env, vaddr ad= dr, Int128 val, val =3D bswap128(val); } if (first < 8) { - do_st_leN(env, &l.page[0], int128_getlo(val), l.mmu_idx, l.memop, = ra); + do_st_leN(cpu, &l.page[0], int128_getlo(val), l.mmu_idx, l.memop, = ra); val =3D int128_urshift(val, first * 8); - do_st16_leN(env, &l.page[1], val, l.mmu_idx, l.memop, ra); + do_st16_leN(cpu, &l.page[1], val, l.mmu_idx, l.memop, ra); } else { - b =3D do_st16_leN(env, &l.page[0], val, l.mmu_idx, l.memop, ra); - do_st_leN(env, &l.page[1], b, l.mmu_idx, l.memop, ra); + b =3D do_st16_leN(cpu, &l.page[0], val, l.mmu_idx, l.memop, ra); + do_st_leN(cpu, &l.page[1], b, l.mmu_idx, l.memop, ra); } } =20 @@ -3105,7 +3103,7 @@ void helper_st16_mmu(CPUArchState *env, uint64_t addr= , Int128 val, MemOpIdx oi, uintptr_t retaddr) { tcg_debug_assert((get_memop(oi) & MO_SIZE) =3D=3D MO_128); - do_st16_mmu(env, addr, val, oi, retaddr); + do_st16_mmu(env_cpu(env), addr, val, oi, retaddr); } =20 void helper_st_i128(CPUArchState *env, uint64_t addr, Int128 val, MemOpIdx= oi) @@ -3133,7 +3131,7 @@ void cpu_stw_mmu(CPUArchState *env, abi_ptr addr, uin= t16_t val, MemOpIdx oi, uintptr_t retaddr) { tcg_debug_assert((get_memop(oi) & MO_SIZE) =3D=3D MO_16); - do_st2_mmu(env, addr, val, oi, retaddr); + do_st2_mmu(env_cpu(env), addr, val, oi, retaddr); plugin_store_cb(env, addr, oi); } =20 @@ -3141,7 +3139,7 @@ void cpu_stl_mmu(CPUArchState *env, abi_ptr addr, uin= t32_t val, MemOpIdx oi, uintptr_t retaddr) { tcg_debug_assert((get_memop(oi) & MO_SIZE) =3D=3D MO_32); - do_st4_mmu(env, addr, val, oi, retaddr); + do_st4_mmu(env_cpu(env), addr, val, oi, retaddr); plugin_store_cb(env, addr, oi); } =20 @@ -3149,7 +3147,7 @@ void cpu_stq_mmu(CPUArchState *env, abi_ptr addr, uin= t64_t val, MemOpIdx oi, uintptr_t retaddr) { tcg_debug_assert((get_memop(oi) & MO_SIZE) =3D=3D MO_64); - do_st8_mmu(env, addr, val, oi, retaddr); + do_st8_mmu(env_cpu(env), addr, val, oi, retaddr); plugin_store_cb(env, addr, oi); } =20 @@ -3157,7 +3155,7 @@ void cpu_st16_mmu(CPUArchState *env, abi_ptr addr, In= t128 val, MemOpIdx oi, uintptr_t retaddr) { tcg_debug_assert((get_memop(oi) & MO_SIZE) =3D=3D MO_128); - do_st16_mmu(env, addr, val, oi, retaddr); + do_st16_mmu(env_cpu(env), addr, val, oi, retaddr); plugin_store_cb(env, addr, oi); } =20 @@ -3199,47 +3197,47 @@ void cpu_st16_mmu(CPUArchState *env, abi_ptr addr, = Int128 val, uint32_t cpu_ldub_code(CPUArchState *env, abi_ptr addr) { MemOpIdx oi =3D make_memop_idx(MO_UB, cpu_mmu_index(env, true)); - return do_ld1_mmu(env, addr, oi, 0, MMU_INST_FETCH); + return do_ld1_mmu(env_cpu(env), addr, oi, 0, MMU_INST_FETCH); } =20 uint32_t cpu_lduw_code(CPUArchState *env, abi_ptr addr) { MemOpIdx oi =3D make_memop_idx(MO_TEUW, cpu_mmu_index(env, true)); - return do_ld2_mmu(env, addr, oi, 0, MMU_INST_FETCH); + return do_ld2_mmu(env_cpu(env), addr, oi, 0, MMU_INST_FETCH); } =20 uint32_t cpu_ldl_code(CPUArchState *env, abi_ptr addr) { MemOpIdx oi =3D make_memop_idx(MO_TEUL, cpu_mmu_index(env, true)); - return do_ld4_mmu(env, addr, oi, 0, MMU_INST_FETCH); + return do_ld4_mmu(env_cpu(env), addr, oi, 0, MMU_INST_FETCH); } =20 uint64_t cpu_ldq_code(CPUArchState *env, abi_ptr addr) { MemOpIdx oi =3D make_memop_idx(MO_TEUQ, cpu_mmu_index(env, true)); - return do_ld8_mmu(env, addr, oi, 0, MMU_INST_FETCH); + return do_ld8_mmu(env_cpu(env), addr, oi, 0, MMU_INST_FETCH); } =20 uint8_t cpu_ldb_code_mmu(CPUArchState *env, abi_ptr addr, MemOpIdx oi, uintptr_t retaddr) { - return do_ld1_mmu(env, addr, oi, retaddr, MMU_INST_FETCH); + return do_ld1_mmu(env_cpu(env), addr, oi, retaddr, MMU_INST_FETCH); } =20 uint16_t cpu_ldw_code_mmu(CPUArchState *env, abi_ptr addr, MemOpIdx oi, uintptr_t retaddr) { - return do_ld2_mmu(env, addr, oi, retaddr, MMU_INST_FETCH); + return do_ld2_mmu(env_cpu(env), addr, oi, retaddr, MMU_INST_FETCH); } =20 uint32_t cpu_ldl_code_mmu(CPUArchState *env, abi_ptr addr, MemOpIdx oi, uintptr_t retaddr) { - return do_ld4_mmu(env, addr, oi, retaddr, MMU_INST_FETCH); + return do_ld4_mmu(env_cpu(env), addr, oi, retaddr, MMU_INST_FETCH); } =20 uint64_t cpu_ldq_code_mmu(CPUArchState *env, abi_ptr addr, MemOpIdx oi, uintptr_t retaddr) { - return do_ld8_mmu(env, addr, oi, retaddr, MMU_INST_FETCH); + return do_ld8_mmu(env_cpu(env), addr, oi, retaddr, MMU_INST_FETCH); } --=20 2.34.1