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([177.9.182.82]) by smtp.gmail.com with ESMTPSA id p15-20020a0568301d4f00b006af9d8af435sm3991255oth.50.2023.09.12.06.25.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Sep 2023 06:25:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1694525120; x=1695129920; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=voPlcLnCfHA3Pf7+udd5Id15KbD/BVbOGmcjjKXZ6OY=; b=CtnlhadzinQLY3/JfgMk8CtgLF4/FgJMvfOPi7aNMuJAFwPQLOdAyqyEmF/yc80Oid XefRXQ5SSQGagze3+XAZFxIKOFy7o5LdvEzLptfykCQUWZrk0qt+7/bICzhrvm8lgLQE fN07jNe7SKTG5o3crlVBaT9aa65MfQ1JcSJR4dvX9jrBbLZYKaeRgsq9dCZpK4Ea6kR8 auvO9wOD2zJW+2UgFcfmziwt+DOmn3khIRMuQGYS7CQVvWSYTKO5susb+pOBW4ohkF9K u4jPKDOB7mY0J8alnq3LkF8UDPxZ+NTPCADxNkUFtbxV8Fo/wFlZaO+el38W8xpWYcqB C1pQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1694525120; x=1695129920; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=voPlcLnCfHA3Pf7+udd5Id15KbD/BVbOGmcjjKXZ6OY=; b=Fkhu2d6HgYCwoNajCLnsnA0geS1mWiQaMiDlvRwJvlQubq8/tGqnD/4Q4vWcIwTg3/ PZFouXLzOiVnT05hIoVSgkp37gxnwiSO5CvTw2Txk047guxPisntRWKAvcCZKvVlh1En h5tRE3RqIGg37yutwcJ7JCI0yEDRrSVzQDYI14cguqHvQfoLVEsUlbIuMPJk3bxAfFjN Ct2W8JxqvANrOp+FpawPwVLrhydJi8iSGzi5ZGkhzVONcmInrXP3Mkg6hj5srgldLoak ExG+F7hY6Bqcv4uryqDalO5OhVVvUHuuCy0QrIcoWLDAoEfXjlcM2NkuYFt7xV9jkt83 okXg== X-Gm-Message-State: AOJu0Yy38sF9op7uLky7sbHqZdcIxxcPugsLaEBNzIFEAYM9+dhqlBqQ eCdIZ9JXITOmWmi/Sy7dyh97sHvMioA2WYBGd8Q= X-Google-Smtp-Source: AGHT+IEhqrdIM6CvJ6ORoGKoUpIIvmN5JBZm3RczkIarvfEP6iCFej6K8W7juFJmBUoUJ1d5q4pRQg== X-Received: by 2002:a9d:7b57:0:b0:6bd:b0c9:a89 with SMTP id f23-20020a9d7b57000000b006bdb0c90a89mr12116240oto.2.1694525119971; Tue, 12 Sep 2023 06:25:19 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, ajones@ventanamicro.com, philmd@linaro.org, Daniel Henrique Barboza Subject: [PATCH v10 14/20] target/riscv: make CPUCFG() macro public Date: Tue, 12 Sep 2023 10:24:17 -0300 Message-ID: <20230912132423.268494-15-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230912132423.268494-1-dbarboza@ventanamicro.com> References: <20230912132423.268494-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::32a; envelope-from=dbarboza@ventanamicro.com; helo=mail-ot1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1694525242159100001 The RISC-V KVM driver uses a CPUCFG() macro that calculates the offset of a certain field in the struct RISCVCPUConfig. We're going to use this macro in target/riscv/cpu.c as well in the next patches. Make it public. Rename it to CPU_CFG_OFFSET() for more clarity while we're at it. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Reviewed-by: Andrew Jones Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/riscv/cpu.c | 2 +- target/riscv/cpu.h | 2 ++ target/riscv/kvm.c | 8 +++----- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 032fad8e03..85630ac2c1 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -48,7 +48,7 @@ struct isa_ext_data { }; =20 #define ISA_EXT_DATA_ENTRY(_name, _min_ver, _prop) \ - {#_name, _min_ver, offsetof(struct RISCVCPUConfig, _prop)} + {#_name, _min_ver, CPU_CFG_OFFSET(_prop)} =20 /* * From vector_helper.c diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 6316cbcc23..7d6cfb07ea 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -62,6 +62,8 @@ const char *riscv_get_misa_ext_name(uint32_t bit); const char *riscv_get_misa_ext_description(uint32_t bit); =20 +#define CPU_CFG_OFFSET(_prop) offsetof(struct RISCVCPUConfig, _prop) + /* Privileged specification version */ enum { PRIV_VERSION_1_10_0 =3D 0, diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c index c01cfb03f4..14763ec0cd 100644 --- a/target/riscv/kvm.c +++ b/target/riscv/kvm.c @@ -205,10 +205,8 @@ static void kvm_riscv_update_cpu_misa_ext(RISCVCPU *cp= u, CPUState *cs) } } =20 -#define CPUCFG(_prop) offsetof(struct RISCVCPUConfig, _prop) - #define KVM_EXT_CFG(_name, _prop, _reg_id) \ - {.name =3D _name, .offset =3D CPUCFG(_prop), \ + {.name =3D _name, .offset =3D CPU_CFG_OFFSET(_prop), \ .kvm_reg_id =3D _reg_id} =20 static KVMCPUConfig kvm_multi_ext_cfgs[] =3D { @@ -285,13 +283,13 @@ static void kvm_cpu_set_multi_ext_cfg(Object *obj, Vi= sitor *v, =20 static KVMCPUConfig kvm_cbom_blocksize =3D { .name =3D "cbom_blocksize", - .offset =3D CPUCFG(cbom_blocksize), + .offset =3D CPU_CFG_OFFSET(cbom_blocksize), .kvm_reg_id =3D KVM_REG_RISCV_CONFIG_REG(zicbom_block_size) }; =20 static KVMCPUConfig kvm_cboz_blocksize =3D { .name =3D "cboz_blocksize", - .offset =3D CPUCFG(cboz_blocksize), + .offset =3D CPU_CFG_OFFSET(cboz_blocksize), .kvm_reg_id =3D KVM_REG_RISCV_CONFIG_REG(zicboz_block_size) }; =20 --=20 2.41.0