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From: Alistair Francis <alistair23@gmail.com>
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To: qemu-devel@nongnu.org
Cc: alistair23@gmail.com, Tommy Wu <tommy.wu@sifive.com>,
Frank Chang <frank.chang@sifive.com>,
Alistair Francis <alistair.francis@wdc.com>
Subject: [PULL v2 44/45] target/riscv: Align the AIA model to v1.0 ratified
spec
Date: Mon, 11 Sep 2023 16:43:19 +1000
Message-ID: <20230911064320.939791-45-alistair.francis@wdc.com>
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From: Tommy Wu <tommy.wu@sifive.com>
According to the new spec, when vsiselect has a reserved value, attempts
from M-mode or HS-mode to access vsireg, or from VS-mode to access
sireg, should preferably raise an illegal instruction exception.
Signed-off-by: Tommy Wu <tommy.wu@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Message-ID: <20230816061647.600672-1-tommy.wu@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/csr.c | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 63c3b0d9fc..68eecc3c96 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -1684,7 +1684,7 @@ static int rmw_iprio(target_ulong xlen,
static int rmw_xireg(CPURISCVState *env, int csrno, target_ulong *val,
target_ulong new_val, target_ulong wr_mask)
{
- bool virt;
+ bool virt, isel_reserved;
uint8_t *iprio;
int ret =3D -EINVAL;
target_ulong priv, isel, vgein;
@@ -1694,6 +1694,7 @@ static int rmw_xireg(CPURISCVState *env, int csrno, t=
arget_ulong *val,
=20
/* Decode register details from CSR number */
virt =3D false;
+ isel_reserved =3D false;
switch (csrno) {
case CSR_MIREG:
iprio =3D env->miprio;
@@ -1738,11 +1739,13 @@ static int rmw_xireg(CPURISCVState *env, int csrno,=
target_ulong *val,
riscv_cpu_mxl_bits(env)),
val, new_val, wr_mask);
}
+ } else {
+ isel_reserved =3D true;
}
=20
done:
if (ret) {
- return (env->virt_enabled && virt) ?
+ return (env->virt_enabled && virt && !isel_reserved) ?
RISCV_EXCP_VIRT_INSTRUCTION_FAULT : RISCV_EXCP_ILLEGAL_INST;
}
return RISCV_EXCP_NONE;
--=20
2.41.0