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From: Alistair Francis <alistair23@gmail.com>
X-Google-Original-From: Alistair Francis <alistair.francis@wdc.com>
To: qemu-devel@nongnu.org
Cc: alistair23@gmail.com, Akihiko Odaki <akihiko.odaki@daynix.com>,
=?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= <philmd@linaro.org>,
LIU Zhiwei <zhiwei_liu@linux.alibaba.com>,
Alistair Francis <alistair.francis@wdc.com>
Subject: [PULL v2 42/45] target/riscv: Allocate itrigger timers only once
Date: Mon, 11 Sep 2023 16:43:17 +1000
Message-ID: <20230911064320.939791-43-alistair.francis@wdc.com>
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From: Akihiko Odaki <akihiko.odaki@daynix.com>
riscv_trigger_init() had been called on reset events that can happen
several times for a CPU and it allocated timers for itrigger. If old
timers were present, they were simply overwritten by the new timers,
resulting in a memory leak.
Divide riscv_trigger_init() into two functions, namely
riscv_trigger_realize() and riscv_trigger_reset() and call them in
appropriate timing. The timer allocation will happen only once for a
CPU in riscv_trigger_realize().
Fixes: 5a4ae64cac ("target/riscv: Add itrigger support when icount is enabl=
ed")
Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Reviewed-by: Philippe Mathieu-Daud=C3=A9 <philmd@linaro.org>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20230818034059.9146-1-akihiko.odaki@daynix.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/debug.h | 3 ++-
target/riscv/cpu.c | 8 +++++++-
target/riscv/debug.c | 15 ++++++++++++---
3 files changed, 21 insertions(+), 5 deletions(-)
diff --git a/target/riscv/debug.h b/target/riscv/debug.h
index c471748d5a..5794aa6ee5 100644
--- a/target/riscv/debug.h
+++ b/target/riscv/debug.h
@@ -143,7 +143,8 @@ void riscv_cpu_debug_excp_handler(CPUState *cs);
bool riscv_cpu_debug_check_breakpoint(CPUState *cs);
bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp);
=20
-void riscv_trigger_init(CPURISCVState *env);
+void riscv_trigger_realize(CPURISCVState *env);
+void riscv_trigger_reset_hold(CPURISCVState *env);
=20
bool riscv_itrigger_enabled(CPURISCVState *env);
void riscv_itrigger_update_priv(CPURISCVState *env);
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index bf0912014e..f227c7664e 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -926,7 +926,7 @@ static void riscv_cpu_reset_hold(Object *obj)
=20
#ifndef CONFIG_USER_ONLY
if (cpu->cfg.debug) {
- riscv_trigger_init(env);
+ riscv_trigger_reset_hold(env);
}
=20
if (kvm_enabled()) {
@@ -1525,6 +1525,12 @@ static void riscv_cpu_realize(DeviceState *dev, Erro=
r **errp)
=20
riscv_cpu_register_gdb_regs_for_features(cs);
=20
+#ifndef CONFIG_USER_ONLY
+ if (cpu->cfg.debug) {
+ riscv_trigger_realize(&cpu->env);
+ }
+#endif
+
qemu_init_vcpu(cs);
cpu_reset(cs);
=20
diff --git a/target/riscv/debug.c b/target/riscv/debug.c
index 211f5921b6..4945d1a1f2 100644
--- a/target/riscv/debug.c
+++ b/target/riscv/debug.c
@@ -903,7 +903,17 @@ bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CP=
UWatchpoint *wp)
return false;
}
=20
-void riscv_trigger_init(CPURISCVState *env)
+void riscv_trigger_realize(CPURISCVState *env)
+{
+ int i;
+
+ for (i =3D 0; i < RV_MAX_TRIGGERS; i++) {
+ env->itrigger_timer[i] =3D timer_new_ns(QEMU_CLOCK_VIRTUAL,
+ riscv_itrigger_timer_cb, env=
);
+ }
+}
+
+void riscv_trigger_reset_hold(CPURISCVState *env)
{
target_ulong tdata1 =3D build_tdata1(env, TRIGGER_TYPE_AD_MATCH, 0, 0);
int i;
@@ -928,7 +938,6 @@ void riscv_trigger_init(CPURISCVState *env)
env->tdata3[i] =3D 0;
env->cpu_breakpoint[i] =3D NULL;
env->cpu_watchpoint[i] =3D NULL;
- env->itrigger_timer[i] =3D timer_new_ns(QEMU_CLOCK_VIRTUAL,
- riscv_itrigger_timer_cb, env=
);
+ timer_del(env->itrigger_timer[i]);
}
}
--=20
2.41.0