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From: Alistair Francis <alistair23@gmail.com>
X-Google-Original-From: Alistair Francis <alistair.francis@wdc.com>
To: qemu-devel@nongnu.org
Cc: alistair23@gmail.com, Yong-Xuan Wang <yongxuan.wang@sifive.com>,
Jim Shu <jim.shu@sifive.com>,
Daniel Henrique Barboza <dbarboza@ventanamicro.com>,
Andrew Jones <ajones@ventanamicro.com>,
Alistair Francis <alistair.francis@wdc.com>
Subject: [PULL v2 32/45] target/riscv: update APLIC and IMSIC to support KVM
AIA
Date: Mon, 11 Sep 2023 16:43:07 +1000
Message-ID: <20230911064320.939791-33-alistair.francis@wdc.com>
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From: Yong-Xuan Wang <yongxuan.wang@sifive.com>
KVM AIA can't emulate APLIC only. When "aia=3Daplic" parameter is passed,
APLIC devices is emulated by QEMU. For "aia=3Daplic-imsic", remove the
mmio operations of APLIC when using KVM AIA and send wired interrupt
signal via KVM_IRQ_LINE API.
After KVM AIA enabled, MSI messages are delivered by KVM_SIGNAL_MSI API
when the IMSICs receive mmio write requests.
Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com>
Reviewed-by: Jim Shu <jim.shu@sifive.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Message-ID: <20230727102439.22554-5-yongxuan.wang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/intc/riscv_aplic.c | 56 ++++++++++++++++++++++++++++++-------------
hw/intc/riscv_imsic.c | 25 +++++++++++++++----
2 files changed, 61 insertions(+), 20 deletions(-)
diff --git a/hw/intc/riscv_aplic.c b/hw/intc/riscv_aplic.c
index 4bdc6a5d1a..592c3ce768 100644
--- a/hw/intc/riscv_aplic.c
+++ b/hw/intc/riscv_aplic.c
@@ -31,6 +31,7 @@
#include "hw/irq.h"
#include "target/riscv/cpu.h"
#include "sysemu/sysemu.h"
+#include "sysemu/kvm.h"
#include "migration/vmstate.h"
=20
#define APLIC_MAX_IDC (1UL << 14)
@@ -148,6 +149,15 @@
=20
#define APLIC_IDC_CLAIMI 0x1c
=20
+/*
+ * KVM AIA only supports APLIC MSI, fallback to QEMU emulation if we want =
to use
+ * APLIC Wired.
+ */
+static bool is_kvm_aia(bool msimode)
+{
+ return kvm_irqchip_in_kernel() && msimode;
+}
+
static uint32_t riscv_aplic_read_input_word(RISCVAPLICState *aplic,
uint32_t word)
{
@@ -471,6 +481,11 @@ static uint32_t riscv_aplic_idc_claimi(RISCVAPLICState=
*aplic, uint32_t idc)
return topi;
}
=20
+static void riscv_kvm_aplic_request(void *opaque, int irq, int level)
+{
+ kvm_set_irq(kvm_state, irq, !!level);
+}
+
static void riscv_aplic_request(void *opaque, int irq, int level)
{
bool update =3D false;
@@ -801,29 +816,35 @@ static void riscv_aplic_realize(DeviceState *dev, Err=
or **errp)
uint32_t i;
RISCVAPLICState *aplic =3D RISCV_APLIC(dev);
=20
- aplic->bitfield_words =3D (aplic->num_irqs + 31) >> 5;
- aplic->sourcecfg =3D g_new0(uint32_t, aplic->num_irqs);
- aplic->state =3D g_new0(uint32_t, aplic->num_irqs);
- aplic->target =3D g_new0(uint32_t, aplic->num_irqs);
- if (!aplic->msimode) {
- for (i =3D 0; i < aplic->num_irqs; i++) {
- aplic->target[i] =3D 1;
+ if (!is_kvm_aia(aplic->msimode)) {
+ aplic->bitfield_words =3D (aplic->num_irqs + 31) >> 5;
+ aplic->sourcecfg =3D g_new0(uint32_t, aplic->num_irqs);
+ aplic->state =3D g_new0(uint32_t, aplic->num_irqs);
+ aplic->target =3D g_new0(uint32_t, aplic->num_irqs);
+ if (!aplic->msimode) {
+ for (i =3D 0; i < aplic->num_irqs; i++) {
+ aplic->target[i] =3D 1;
+ }
}
- }
- aplic->idelivery =3D g_new0(uint32_t, aplic->num_harts);
- aplic->iforce =3D g_new0(uint32_t, aplic->num_harts);
- aplic->ithreshold =3D g_new0(uint32_t, aplic->num_harts);
+ aplic->idelivery =3D g_new0(uint32_t, aplic->num_harts);
+ aplic->iforce =3D g_new0(uint32_t, aplic->num_harts);
+ aplic->ithreshold =3D g_new0(uint32_t, aplic->num_harts);
=20
- memory_region_init_io(&aplic->mmio, OBJECT(dev), &riscv_aplic_ops, apl=
ic,
- TYPE_RISCV_APLIC, aplic->aperture_size);
- sysbus_init_mmio(SYS_BUS_DEVICE(dev), &aplic->mmio);
+ memory_region_init_io(&aplic->mmio, OBJECT(dev), &riscv_aplic_ops,
+ aplic, TYPE_RISCV_APLIC, aplic->aperture_siz=
e);
+ sysbus_init_mmio(SYS_BUS_DEVICE(dev), &aplic->mmio);
+ }
=20
/*
* Only root APLICs have hardware IRQ lines. All non-root APLICs
* have IRQ lines delegated by their parent APLIC.
*/
if (!aplic->parent) {
- qdev_init_gpio_in(dev, riscv_aplic_request, aplic->num_irqs);
+ if (is_kvm_aia(aplic->msimode)) {
+ qdev_init_gpio_in(dev, riscv_kvm_aplic_request, aplic->num_irq=
s);
+ } else {
+ qdev_init_gpio_in(dev, riscv_aplic_request, aplic->num_irqs);
+ }
}
=20
/* Create output IRQ lines for non-MSI mode */
@@ -958,7 +979,10 @@ DeviceState *riscv_aplic_create(hwaddr addr, hwaddr si=
ze,
qdev_prop_set_bit(dev, "mmode", mmode);
=20
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
- sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);
+
+ if (!is_kvm_aia(msimode)) {
+ sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);
+ }
=20
if (parent) {
riscv_aplic_add_child(parent, dev);
diff --git a/hw/intc/riscv_imsic.c b/hw/intc/riscv_imsic.c
index fea3385b51..760dbddcf7 100644
--- a/hw/intc/riscv_imsic.c
+++ b/hw/intc/riscv_imsic.c
@@ -32,6 +32,7 @@
#include "target/riscv/cpu.h"
#include "target/riscv/cpu_bits.h"
#include "sysemu/sysemu.h"
+#include "sysemu/kvm.h"
#include "migration/vmstate.h"
=20
#define IMSIC_MMIO_PAGE_LE 0x00
@@ -283,6 +284,20 @@ static void riscv_imsic_write(void *opaque, hwaddr add=
r, uint64_t value,
goto err;
}
=20
+#if defined(CONFIG_KVM)
+ if (kvm_irqchip_in_kernel()) {
+ struct kvm_msi msi;
+
+ msi.address_lo =3D extract64(imsic->mmio.addr + addr, 0, 32);
+ msi.address_hi =3D extract64(imsic->mmio.addr + addr, 32, 32);
+ msi.data =3D le32_to_cpu(value);
+
+ kvm_vm_ioctl(kvm_state, KVM_SIGNAL_MSI, &msi);
+
+ return;
+ }
+#endif
+
/* Writes only supported for MSI little-endian registers */
page =3D addr >> IMSIC_MMIO_PAGE_SHIFT;
if ((addr & (IMSIC_MMIO_PAGE_SZ - 1)) =3D=3D IMSIC_MMIO_PAGE_LE) {
@@ -320,10 +335,12 @@ static void riscv_imsic_realize(DeviceState *dev, Err=
or **errp)
CPUState *cpu =3D cpu_by_arch_id(imsic->hartid);
CPURISCVState *env =3D cpu ? cpu->env_ptr : NULL;
=20
- imsic->num_eistate =3D imsic->num_pages * imsic->num_irqs;
- imsic->eidelivery =3D g_new0(uint32_t, imsic->num_pages);
- imsic->eithreshold =3D g_new0(uint32_t, imsic->num_pages);
- imsic->eistate =3D g_new0(uint32_t, imsic->num_eistate);
+ if (!kvm_irqchip_in_kernel()) {
+ imsic->num_eistate =3D imsic->num_pages * imsic->num_irqs;
+ imsic->eidelivery =3D g_new0(uint32_t, imsic->num_pages);
+ imsic->eithreshold =3D g_new0(uint32_t, imsic->num_pages);
+ imsic->eistate =3D g_new0(uint32_t, imsic->num_eistate);
+ }
=20
memory_region_init_io(&imsic->mmio, OBJECT(dev), &riscv_imsic_ops,
imsic, TYPE_RISCV_IMSIC,
--=20
2.41.0