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From: Alistair Francis <alistair23@gmail.com>
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To: qemu-devel@nongnu.org
Cc: alistair23@gmail.com, LIU Zhiwei <zhiwei_liu@linux.alibaba.com>,
Daniel Henrique Barboza <dbarboza@ventanamicro.com>,
Weiwei Li <liweiwei@iscas.ac.cn>,
Alistair Francis <alistair.francis@wdc.com>
Subject: [PULL v2 25/45] target/riscv: Fix zfa fleq.d and fltq.d
Date: Mon, 11 Sep 2023 16:43:00 +1000
Message-ID: <20230911064320.939791-26-alistair.francis@wdc.com>
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From: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Commit a47842d ("riscv: Add support for the Zfa extension") implemented the=
zfa extension.
However, it has some typos for fleq.d and fltq.d. Both of them misused the =
fltq.s
helper function.
Fixes: a47842d ("riscv: Add support for the Zfa extension")
Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Message-ID: <20230728003906.768-1-zhiwei_liu@linux.alibaba.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/insn_trans/trans_rvzfa.c.inc | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvzfa.c.inc b/target/riscv/insn_=
trans/trans_rvzfa.c.inc
index 2c715af3e5..0fdd2698f6 100644
--- a/target/riscv/insn_trans/trans_rvzfa.c.inc
+++ b/target/riscv/insn_trans/trans_rvzfa.c.inc
@@ -470,7 +470,7 @@ bool trans_fleq_d(DisasContext *ctx, arg_fleq_d *a)
TCGv_i64 src1 =3D get_fpr_hs(ctx, a->rs1);
TCGv_i64 src2 =3D get_fpr_hs(ctx, a->rs2);
=20
- gen_helper_fltq_s(dest, cpu_env, src1, src2);
+ gen_helper_fleq_d(dest, cpu_env, src1, src2);
gen_set_gpr(ctx, a->rd, dest);
return true;
}
@@ -485,7 +485,7 @@ bool trans_fltq_d(DisasContext *ctx, arg_fltq_d *a)
TCGv_i64 src1 =3D get_fpr_hs(ctx, a->rs1);
TCGv_i64 src2 =3D get_fpr_hs(ctx, a->rs2);
=20
- gen_helper_fltq_s(dest, cpu_env, src1, src2);
+ gen_helper_fltq_d(dest, cpu_env, src1, src2);
gen_set_gpr(ctx, a->rd, dest);
return true;
}
--=20
2.41.0